Rohan - COG4050 and ADXL355 Tilt sensing
Dependents: COG4050_adxl355_tilt COG4050_adxl355_tilt COG4050_adxl355_tilt_4050
Fork of ADXL355 by
ADXL355.h@1:e80c97768af4, 2018-08-21 (annotated)
- Committer:
- RGurav
- Date:
- Tue Aug 21 13:25:06 2018 +0000
- Revision:
- 1:e80c97768af4
- Parent:
- 0:1b8d65be0eef
COG4050 and ADXL355 Tilt sensing
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
RGurav | 0:1b8d65be0eef | 1 | |
RGurav | 0:1b8d65be0eef | 2 | #ifndef ADXL355_H_ |
RGurav | 0:1b8d65be0eef | 3 | #define ADXL355_H_ |
RGurav | 0:1b8d65be0eef | 4 | |
RGurav | 0:1b8d65be0eef | 5 | class ADXL355 |
RGurav | 0:1b8d65be0eef | 6 | { |
RGurav | 0:1b8d65be0eef | 7 | public: |
RGurav | 0:1b8d65be0eef | 8 | // -------------------------- // |
RGurav | 0:1b8d65be0eef | 9 | // CONST AND VARIABLES // |
RGurav | 0:1b8d65be0eef | 10 | // -------------------------- // |
RGurav | 0:1b8d65be0eef | 11 | typedef struct { |
RGurav | 0:1b8d65be0eef | 12 | // sensitivity |
RGurav | 0:1b8d65be0eef | 13 | float S[2][2]; |
RGurav | 0:1b8d65be0eef | 14 | float St; |
RGurav | 0:1b8d65be0eef | 15 | // 0g offset |
RGurav | 0:1b8d65be0eef | 16 | float B[2][0]; |
RGurav | 0:1b8d65be0eef | 17 | } ADXL355_calibdata_t; |
RGurav | 0:1b8d65be0eef | 18 | ADXL355_calibdata_t calib_data; |
RGurav | 0:1b8d65be0eef | 19 | // gravity filed vectors |
RGurav | 0:1b8d65be0eef | 20 | const static float t_sens = -9.05; |
RGurav | 0:1b8d65be0eef | 21 | const static float t_bias = 1852; |
RGurav | 0:1b8d65be0eef | 22 | float axis355_sens; |
RGurav | 0:1b8d65be0eef | 23 | float axis357_sens; |
RGurav | 0:1b8d65be0eef | 24 | // -------------------------- // |
RGurav | 0:1b8d65be0eef | 25 | // REGISTERS // |
RGurav | 0:1b8d65be0eef | 26 | // -------------------------- // |
RGurav | 0:1b8d65be0eef | 27 | typedef enum { |
RGurav | 0:1b8d65be0eef | 28 | DEVID_AD = 0x00, |
RGurav | 0:1b8d65be0eef | 29 | DEVID_MST = 0x01, |
RGurav | 0:1b8d65be0eef | 30 | PARTID = 0x02, |
RGurav | 0:1b8d65be0eef | 31 | REVID = 0x03, |
RGurav | 0:1b8d65be0eef | 32 | STATUS = 0x04, |
RGurav | 0:1b8d65be0eef | 33 | FIFO_ENTRIES = 0x05, |
RGurav | 0:1b8d65be0eef | 34 | TEMP2 = 0x06, |
RGurav | 0:1b8d65be0eef | 35 | TEMP1 = 0x07, |
RGurav | 0:1b8d65be0eef | 36 | XDATA3 = 0x08, |
RGurav | 0:1b8d65be0eef | 37 | XDATA2 = 0x09, |
RGurav | 0:1b8d65be0eef | 38 | XDATA1 = 0x0A, |
RGurav | 0:1b8d65be0eef | 39 | YDATA3 = 0x0B, |
RGurav | 0:1b8d65be0eef | 40 | YDATA2 = 0x0C, |
RGurav | 0:1b8d65be0eef | 41 | YDATA1 = 0x0D, |
RGurav | 0:1b8d65be0eef | 42 | ZDATA3 = 0x0E, |
RGurav | 0:1b8d65be0eef | 43 | ZDATA2 = 0x0F, |
RGurav | 0:1b8d65be0eef | 44 | ZDATA1 = 0x10, |
RGurav | 0:1b8d65be0eef | 45 | FIFO_DATA = 0x11, |
RGurav | 0:1b8d65be0eef | 46 | OFFSET_X_H = 0x1E, |
RGurav | 0:1b8d65be0eef | 47 | OFFSET_X_L = 0x1F, |
RGurav | 0:1b8d65be0eef | 48 | OFFSET_Y_H = 0x20, |
RGurav | 0:1b8d65be0eef | 49 | OFFSET_Y_L = 0x21, |
RGurav | 0:1b8d65be0eef | 50 | OFFSET_Z_H = 0x22, |
RGurav | 0:1b8d65be0eef | 51 | OFFSET_Z_L = 0x23, |
RGurav | 0:1b8d65be0eef | 52 | ACT_EN = 0x24, |
RGurav | 0:1b8d65be0eef | 53 | ACT_THRESH_H = 0x25, |
RGurav | 0:1b8d65be0eef | 54 | ACT_THRESH_L = 0x26, |
RGurav | 0:1b8d65be0eef | 55 | ACT_COUNT = 0x27, |
RGurav | 0:1b8d65be0eef | 56 | FILTER = 0x28, |
RGurav | 0:1b8d65be0eef | 57 | FIFO_SAMPLES = 0x29, |
RGurav | 0:1b8d65be0eef | 58 | INT_MAP = 0x2A, |
RGurav | 0:1b8d65be0eef | 59 | SYNC = 0x2B, |
RGurav | 0:1b8d65be0eef | 60 | RANGE = 0x2C, |
RGurav | 0:1b8d65be0eef | 61 | POWER_CTL = 0x2D, |
RGurav | 0:1b8d65be0eef | 62 | SELF_TEST = 0x2E, |
RGurav | 0:1b8d65be0eef | 63 | RESET = 0x2F |
RGurav | 0:1b8d65be0eef | 64 | } ADXL355_register_t; |
RGurav | 0:1b8d65be0eef | 65 | // -------------------------- // |
RGurav | 0:1b8d65be0eef | 66 | // REGISTERS - DEFAULT VALUES // |
RGurav | 0:1b8d65be0eef | 67 | // -------------------------- // |
RGurav | 0:1b8d65be0eef | 68 | // Modes - POWER_CTL |
RGurav | 0:1b8d65be0eef | 69 | typedef enum { |
RGurav | 0:1b8d65be0eef | 70 | DRDY_OFF = 0x04, |
RGurav | 0:1b8d65be0eef | 71 | TEMP_OFF = 0x02, |
RGurav | 0:1b8d65be0eef | 72 | STANDBY = 0x01, |
RGurav | 0:1b8d65be0eef | 73 | MEASUREMENT = 0x00 |
RGurav | 0:1b8d65be0eef | 74 | } ADXL355_modes_t; |
RGurav | 0:1b8d65be0eef | 75 | // Activate Threshold - ACT_EN |
RGurav | 0:1b8d65be0eef | 76 | typedef enum { |
RGurav | 0:1b8d65be0eef | 77 | ACT_Z = 0x04, |
RGurav | 0:1b8d65be0eef | 78 | ACT_Y = 0x02, |
RGurav | 0:1b8d65be0eef | 79 | ACT_X = 0x01 |
RGurav | 0:1b8d65be0eef | 80 | } ADXL355_act_ctl_t; |
RGurav | 0:1b8d65be0eef | 81 | // High-Pass and Low-Pass Filter - FILTER |
RGurav | 0:1b8d65be0eef | 82 | typedef enum { |
RGurav | 0:1b8d65be0eef | 83 | HPFOFF = 0x00, |
RGurav | 0:1b8d65be0eef | 84 | HPF247 = 0x10, |
RGurav | 0:1b8d65be0eef | 85 | HPF62 = 0x20, |
RGurav | 0:1b8d65be0eef | 86 | HPF15 = 0x30, |
RGurav | 0:1b8d65be0eef | 87 | HPF3 = 0x40, |
RGurav | 0:1b8d65be0eef | 88 | HPF09 = 0x50, |
RGurav | 0:1b8d65be0eef | 89 | HPF02 = 0x60, |
RGurav | 0:1b8d65be0eef | 90 | ODR4000HZ = 0x00, |
RGurav | 0:1b8d65be0eef | 91 | ODR2000HZ = 0x01, |
RGurav | 0:1b8d65be0eef | 92 | ODR1000HZ = 0x02, |
RGurav | 0:1b8d65be0eef | 93 | ODR500HZ = 0x03, |
RGurav | 0:1b8d65be0eef | 94 | ODR250HZ = 0x04, |
RGurav | 0:1b8d65be0eef | 95 | ODR125Hz = 0x05, |
RGurav | 0:1b8d65be0eef | 96 | ODR62HZ = 0x06, |
RGurav | 0:1b8d65be0eef | 97 | ODR31Hz = 0x07, |
RGurav | 0:1b8d65be0eef | 98 | ODR15Hz = 0x08, |
RGurav | 0:1b8d65be0eef | 99 | ODR7Hz = 0x09, |
RGurav | 0:1b8d65be0eef | 100 | ODR3HZ = 0x0A |
RGurav | 0:1b8d65be0eef | 101 | } ADXL355_filter_ctl_t; |
RGurav | 0:1b8d65be0eef | 102 | // External timing register - INT_MAP |
RGurav | 0:1b8d65be0eef | 103 | typedef enum { |
RGurav | 0:1b8d65be0eef | 104 | OVR_EN = 0x04, |
RGurav | 0:1b8d65be0eef | 105 | FULL_EN = 0x02, |
RGurav | 0:1b8d65be0eef | 106 | RDY_EN = 0x01 |
RGurav | 0:1b8d65be0eef | 107 | } ADXL355_intmap_ctl_t; |
RGurav | 0:1b8d65be0eef | 108 | // External timing register - SYNC |
RGurav | 0:1b8d65be0eef | 109 | typedef enum { |
RGurav | 0:1b8d65be0eef | 110 | EXT_CLK = 0x04, |
RGurav | 0:1b8d65be0eef | 111 | INT_SYNC = 0x00, |
RGurav | 0:1b8d65be0eef | 112 | EXT_SYNC_NO_INT = 0x01, |
RGurav | 0:1b8d65be0eef | 113 | EXT_SYNC_INT = 0x02 |
RGurav | 0:1b8d65be0eef | 114 | } ADXL355_sync_ctl_t; |
RGurav | 0:1b8d65be0eef | 115 | // polarity and range - RANGE |
RGurav | 0:1b8d65be0eef | 116 | typedef enum { |
RGurav | 0:1b8d65be0eef | 117 | RANGE2G = 0x01, |
RGurav | 0:1b8d65be0eef | 118 | RANGE4G = 0x02, |
RGurav | 0:1b8d65be0eef | 119 | RANGE8G = 0x03, |
RGurav | 0:1b8d65be0eef | 120 | RANGE10 = 0x01, |
RGurav | 0:1b8d65be0eef | 121 | RANGE20 = 0x02, |
RGurav | 0:1b8d65be0eef | 122 | RANGE40 = 0x03 |
RGurav | 0:1b8d65be0eef | 123 | } ADXL355_range_ctl_t; |
RGurav | 0:1b8d65be0eef | 124 | // self test interrupt - INT |
RGurav | 0:1b8d65be0eef | 125 | typedef enum { |
RGurav | 0:1b8d65be0eef | 126 | ST2 = 0x02, |
RGurav | 0:1b8d65be0eef | 127 | ST1 = 0x01 |
RGurav | 0:1b8d65be0eef | 128 | } ADXL355_int_ctl_t; |
RGurav | 0:1b8d65be0eef | 129 | // -------------------------- // |
RGurav | 0:1b8d65be0eef | 130 | // FUNCTIONS // |
RGurav | 0:1b8d65be0eef | 131 | // -------------------------- // |
RGurav | 0:1b8d65be0eef | 132 | // SPI configuration & constructor |
RGurav | 0:1b8d65be0eef | 133 | ADXL355(PinName cs_pin , PinName MOSI , PinName MISO , PinName SCK ); |
RGurav | 0:1b8d65be0eef | 134 | void frequency(int hz); |
RGurav | 0:1b8d65be0eef | 135 | // Low level SPI bus comm methods |
RGurav | 0:1b8d65be0eef | 136 | void reset(void); |
RGurav | 0:1b8d65be0eef | 137 | void write_reg(ADXL355_register_t reg, uint8_t data); |
RGurav | 0:1b8d65be0eef | 138 | void write_reg_u16(ADXL355_register_t reg, uint16_t data); |
RGurav | 0:1b8d65be0eef | 139 | uint8_t read_reg(ADXL355_register_t reg); |
RGurav | 0:1b8d65be0eef | 140 | uint16_t read_reg_u16(ADXL355_register_t reg); |
RGurav | 0:1b8d65be0eef | 141 | uint32_t read_reg_u20(ADXL355_register_t reg); |
RGurav | 0:1b8d65be0eef | 142 | // ADXL general register R/W methods |
RGurav | 0:1b8d65be0eef | 143 | void set_power_ctl_reg(uint8_t data); |
RGurav | 0:1b8d65be0eef | 144 | void set_filter_ctl_reg(ADXL355_filter_ctl_t hpf, ADXL355_filter_ctl_t odr); |
RGurav | 0:1b8d65be0eef | 145 | void set_clk(ADXL355_sync_ctl_t data); |
RGurav | 0:1b8d65be0eef | 146 | void set_device(ADXL355_range_ctl_t range); |
RGurav | 0:1b8d65be0eef | 147 | uint8_t read_status(); |
RGurav | 0:1b8d65be0eef | 148 | // ADXL X/Y/Z/T scanning methods |
RGurav | 0:1b8d65be0eef | 149 | uint32_t scanx(); |
RGurav | 0:1b8d65be0eef | 150 | uint32_t scany(); |
RGurav | 0:1b8d65be0eef | 151 | uint32_t scanz(); |
RGurav | 0:1b8d65be0eef | 152 | uint16_t scant(); |
RGurav | 0:1b8d65be0eef | 153 | // ADXL activity methods |
RGurav | 0:1b8d65be0eef | 154 | void set_activity_axis(ADXL355_act_ctl_t axis); |
RGurav | 0:1b8d65be0eef | 155 | void set_activity_cnt(uint8_t count); |
RGurav | 0:1b8d65be0eef | 156 | void set_activity_threshold(uint8_t data_h, uint8_t data_l); |
RGurav | 0:1b8d65be0eef | 157 | void set_inactivity(); |
RGurav | 0:1b8d65be0eef | 158 | // ADXL interrupt methods |
RGurav | 0:1b8d65be0eef | 159 | void set_interrupt1_pin(PinName in, ADXL355_intmap_ctl_t mode); |
RGurav | 0:1b8d65be0eef | 160 | void set_interrupt2_pin(PinName in, ADXL355_intmap_ctl_t mode); |
RGurav | 0:1b8d65be0eef | 161 | void enable_interrupt1(); |
RGurav | 0:1b8d65be0eef | 162 | void enable_interrupt2(); |
RGurav | 0:1b8d65be0eef | 163 | void disable_interrupt1(); |
RGurav | 0:1b8d65be0eef | 164 | void disable_interrupt2(); |
RGurav | 0:1b8d65be0eef | 165 | void set_polling_interrupt1_pin(uint8_t data); |
RGurav | 0:1b8d65be0eef | 166 | void set_polling_interrupt2_pin(uint8_t data); |
RGurav | 0:1b8d65be0eef | 167 | bool get_int1(); |
RGurav | 0:1b8d65be0eef | 168 | bool get_int2(); |
RGurav | 0:1b8d65be0eef | 169 | // ADXL FIFO methods |
RGurav | 0:1b8d65be0eef | 170 | uint8_t fifo_read_nr_of_entries(); |
RGurav | 0:1b8d65be0eef | 171 | void fifo_setup(uint8_t nr_of_entries); |
RGurav | 0:1b8d65be0eef | 172 | uint32_t fifo_read_u32(); |
RGurav | 0:1b8d65be0eef | 173 | uint64_t fifo_scan(); |
RGurav | 0:1b8d65be0eef | 174 | // ADXL calibration |
RGurav | 0:1b8d65be0eef | 175 | float convert(uint32_t data); |
RGurav | 0:1b8d65be0eef | 176 | ADXL355_calibdata_t convert_2p(float angle[11][2], float meas[11][2]); |
RGurav | 0:1b8d65be0eef | 177 | ADXL355_calibdata_t convert_3to8p(float angle[11][2], float meas[11][2], int count); |
RGurav | 0:1b8d65be0eef | 178 | ADXL355_calibdata_t convert_12p(float angle[11][2], float meas[11][2]); |
RGurav | 0:1b8d65be0eef | 179 | |
RGurav | 0:1b8d65be0eef | 180 | private: |
RGurav | 0:1b8d65be0eef | 181 | // SPI adxl355; ///< SPI instance of the ADXL |
RGurav | 0:1b8d65be0eef | 182 | SPI adxl355; DigitalOut cs; |
RGurav | 0:1b8d65be0eef | 183 | const static uint8_t _DEVICE_AD = 0xAD; // contect of DEVID_AD (only-read) register |
RGurav | 0:1b8d65be0eef | 184 | const static uint8_t _RESET = 0x52; // reset code |
RGurav | 0:1b8d65be0eef | 185 | const static uint8_t _DUMMY_BYTE = 0xAA; // 10101010 |
RGurav | 0:1b8d65be0eef | 186 | const static uint8_t _WRITE_REG_CMD = 0x00; // write register |
RGurav | 0:1b8d65be0eef | 187 | const static uint8_t _READ_REG_CMD = 0x01; // read register |
RGurav | 0:1b8d65be0eef | 188 | const static uint8_t _READ_FIFO_CMD = 0x23; // read FIFO |
RGurav | 0:1b8d65be0eef | 189 | const static uint8_t _SPI_MODE = 0; // timing scheme |
RGurav | 0:1b8d65be0eef | 190 | }; |
RGurav | 0:1b8d65be0eef | 191 | |
RGurav | 0:1b8d65be0eef | 192 | #endif |
RGurav | 0:1b8d65be0eef | 193 |