Diff: pulse.cpp

Revision:

36:b6431cd8ecd6

Parent:

34:701503855d52

--- a/pulse.cpp	Tue Dec 13 04:34:36 2016 +0000
+++ b/pulse.cpp	Sun Dec 18 02:29:59 2016 +0000
@@ -1,6 +1,7 @@
 #pragma once
 #include "mbed.h"
 #include "pulse.h"
+#include "rtos.h"
 
 #pragma once
 #include "mbed.h"
@@ -22,8 +23,8 @@
  * due to absence of PWM capabilities of Pins D2 and D4
  * on the FRDM-K64F Board
  */
- pacing_ref_pwm(PTB9),    // Pin D2 (PTB9)
- vent_ref_pwm(PTA1),    // Pin D3
+ pacing_ref_pwm(PTA1),    // Pin D2 (PTB9)
+ vent_ref_pwm(PTB9),    // Pin D3
  atria_ref_pwm(PTB23),   // Pin D4
 
 
@@ -56,8 +57,8 @@
  * due to absence of PWM capabilities of Pins D2 and D4
  * on the FRDM-K64F Board
  */
- pacing_ref_pwm(PTB9),    // Pin D2 (PTB9)
- vent_ref_pwm(PTA1),    // Pin D3
+ pacing_ref_pwm(PTA1),    // Pin D2 (PTB9)
+ vent_ref_pwm(PTB9),    // Pin D3
  atria_ref_pwm(PTB23),   // Pin D4
 
 
@@ -101,16 +102,16 @@
     vent_pace_ctrl.write(0);
     atr_grnd_ctrl .write(1);
     vent_grnd_ctrl.write(1);
-    wait_ms(50);
+    Thread::wait(50);
     
 
     /* Stage 2: Ref PWM LOW */
     pacing_ref_pwm.write(0);
-    wait_ms(100);
+    Thread::wait(100);
 
     /* Stage 3: Charge CTRL off */
     pace_charge_ctrl.write(0);
-    wait_ms(10);
+    Thread::wait(10);
     
     /* Stage 4: Ground OFF */
     atr_grnd_ctrl.write(0);
@@ -126,11 +127,11 @@
     
     /* Stage 1: Ref PWM On */
     pacing_ref_pwm.write(myChamber->getPaceAmp());
-    wait_ms(10);
+    Thread::wait(10);
 
     /* Stage 2: Charge CTRL on */
     pace_charge_ctrl.write(1);
-    wait_ms(10);
+    Thread::wait(10);
 }
 
 void pulse::atr_pace_prime() {
@@ -142,11 +143,11 @@
     
     /* Stage 4: Ref PWM On */
     pacing_ref_pwm.write(myChamber->getPaceAmp());
-    wait_ms(10);
+    Thread::wait(10);
 
     /* Stage 5: Charge CTRL on */
     pace_charge_ctrl.write(1);
-    wait_ms(10);
+    Thread::wait(10);
 }
 
 void pulse::pace_vent(double pulse_width_us) {