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LPC2368/vector_defns.h@44:8d22cce05b9a, 2018-09-09 (annotated)

Committer:
TUATBM
Date:
Sun Sep 09 14:57:10 2018 +0000
Revision:
44:8d22cce05b9a
Parent:
40:976df7c37ad5 
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emilmont 40:976df7c37ad5 1 /* mbed Microcontroller Library - Vectors
emilmont 40:976df7c37ad5 2 * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
emilmont 40:976df7c37ad5 3 */
emilmont 40:976df7c37ad5 4
emilmont 40:976df7c37ad5 5 #ifndef MBED_VECTOR_DEFNS_H
emilmont 40:976df7c37ad5 6 #define MBED_VECTOR_DEFNS_H
emilmont 40:976df7c37ad5 7
emilmont 40:976df7c37ad5 8 // Assember Macros
emilmont 40:976df7c37ad5 9 #ifdef __ARMCC_VERSION
emilmont 40:976df7c37ad5 10 #define EXPORT(x) EXPORT x
emilmont 40:976df7c37ad5 11 #define WEAK_EXPORT(x) EXPORT x [WEAK]
emilmont 40:976df7c37ad5 12 #define IMPORT(x) IMPORT x
emilmont 40:976df7c37ad5 13 #define LABEL(x) x
emilmont 40:976df7c37ad5 14 #else
emilmont 40:976df7c37ad5 15 #define EXPORT(x) .global x
emilmont 40:976df7c37ad5 16 #define WEAK_EXPORT(x) .weak x
emilmont 40:976df7c37ad5 17 #define IMPORT(x) .global x
emilmont 40:976df7c37ad5 18 #define LABEL(x) x:
emilmont 40:976df7c37ad5 19 #endif
emilmont 40:976df7c37ad5 20
emilmont 40:976df7c37ad5 21 // RealMonitor
emilmont 40:976df7c37ad5 22 // Requires RAM (0x40000040-0x4000011F) to be allocated by the linker
emilmont 40:976df7c37ad5 23
emilmont 40:976df7c37ad5 24 // RealMonitor entry points
emilmont 40:976df7c37ad5 25 #define rm_init_entry 0x7fffff91
emilmont 40:976df7c37ad5 26 #define rm_undef_handler 0x7fffffa0
emilmont 40:976df7c37ad5 27 #define rm_prefetchabort_handler 0x7fffffb0
emilmont 40:976df7c37ad5 28 #define rm_dataabort_handler 0x7fffffc0
emilmont 40:976df7c37ad5 29 #define rm_irqhandler2 0x7fffffe0
emilmont 40:976df7c37ad5 30 //#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64
emilmont 40:976df7c37ad5 31 #define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40
emilmont 40:976df7c37ad5 32
emilmont 40:976df7c37ad5 33 // Unofficial RealMonitor entry points and variables
emilmont 40:976df7c37ad5 34 #define RM_MSG_SWI 0x00940000
emilmont 40:976df7c37ad5 35 #define StateP 0x40000040
emilmont 40:976df7c37ad5 36
emilmont 40:976df7c37ad5 37 // VIC register addresses
emilmont 40:976df7c37ad5 38 #define VIC_Base 0xfffff000
emilmont 40:976df7c37ad5 39 #define VICAddress_Offset 0xf00
emilmont 40:976df7c37ad5 40 #define VICVectAddr2_Offset 0x108
emilmont 40:976df7c37ad5 41 #define VICVectAddr3_Offset 0x10c
emilmont 40:976df7c37ad5 42 #define VICIntEnClr_Offset 0x014
emilmont 40:976df7c37ad5 43 #define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014))
emilmont 40:976df7c37ad5 44 #define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108))
emilmont 40:976df7c37ad5 45 #define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C))
emilmont 40:976df7c37ad5 46
emilmont 40:976df7c37ad5 47 // ARM Mode bits and Interrupt flags in PSRs
emilmont 40:976df7c37ad5 48 #define Mode_USR 0x10
emilmont 40:976df7c37ad5 49 #define Mode_FIQ 0x11
emilmont 40:976df7c37ad5 50 #define Mode_IRQ 0x12
emilmont 40:976df7c37ad5 51 #define Mode_SVC 0x13
emilmont 40:976df7c37ad5 52 #define Mode_ABT 0x17
emilmont 40:976df7c37ad5 53 #define Mode_UND 0x1B
emilmont 40:976df7c37ad5 54 #define Mode_SYS 0x1F
emilmont 40:976df7c37ad5 55 #define I_Bit 0x80 // when I bit is set, IRQ is disabled
emilmont 40:976df7c37ad5 56 #define F_Bit 0x40 // when F bit is set, FIQ is disabled
emilmont 40:976df7c37ad5 57
emilmont 40:976df7c37ad5 58 // MCU RAM
emilmont 40:976df7c37ad5 59 #define LPC2368_RAM_ADDRESS 0x40000000 // RAM Base
emilmont 40:976df7c37ad5 60 #define LPC2368_RAM_SIZE 0x8000 // 32KB
emilmont 40:976df7c37ad5 61
emilmont 40:976df7c37ad5 62 // ISR Stack Allocation
emilmont 40:976df7c37ad5 63 #define UND_stack_size 0x00000040
emilmont 40:976df7c37ad5 64 #define SVC_stack_size 0x00000040
emilmont 40:976df7c37ad5 65 #define ABT_stack_size 0x00000040
emilmont 40:976df7c37ad5 66 #define FIQ_stack_size 0x00000000
emilmont 40:976df7c37ad5 67 #define IRQ_stack_size 0x00000040
emilmont 40:976df7c37ad5 68
emilmont 40:976df7c37ad5 69 #define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size)
emilmont 40:976df7c37ad5 70
emilmont 40:976df7c37ad5 71 // Full Descending Stack, so top-most stack points to just above the top of RAM
emilmont 40:976df7c37ad5 72 #define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE)
emilmont 40:976df7c37ad5 73 #define USR_STACK_TOP (LPC2368_STACK_TOP - ISR_stack_size)
emilmont 40:976df7c37ad5 74
emilmont 40:976df7c37ad5 75 #endif