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Dependencies:   mbed MPU6050_2

MPU9250/MPU9250_register.h@0:eae101ae93c0, 2019-02-06 (annotated)

Committer:
taknokolat
Date:
Wed Feb 06 10:54:28 2019 +0000
Revision:
0:eae101ae93c0
a;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
taknokolat 0:eae101ae93c0 1 #ifndef MPU9250_REGISTER_H
taknokolat 0:eae101ae93c0 2 #define MPU9250_REGISTER_H
taknokolat 0:eae101ae93c0 3
taknokolat 0:eae101ae93c0 4 // See also MPU-9250 Register Map and Descriptions, Revision 4.0, RM-MPU-9250A-00, Rev. 1.4, 9/9/2013 for registers not listed in
taknokolat 0:eae101ae93c0 5 // above document; the MPU9250 and MPU9150 are virtually identical but the latter has a different register map
taknokolat 0:eae101ae93c0 6
taknokolat 0:eae101ae93c0 7 //AK8963 registers
taknokolat 0:eae101ae93c0 8 #define WHO_AM_I_AK8963 0x00 // should return 0x48
taknokolat 0:eae101ae93c0 9 #define INFO 0x01
taknokolat 0:eae101ae93c0 10 #define AK8963_ST1 0x02 // data ready status bit 0
taknokolat 0:eae101ae93c0 11 #define AK8963_XOUT_L 0x03 // data
taknokolat 0:eae101ae93c0 12 #define AK8963_XOUT_H 0x04
taknokolat 0:eae101ae93c0 13 #define AK8963_YOUT_L 0x05
taknokolat 0:eae101ae93c0 14 #define AK8963_YOUT_H 0x06
taknokolat 0:eae101ae93c0 15 #define AK8963_ZOUT_L 0x07
taknokolat 0:eae101ae93c0 16 #define AK8963_ZOUT_H 0x08
taknokolat 0:eae101ae93c0 17 #define AK8963_ST2 0x09 // Data overflow bit 3 and data read error status bit 2
taknokolat 0:eae101ae93c0 18 #define AK8963_CNTL 0x0A // Power down (0000), single-measurement (0001), self-test (1000) and Fuse ROM (1111) modes on bits 3:0
taknokolat 0:eae101ae93c0 19 #define AK8963_ASTC 0x0C // Self test control
taknokolat 0:eae101ae93c0 20 #define AK8963_I2CDIS 0x0F // I2C disable
taknokolat 0:eae101ae93c0 21 #define AK8963_ASAX 0x10 // Fuse ROM x-axis sensitivity adjustment value
taknokolat 0:eae101ae93c0 22 #define AK8963_ASAY 0x11 // Fuse ROM y-axis sensitivity adjustment value
taknokolat 0:eae101ae93c0 23 #define AK8963_ASAZ 0x12 // Fuse ROM z-axis sensitivity adjustment value
taknokolat 0:eae101ae93c0 24
taknokolat 0:eae101ae93c0 25
taknokolat 0:eae101ae93c0 26
taknokolat 0:eae101ae93c0 27 //MPU6500 register
taknokolat 0:eae101ae93c0 28 #define SELF_TEST_X_GYRO 0x00
taknokolat 0:eae101ae93c0 29 #define SELF_TEST_Y_GYRO 0x01
taknokolat 0:eae101ae93c0 30 #define SELF_TEST_Z_GYRO 0x02
taknokolat 0:eae101ae93c0 31
taknokolat 0:eae101ae93c0 32 #define SELF_TEST_X_ACCEL 0x0D
taknokolat 0:eae101ae93c0 33 #define SELF_TEST_Y_ACCEL 0x0E
taknokolat 0:eae101ae93c0 34 #define SELF_TEST_Z_ACCEL 0x0F
taknokolat 0:eae101ae93c0 35
taknokolat 0:eae101ae93c0 36 #define SELF_TEST_A 0x10
taknokolat 0:eae101ae93c0 37
taknokolat 0:eae101ae93c0 38 #define XG_OFFSET_H 0x13 // User-defined trim values for gyroscope
taknokolat 0:eae101ae93c0 39 #define XG_OFFSET_L 0x14
taknokolat 0:eae101ae93c0 40 #define YG_OFFSET_H 0x15
taknokolat 0:eae101ae93c0 41 #define YG_OFFSET_L 0x16
taknokolat 0:eae101ae93c0 42 #define ZG_OFFSET_H 0x17
taknokolat 0:eae101ae93c0 43 #define ZG_OFFSET_L 0x18
taknokolat 0:eae101ae93c0 44 #define SMPLRT_DIV 0x19
taknokolat 0:eae101ae93c0 45 #define CONFIG 0x1A
taknokolat 0:eae101ae93c0 46 #define GYRO_CONFIG 0x1B
taknokolat 0:eae101ae93c0 47 #define ACCEL_CONFIG 0x1C
taknokolat 0:eae101ae93c0 48 #define ACCEL_CONFIG2 0x1D
taknokolat 0:eae101ae93c0 49 #define LP_ACCEL_ODR 0x1E
taknokolat 0:eae101ae93c0 50 #define WOM_THR 0x1F
taknokolat 0:eae101ae93c0 51
taknokolat 0:eae101ae93c0 52 #define MOT_DUR 0x20 // Duration counter threshold for motion interrupt generation, 1 kHz rate, LSB = 1 ms
taknokolat 0:eae101ae93c0 53 #define ZMOT_THR 0x21 // Zero-motion detection threshold bits [7:0]
taknokolat 0:eae101ae93c0 54 #define ZRMOT_DUR 0x22 // Duration counter threshold for zero motion interrupt generation, 16 Hz rate, LSB = 64 ms
taknokolat 0:eae101ae93c0 55
taknokolat 0:eae101ae93c0 56 #define FIFO_EN 0x23
taknokolat 0:eae101ae93c0 57 #define I2C_MST_CTRL 0x24
taknokolat 0:eae101ae93c0 58 #define I2C_SLV0_ADDR 0x25
taknokolat 0:eae101ae93c0 59 #define I2C_SLV0_REG 0x26
taknokolat 0:eae101ae93c0 60 #define I2C_SLV0_CTRL 0x27
taknokolat 0:eae101ae93c0 61 #define I2C_SLV1_ADDR 0x28
taknokolat 0:eae101ae93c0 62 #define I2C_SLV1_REG 0x29
taknokolat 0:eae101ae93c0 63 #define I2C_SLV1_CTRL 0x2A
taknokolat 0:eae101ae93c0 64 #define I2C_SLV2_ADDR 0x2B
taknokolat 0:eae101ae93c0 65 #define I2C_SLV2_REG 0x2C
taknokolat 0:eae101ae93c0 66 #define I2C_SLV2_CTRL 0x2D
taknokolat 0:eae101ae93c0 67 #define I2C_SLV3_ADDR 0x2E
taknokolat 0:eae101ae93c0 68 #define I2C_SLV3_REG 0x2F
taknokolat 0:eae101ae93c0 69 #define I2C_SLV3_CTRL 0x30
taknokolat 0:eae101ae93c0 70 #define I2C_SLV4_ADDR 0x31
taknokolat 0:eae101ae93c0 71 #define I2C_SLV4_REG 0x32
taknokolat 0:eae101ae93c0 72 #define I2C_SLV4_DO 0x33
taknokolat 0:eae101ae93c0 73 #define I2C_SLV4_CTRL 0x34
taknokolat 0:eae101ae93c0 74 #define I2C_SLV4_DI 0x35
taknokolat 0:eae101ae93c0 75 #define I2C_MST_STATUS 0x36
taknokolat 0:eae101ae93c0 76 #define INT_PIN_CFG 0x37
taknokolat 0:eae101ae93c0 77 #define INT_ENABLE 0x38
taknokolat 0:eae101ae93c0 78 #define DMP_INT_STATUS 0x39 // Check DMP interrupt
taknokolat 0:eae101ae93c0 79 #define INT_STATUS 0x3A
taknokolat 0:eae101ae93c0 80 #define ACCEL_XOUT_H 0x3B
taknokolat 0:eae101ae93c0 81 #define ACCEL_XOUT_L 0x3C
taknokolat 0:eae101ae93c0 82 #define ACCEL_YOUT_H 0x3D
taknokolat 0:eae101ae93c0 83 #define ACCEL_YOUT_L 0x3E
taknokolat 0:eae101ae93c0 84 #define ACCEL_ZOUT_H 0x3F
taknokolat 0:eae101ae93c0 85 #define ACCEL_ZOUT_L 0x40
taknokolat 0:eae101ae93c0 86 #define TEMP_OUT_H 0x41
taknokolat 0:eae101ae93c0 87 #define TEMP_OUT_L 0x42
taknokolat 0:eae101ae93c0 88 #define GYRO_XOUT_H 0x43
taknokolat 0:eae101ae93c0 89 #define GYRO_XOUT_L 0x44
taknokolat 0:eae101ae93c0 90 #define GYRO_YOUT_H 0x45
taknokolat 0:eae101ae93c0 91 #define GYRO_YOUT_L 0x46
taknokolat 0:eae101ae93c0 92 #define GYRO_ZOUT_H 0x47
taknokolat 0:eae101ae93c0 93 #define GYRO_ZOUT_L 0x48
taknokolat 0:eae101ae93c0 94 #define EXT_SENS_DATA_00 0x49
taknokolat 0:eae101ae93c0 95 #define EXT_SENS_DATA_01 0x4A
taknokolat 0:eae101ae93c0 96 #define EXT_SENS_DATA_02 0x4B
taknokolat 0:eae101ae93c0 97 #define EXT_SENS_DATA_03 0x4C
taknokolat 0:eae101ae93c0 98 #define EXT_SENS_DATA_04 0x4D
taknokolat 0:eae101ae93c0 99 #define EXT_SENS_DATA_05 0x4E
taknokolat 0:eae101ae93c0 100 #define EXT_SENS_DATA_06 0x4F
taknokolat 0:eae101ae93c0 101 #define EXT_SENS_DATA_07 0x50
taknokolat 0:eae101ae93c0 102 #define EXT_SENS_DATA_08 0x51
taknokolat 0:eae101ae93c0 103 #define EXT_SENS_DATA_09 0x52
taknokolat 0:eae101ae93c0 104 #define EXT_SENS_DATA_10 0x53
taknokolat 0:eae101ae93c0 105 #define EXT_SENS_DATA_11 0x54
taknokolat 0:eae101ae93c0 106 #define EXT_SENS_DATA_12 0x55
taknokolat 0:eae101ae93c0 107 #define EXT_SENS_DATA_13 0x56
taknokolat 0:eae101ae93c0 108 #define EXT_SENS_DATA_14 0x57
taknokolat 0:eae101ae93c0 109 #define EXT_SENS_DATA_15 0x58
taknokolat 0:eae101ae93c0 110 #define EXT_SENS_DATA_16 0x59
taknokolat 0:eae101ae93c0 111 #define EXT_SENS_DATA_17 0x5A
taknokolat 0:eae101ae93c0 112 #define EXT_SENS_DATA_18 0x5B
taknokolat 0:eae101ae93c0 113 #define EXT_SENS_DATA_19 0x5C
taknokolat 0:eae101ae93c0 114 #define EXT_SENS_DATA_20 0x5D
taknokolat 0:eae101ae93c0 115 #define EXT_SENS_DATA_21 0x5E
taknokolat 0:eae101ae93c0 116 #define EXT_SENS_DATA_22 0x5F
taknokolat 0:eae101ae93c0 117 #define EXT_SENS_DATA_23 0x60
taknokolat 0:eae101ae93c0 118 #define MOT_DETECT_STATUS 0x61
taknokolat 0:eae101ae93c0 119 #define I2C_SLV0_DO 0x63
taknokolat 0:eae101ae93c0 120 #define I2C_SLV1_DO 0x64
taknokolat 0:eae101ae93c0 121 #define I2C_SLV2_DO 0x65
taknokolat 0:eae101ae93c0 122 #define I2C_SLV3_DO 0x66
taknokolat 0:eae101ae93c0 123 #define I2C_MST_DELAY_CTRL 0x67
taknokolat 0:eae101ae93c0 124 #define SIGNAL_PATH_RESET 0x68
taknokolat 0:eae101ae93c0 125 #define MOT_DETECT_CTRL 0x69
taknokolat 0:eae101ae93c0 126 #define USER_CTRL 0x6A // Bit 7 enable DMP, bit 3 reset DMP
taknokolat 0:eae101ae93c0 127 #define PWR_MGMT_1 0x6B // Device defaults to the SLEEP mode
taknokolat 0:eae101ae93c0 128 #define PWR_MGMT_2 0x6C
taknokolat 0:eae101ae93c0 129 #define DMP_BANK 0x6D // Activates a specific bank in the DMP
taknokolat 0:eae101ae93c0 130 #define DMP_RW_PNT 0x6E // Set read/write pointer to a specific start address in specified DMP bank
taknokolat 0:eae101ae93c0 131 #define DMP_REG 0x6F // Register in DMP from which to read or to which to write
taknokolat 0:eae101ae93c0 132 #define DMP_REG_1 0x70
taknokolat 0:eae101ae93c0 133 #define DMP_REG_2 0x71
taknokolat 0:eae101ae93c0 134 #define FIFO_COUNTH 0x72
taknokolat 0:eae101ae93c0 135 #define FIFO_COUNTL 0x73
taknokolat 0:eae101ae93c0 136 #define FIFO_R_W 0x74
taknokolat 0:eae101ae93c0 137 #define WHO_AM_I_MPU9250 0x75 // Should return 0x71
taknokolat 0:eae101ae93c0 138 #define XA_OFFSET_H 0x77
taknokolat 0:eae101ae93c0 139 #define XA_OFFSET_L 0x78
taknokolat 0:eae101ae93c0 140 #define YA_OFFSET_H 0x7A
taknokolat 0:eae101ae93c0 141 #define YA_OFFSET_L 0x7B
taknokolat 0:eae101ae93c0 142 #define ZA_OFFSET_H 0x7D
taknokolat 0:eae101ae93c0 143 #define ZA_OFFSET_L 0x7E
taknokolat 0:eae101ae93c0 144
taknokolat 0:eae101ae93c0 145 #endif