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7 years, 5 months ago.
Renesas RZ/A1H L1 cache flushing and DMA - why not found in USBDevice
Why does the USBDevice driver (and also the R_BSP library) for this processor in mbed omit all reference to L1 cache flushing? The Renesas DMA example code (in application note R01AN1703EJ0101) makes use of L1_D_CacheWritebackFlushAll() and L1_D_CacheFlushAll() at the beginning and end of DMA transfers between a internal memory and an integrated peripheral.
I have found these cache routines to be essential to the successful use of DMA.
Question relating to:
7 years, 4 months ago.
Hi Adam, We are checking on this - as GR-PEACH board on mbed.org is supported it does not have any external RAM or SDRAM. R01AN1703EJ0101 Rev.1.01 is a more general device/SoC use Application note where an external SDRAM can have DMA setup for L1 Cache area and the three members of RZA family RZAH/M/L have different sizes of SoC RAM 10,8,3MB. These instructions will not work on GR-PEACH.