Just Gary

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8 years, 9 months ago.

How does mbed and the rtos handle device interrupts through GIC?

I have read the Renesas reference manual, the Arm GIC manual, and several online tutorials on using the interrupt controller, but I can't quite figure out if mbed provides an interrupt handler on the A9 core or if I have to provide one in my code. I want to believe that the rtos has handlers in place for each mode the processor might be in, but I haven't found it yet in the mbed source.

The question: assuming that I set up the GIC in a manner similar to that shown in the C code example in "Using the Arm Generic Interrupt Controller" by Altera (ftp://ftp.altera.com/up/pub/Altera_Material/14.0/Tutorials/Using_GIC.pdf, page 17 and on), how do I tell the rtos or the A9 the address of my interrupt handler routine? Or is the GIC already set up in the rtos, and I just need to enable my specific interrupt?

If you have a simple example for mbed, please post it.

Regards,

- Just Gary

Question relating to:

Last updated: 16 Sep 2020
GR-PEACH is an Mbed enabled platform which combines the advantages of the Mbed ecosystem and Arduino UNO form factor.

2 Answers

Tomo Yamanaka
8 years, 9 months ago.

Hi Just Gary.

Thank you your comments.

> but I can't quite figure out if mbed provides an interrupt handler on the A9 core or if I have to provide one in my code.
> I want to believe that the rtos has handlers in place for each mode the processor might be in, but I haven't found it yet in the mbed source.

The mbed provides an interrupt handler that is placed in mbed library and mbed-rtos library.
GIC function of GR-PEACH is placed in mbed lib too.
You will be able to find the function, as below.

- Interrupt handler

- GIC

> how do I tell the rtos or the A9 the address of my interrupt handler routine?
> Or is the GIC already set up in the rtos, and I just need to enable my specific interrupt?

The GIC is set up in Reset Handler.
If you want to register your IRQ handler routine to GIC, please refer to below.

mbed-dev/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c : Line60 to 62

InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
GIC_EnableIRQ(US_TICKER_TIMER_IRQn);



Accepted Answer

Tomo-san -

Thank you. I had found that source file about the same time that you posted your reply, so I quickly made a test. I then got the interrupt, but it looked like the handler would not return. I tried adding a call to GIC_EndInterrupt(IRQn), but it still didn't return. It turns out that it was returning, only to immediately reenter.

Since I am playing with the MTU2 timer, I finally figured out that I have to clear the TGFA bit in MTU2.TSR_1 before I return from the interrupt handler. The example now works great, but for the sake of completeness, do I ever have to issue a call to GIC_EndInterrupt(IRQn), or does the mbed library do that for me? It looks like the library does that for me, but I just want to make sure.

Thanks again,

- Just Gary

posted by Just Gary 27 Feb 2016

Hi Just Gary.

The example now works great, but for the sake of completeness, do I ever have to issue a call to GIC_EndInterrupt(IRQn), or does the mbed library do that for me? It looks like the library does that for me, but I just want to make sure.

The mbed library do that for you. ICCEOIR will be written in last of IRQ_Handler.(It's same as calling GIC_EndInterrupt(IRQn))

Regards, Tomo Yamanaka

posted by Tomo Yamanaka 01 Mar 2016
David Thedens
8 years, 9 months ago.

The mbed RTOS is based upon the open source RTX RTOS which is Cortex M specific. http://www.keil.com/pack/doc/CMSIS/RTOS/html/index.html The A9 is such a different beast, that I doubt the low level context switch would be the same. I looked at FreeRTOS and there are vast differences between M and A.