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9 years, 1 month ago.
simulate I2S using SPI, need for 1.536MHz serial clock rate
I could emulate the ssp port for continuous clock (using TI 4-wire interface), but couldn’t get the required serial clock rate. Only 1.5 or 1.6MHz are doable because of no fractional dividers available. (register SSP CR0 and CPSR).
I also tried to change the SystemClock to 1.536*N, but PLL also cannot support fractional dividers.
Using crystal other than 12MHz is not possible because of USB clock that I need, any other way to create 1.536MHz serial clock and 48MHz USB clock at the same time? Thanks.
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Last updated: 31 Mar 2019
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Just as comment since it doesnt work:
Looking at datasheet, the good news is that it has two PLLs. So as long as you have a standard crystal, it will work with USB.
If you let the main oscillator run at 384MHz, which is outside its official range, so no guarantees it actually works, set the post divider at min, and we got a 192MHz clock. Set the SYSAHBCLKDIV to divide by 5 (so set it to 4), and we got a 38.4MHz main clock. (Note: I don't know if it is actually allowed/functional to use such a high frequency clock for SYSAHBCLKDIV). Then you only need to divide it by 25 to get your clock. Which isn't possible since SSP only wants even bitrate dividers :(.
posted by Erik - 17 Oct 2015