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Hello,
I am working on SDHC driver for Zephyr for FRDM-K64F.
I had to manually enable clock gate for SDHC, as long as zephyr's clock driver does not support it, so I can finally access registers. On initiation stage I send IDLE CMD0 command that passes without an issue and then starting sequence of INTERFACE_CONDITION CMD8 commands, and each of them fails with 16th (Command Timeout) bit in SDHC_IRQSTAT set.
BUS clock is set to 375000 Hz And Source clock - 120000000 Hz
What can be a reason of such behavior?