Important changes to forums and questions

All forums and questions are now archived. To start a new conversation or read the latest updates go to forums.mbed.com.

ADC value's not correct when CLKDIV is even

Topic last updated 10 Feb 2012, by marco driessens. 0 replies
marco driessens
10 Feb 2012

Gaining some more knowlegde about the MBED and the LPC1768 I have written some code using the ADC on a polling base. Conversions are triggered by software and the result is read after the ADC is ready (polling the DONE bit of the result register). Code is based on the mcb1700 code bundle. Now I've discovered that the ADC result makes no sense when I use a even value for the CLKDIV. I can't find any reason for this and also the manual does not say anything about restriction for the CLKDIV value (other than that the MAX freq. must be less then 13MHz)

#ifndef MBED_ADC_H
#define MBED_ADC_H
#endif

#include "mbed.h"

#define XTAL_FREQ       12000000
#define MAX_ADC_CLOCK   13000000
#define CLKS_PER_SAMPLE 65

DigitalOut myled(LED1);
// AnalogIn ADC20(p20);

Serial pc(p13,p14);

int main() {
    int i,div,conv;
    uint32_t regVal;
    int value,high,low;
    
    pc.printf("\r\nMy Analog test program V1.6\r\n");
    pc.printf("Hit a key to start\r\n");
    pc.getc();

    //Work out CCLK
    //adc_clk_freq=CLKS_PER_SAMPLE*sample_rate;
    int m = (LPC_SC->PLL0CFG & 0xFFFF) + 1;
    int n = (LPC_SC->PLL0CFG >> 16) + 1;
    int cclkdiv = LPC_SC->CCLKCFG + 1;
    int Fcco = (2 * m * XTAL_FREQ) / n;
    int cclk = Fcco / cclkdiv;

    pc.printf("CPU freq = %u\r\n",cclk);

    //Power up the ADC        
    LPC_SC->PCONP |= (1 << 12);
    
    // LPC_SC->PCLKSEL0 &= ~(0x3 << 24);  // clear bits    
    // LPC_SC->PCLKSEL0 |= 0x3 << 24;     // div clk by 8
    LPC_PINCON->PINSEL1 &= ~0x003FC000;	/* P0.23~26, A0.0~3, function 01 */
    LPC_PINCON->PINSEL1 |= 0x00154000;
    LPC_PINCON->PINMODE1 &= ~0x003FC000;
    LPC_PINCON->PINMODE1 |= 0x002A8000;
    
    LPC_PINCON->PINSEL3 |= 0xF0000000;	/* P1.30~31, A0.4~5, function 11 */
    LPC_PINCON->PINMODE3 |= 0x80000000;
    
    LPC_ADC->ADCR = ( 0x01 << 0 ) |  /* SEL=1,select channel 0~7 on ADC0 */
        ( 13 << 8 ) |       /* CLKDIV = Fpclk / 2 */ 
        ( 0 << 16 ) |         /* BURST = 0, no BURST, software controlled */
        ( 0 << 17 ) |          /* CLKS = 0, 11 clocks/10 bits */
        ( 1 << 21 ) |          /* PDN = 1, normal operation */
        ( 0 << 24 ) |          /* START = 0 A/D conversion stops */
        ( 0 << 27 );        /* EDGE = 0 (CAP/MAT singal falling,trigger A/D conversion) */ 

    LPC_ADC->ADCR &= 0xFFFFFF00;
    while(1) {
      pc.printf("Enter divider: ");
      pc.scanf("%d",&div);
      pc.printf("\r\nEnter  number of conversions: ");
      pc.scanf("%d",&conv);
      pc.printf("\r\nd: %d, c:%d,\r\n",div,conv);

      LPC_ADC->ADCR &= 0xffff00ff; //CLKDIV = 0
      LPC_ADC->ADCR |= (div <<8);  //CLKDIV = div+1

 
      high = 0;
      low = 65000;    
      for(i=1; i<=conv; i++) {
        LPC_ADC->ADCR |= (1 << 24) | (1 << 4);
    
        while ( 1 ) {            /* wait until end of A/D convert */
          regVal = LPC_ADC->ADDR4;
          /* read result of A/D conversion */
          if ( regVal & 0x80000000 ) {
            break;
          }
        }    
        LPC_ADC->ADCR &= 0xF8FFFFFF;    /* stop ADC now */    

        if ( regVal & 0x40000000 ) {    /* save data when it's not overrun, otherwise, return zero */
          pc.printf("Overrun !\r\n");
          regVal = 0;
        }
        value = ( regVal >> 4 ) & 0xFFF;
        if( value > high )
          high = value;
        if( value < low )
          low = value;  
        pc.printf("%d,%d.\r\n",i,value);
 //       wait_ms(250);
      }
      pc.printf("Highest is: %d.\r\n",high);
      pc.printf("Lowest is: %d.\r\n",low);
      pc.printf("Difference is: %d.\r\n",high-low);
    }
}

Does anyone have a explanation for this ??