SPI hardware contol of clock/chip select?

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SPI hardware contol of clock/chip select?

Topic last updated 07 Jun 2012, by David Mort. 0 replies

# 07 Jun 2012

Hello Simon et all:

I have an application driving cascaded serial Maxim 6952 LED driver chips in a graphics display module. The data sheets http://datasheets.maxim-ic.com/en/ds/MAX6952.pdf indicate compatibility with a High-Speed 26MHz with SPI-/QSPI-™/ MICROWIRE™-Compatible Serial Interface.

The timing diagrams would indicate SCK polarity of 0 (idle low), and SCK phase of 0(rising edge), therefore using SPI 16-bit, mode 0.

The mbed SPI MOSI line drives first driver boards 'Din' and cascades with 'Dout' driving the next successive driver board's 'Din' until the last driver boards 'Dout' returns to mbed at MISO. Currently I have seven driver boards in the series and write to all seven at the same time, marching-in (7x16 bits) 112 bits of data whilst chip select is low.

                       right most            ........            left most
 *  ________          ___________          ___________          ___________
 * |  mbed  |        |  MAX6952  |        |  MAX6952  |        |  MAX6952  |
 * |        |        |           |        |           |        |           |
 * |    mosi|--------|Din    Dout|--------|Din    Dout|--------|Din    Dout|---Din...Dout--+                  
 * |        |        |           |        |           |        |           |               |
 * |        | +------|clk        | +------|clk        | +------|clk        |       t       |
 * |        | |      |           | |      |           | |      |           |       o       |
 * |        | | +----|cs         | | +----|cs         | | +----|cs         |               |
 * |        | | |    |           | | |    |           | | |    |           |       o       |
 * |        | | | +--|osc        | | | +--|osc        | | | +--|osc        |       t       |
 * |        | | | |  |___________| | | |  |___________| | | |  |___________|       h       |
 * |        | | | |                | | |                | | |                      e       |
 * |     pwm|-----+--------------------+--------------------+---------------osc... r       |
 * |        | | |                  | |                  | |                        s       |
 * |      cs|---+--------------------+--------------------+------------------cs...         |
 * |        | |                    |                    |                                  |
 * |     sck|-+--------------------+--------------------+-------------------clk...         |
 * |        |                                                                              |
 * |    miso|------------------------------------------------------------------------------+
 * |________|

The MAX6952 timing diagram 'Figure 2' and literature require after the transfer of 16-bit word (or multiples thereof as in the case stated above for 112 bits for writing to all cascaded drivers at the same time) that the chip select line be driven high whilst the clock is still high when clocking in the last bit.

The MAX6952 is written to using the following sequence:

1) Take CLK low.
2) Take CS low. This enables the internal 16-bit shift register.
3) Clock 16 bits of data into DIN, D15 first to D0 last, observing the setup and hold times. Bit D15 is low, indicating a write command.
4) Take CS high (while CLK is still high after clocking in the last data bit).
5) Take CLK low.

In it's simplest form, using the following software control of the chip select line using a DigitalOut pin assignment does not meet the MAX6952 item #4 above because the SCK line has already returned to an idle state before the chip select line has reverted to a high state through software:

cs=0;
spi.write(0x0401);  //clock returns to idle state after this line executes
cs=1;               //too late, clock already low

A review of the LCP1768 SSP hardware transfer diagrams (which the mbed SPI library relies upon) in the LPC1768 User manual Chapter 18 ~~http://ics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc17xx.pdf~~ (old link), http://www.nxp.com/documents/user_manual/UM10360.pdf demonstrates that the LPC1768 SSP hardware returns the SSEL line to an inactive state one clock cycle after the last SCK pulse, not while SCK is high on the last bit. This occurs one clock cycle too late. Even if the SSEL was tied to an output pin and utilized for the chip select, it would appear that this too, would not properly support the MAX6952 item #4 above.

The LPC1768 hardware also supports Microwire which (Figures 81 and 82) appears to more closely resemble the clock and chip select (SSEL) timing requirements of the MAX6952, but the mbed library does not support Microwire.

My questions are:

1] How can the mbed SPI library SCK output line be held high long enough during the last bit transmission until the chip select line has had an opportunity to set through software (ie: cs=1;)? Is there a hardware register bit manipulation that can accomplish this?

2] Can the SPI library instantiation be used to do the setup legwork, then modify the SSP0CR0 register setting bit 5 to establish the Microwire frame format for the correct timing, and...

3] How can the hardware SSEL be tied to an output pin to utilize the Microwire hardware version of chip select?

4] Is there any plan to support such a timing mode configuration in the mbed library?

Help and/or any wisdom on the matter would be sincerely appreciated, thanks!

David

Hello Simon et all: I have an application driving cascaded serial Maxim 6952 LED driver chips in a graphics display module. The data sheets [[http://datasheets.maxim-ic.com/en/ds/MAX6952.pdf]] indicate compatibility with a High-Speed 26MHz with SPI-/QSPI-™/ MICROWIRE™-Compatible Serial Interface. The timing diagrams would indicate SCK polarity of 0 (idle low), and SCK phase of 0(rising edge), therefore using SPI 16-bit, mode 0. The mbed SPI MOSI line drives first driver boards 'Din' and cascades with 'Dout' driving the next successive driver board's 'Din' until the last driver boards 'Dout' returns to mbed at MISO. Currently I have seven driver boards in the series and write to all seven at the same time, marching-in (7x16 bits) 112 bits of data whilst chip select is low. <<code>> right most ........ left most * ________ ___________ ___________ ___________ * | mbed | | MAX6952 | | MAX6952 | | MAX6952 | * | | | | | | | | * | mosi|--------|Din Dout|--------|Din Dout|--------|Din Dout|---Din...Dout--+ * | | | | | | | | | * | | +------|clk | +------|clk | +------|clk | t | * | | | | | | | | | | | o | * | | | +----|cs | | +----|cs | | +----|cs | | * | | | | | | | | | | | | | | o | * | | | | +--|osc | | | +--|osc | | | +--|osc | t | * | | | | | |___________| | | | |___________| | | | |___________| h | * | | | | | | | | | | | e | * | pwm|-----+--------------------+--------------------+---------------osc... r | * | | | | | | | | s | * | cs|---+--------------------+--------------------+------------------cs... | * | | | | | | * | sck|-+--------------------+--------------------+-------------------clk... | * | | | * | miso|------------------------------------------------------------------------------+ * |________| <</code>> The MAX6952 timing diagram 'Figure 2' and literature require after the transfer of 16-bit word (or multiples thereof as in the case stated above for 112 bits for writing to all cascaded drivers at the same time) that the chip select line be driven high whilst the clock is still high when clocking in the last bit. **The MAX6952 is written to using the following sequence:** *1) Take CLK low. *2) Take CS low. This enables the internal 16-bit shift register. *3) Clock 16 bits of data into DIN, D15 first to D0 last, observing the setup and hold times. Bit D15 is low, indicating a write command. *4) Take CS high __(while CLK is still high after clocking in the last data bit).__ *5) Take CLK low. In it's simplest form, using the following software control of the chip select line using a DigitalOut pin assignment does not meet the MAX6952 item #4 above because the SCK line has already returned to an idle state before the chip select line has reverted to a high state through software: <<code>> cs=0; spi.write(0x0401); //clock returns to idle state after this line executes cs=1; //too late, clock already low <</code>> A review of the LCP1768 SSP hardware transfer diagrams (which the mbed SPI library relies upon) in the LPC1768 User manual Chapter 18 --http://ics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc17xx.pdf-- (old link), [[http://www.nxp.com/documents/user_manual/UM10360.pdf]] demonstrates that the LPC1768 SSP hardware returns the SSEL line to an inactive state one clock cycle **after** the last SCK pulse, not while SCK is high on the last bit. This occurs one clock cycle too late. Even if the SSEL was tied to an output pin and utilized for the chip select, it would appear that this too, would not properly support the MAX6952 item #4 above. The LPC1768 hardware also supports Microwire which (Figures 81 and 82) appears to more closely resemble the clock and chip select (SSEL) timing requirements of the MAX6952, but the mbed library does not support Microwire. My questions are: *1] How can the mbed SPI library SCK output line be held high long enough during the last bit transmission until the chip select line has had an opportunity to set through software (ie: cs=1;)? Is there a hardware register bit manipulation that can accomplish this? *2] Can the SPI library instantiation be used to do the setup legwork, then modify the SSP0CR0 register setting bit 5 to establish the Microwire frame format for the correct timing, and... *3] How can the hardware SSEL be tied to an output pin to utilize the Microwire hardware version of chip select? *4] Is there any plan to support such a timing mode configuration in the mbed library? Help and/or any wisdom on the matter would be sincerely appreciated, thanks! David

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