CAN Bus Frequency Calculation

# 01 Mar 2011

Could someone who worked on the CAN class educate me on how your method calculated the register values based upon a given baud rate.

I have a system that currently uses 1024K (Yes, its weird and not the best idea) that I need to interface with. I am trying to see how close I can really get.

Kevin LeCroy

# 01 Mar 2011

This post seems to have some useful info. Look at the posts by Jon Ward on 21 June.

http://mbed.org/forum/mbed/topic/833/?page=1#comment-4091

Quote:

There aren't any mbed commands to modify these registers directly, except via normal C pointer accesses, which is what LPC_CAN1->MOD is doing. The CMSIS header file (which is included via the mbed.h file) provides a load of useful structures, and defines all the memory addresses you need. For the LPC1768, this file is called LPC17xx.h, and you can have a look at it by click on the link you can see when you look at the library properties (http://mbed.org/projects/libraries/svn/mbed/trunk), and then looking in the LPC1768 directory. The mbed library is to get people up and prototyping rapidly, but there is always the extra control if people need it. The CAN part of the library hadn't been looked at since it was written a few months ago, which is why it is getting a bit of a re-work at the moment - I'll investigate whether putting the mbed into monitor mode should be an option in the libary.

As for your code example, that looks OK to me. Alas, I don't have a CANCase device or similar to hand, so I cannot try out the bit timings in detail.

The other thing you could try is shifting the sample point or frequency slightly yourself. The LPC_CANx->BTR register is the one that controls the bit timing. It is of the form 0x00pq40nnn, where:

p = (TSEG2 - 1), of the range 0..7

q = (TSEG1 - 1), of the range 0..0xF

nnn = (divide - 1), after a prescale divide of 4

[The 4 gives a Sample Jump Width of 1]

The library is currently 0x000D400B, which gives a TSEG2 of 1, a TSEG1 of 14, and divide of 12. Including the sync bit, this gives us:

So TSEG2 + TSEG1 + Sync == 16 bits.

24 Mhz / (16 bits * 12) = 24e6/192 == 125e3 (125 kbit/s)

So, try reducing TSEG1 to make it a little faster (0x000C400B), incread TSEG1 to make it a bit slower (0x001D400B), or try shifting the sample point (0x001C400B) etc.

If/when you get it working, could you provide an update to say what did and didn't work?

This post seems to have some useful info. Look at the posts by Jon Ward on 21 June. http://mbed.org/forum/mbed/topic/833/?page=1#comment-4091 <<quote>> There aren't any mbed commands to modify these registers directly, except via normal C pointer accesses, which is what LPC_CAN1->MOD is doing. The CMSIS header file (which is included via the mbed.h file) provides a load of useful structures, and defines all the memory addresses you need. For the LPC1768, this file is called LPC17xx.h, and you can have a look at it by click on the link you can see when you look at the library properties (http://mbed.org/projects/libraries/svn/mbed/trunk), and then looking in the LPC1768 directory. The mbed library is to get people up and prototyping rapidly, but there is always the extra control if people need it. The CAN part of the library hadn't been looked at since it was written a few months ago, which is why it is getting a bit of a re-work at the moment - I'll investigate whether putting the mbed into monitor mode should be an option in the libary. As for your code example, that looks OK to me. Alas, I don't have a CANCase device or similar to hand, so I cannot try out the bit timings in detail. The other thing you could try is shifting the sample point or frequency slightly yourself. The LPC_CANx->BTR register is the one that controls the bit timing. It is of the form 0x00pq40nnn, where: p = (TSEG2 - 1), of the range 0..7 q = (TSEG1 - 1), of the range 0..0xF nnn = (divide - 1), after a prescale divide of 4 [The 4 gives a Sample Jump Width of 1] The library is currently 0x000D400B, which gives a TSEG2 of 1, a TSEG1 of 14, and divide of 12. Including the sync bit, this gives us: So TSEG2 + TSEG1 + Sync == 16 bits. 24 Mhz / (16 bits * 12) = 24e6/192 == 125e3 (125 kbit/s) So, try reducing TSEG1 to make it a little faster (0x000C400B), incread TSEG1 to make it a bit slower (0x001D400B), or try shifting the sample point (0x001C400B) etc. If/when you get it working, could you provide an update to say what did and didn't work? <</quote>>

bhagyashritte jatte

# 05 Jan 2014

For LPC-2129 baud rate, is it same calculation as mentioned in above comment ??

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