I'm having difficulties creating a program for the interface between mbed cpu and DS1620. All I need to is to get the temperature from DS1620. I'm very new to this and any help would be great.

#include "mbed.h"
Serial RS232(p9,p10); //tx,rx
DigitalOut nrst(p8);
SPI spi(p5, p6, p7);

int main (){
int temperature = -315;
RS232.printf("Continuous reading from DS1620\n\r");
//set clock and spi format
spi.format(8,0);
spi.frequency(20000);
while(1){
nrst = 0;
wait_us(100);
//initial converstion DS1620
nrst = 1;
spi.write(0xEE);//Start converstion
wait_us(50);
//start reading from DS1620
spi.write(0xAA);//Start read
temperature = spi.write(0x00);
RS232.printf("Temperature is %d\n\r",temperature);
wait(2.0);
}
}

I see you are using the SPI protocol in your program above.  Someone correct me if I'm wrong - but from the DS1620 datasheet it does not look like that chip uses the SPI protocol.

3–WIRE COMMUNICATIONS
The 3–wire bus is comprised of three signals. These are the RST (reset) signal, the CLK (clock) signal,
and the DQ (data) signal. All data transfers are initiated by driving the RST input high. Driving the RST
input low terminates communication. (See Figures 4 and 5.) A clock cycle is a sequence of a falling edge
followed by a rising edge. For data inputs, the data must be valid during the rising edge of a clock cycle.
Data bits are output on the falling edge of the clock and remain valid through the rising edge.

Frank

Just had a look at the data sheet, and i am pretty sure that you have the Chip Select (Reset) signal wrong.

there is a much better device TC77,

if you only need to measure temperature,

I Belive you need..

[Start condition Reset Lo]

Reset Hi

TX $c0

TX $00          // continues conversions.

Reset Lo

delay

while(1)

{

reset Hi

TX $AA

RX Temp Low

RX Temp Hi

Reset Lo

Print out

//short delay (>second)

}

Ceri.

Frank Kienast wrote:

I see you are using the SPI protocol in your program above.  Someone correct me if I'm wrong - but from the DS1620 datasheet it does not look like that chip uses the SPI protocol.

 

3–WIRE COMMUNICATIONS
The 3–wire bus is comprised of three signals. These are the RST (reset) signal, the CLK (clock) signal,
and the DQ (data) signal. All data transfers are initiated by driving the RST input high. Driving the RST
input low terminates communication. (See Figures 4 and 5.) A clock cycle is a sequence of a falling edge
followed by a rising edge. For data inputs, the data must be valid during the rising edge of a clock cycle.
Data bits are output on the falling edge of the clock and remain valid through the rising edge.

Frank

Thanks again.

Yeah, you should be able to bit-bang the protocol that way, using the info in the datasheet for specifics.  Not sure if there is an easier way or not, but bit-banging should definitely work.