F746ZG SPI1, only works on left column of CN7

20 Jun 2019

Hi All,

Reference: https://os.mbed.com/media/uploads/jeromecoutant/nucleo_f746zg_zio_right_2019_1_14.png

I tried SPI1 using the right column of CN7 for SPI1 (PA_5, PA_6, PA_7) but always read zeros. Then I tried the left column of CN7, also SPI1 (PB_5, PB_3, PB_4) and reading "something".

As a newbie I ask myself:

  • Why is there two pins for SPI1 MISO, MOSI etc.?
  • What is the difference between, or meaning of PA_5 versus PB_3? Originally I thought the outlet routes to the same pin on the chip.

It seems to me as I am missing something fundamental in the naming logic of this graphic ...

thx!

18 Sep 2019

Hi Thomas,

Most of the IO has several purposes depending how they have been built electrically. Several pins for the same purpose gives your more flexibility to desing. Internally these pins goes to different places in the chip.

This is tutorial for IO pins in microcontrollers: https://deepbluembedded.com/input-output-io-ports-gpio-pins/

In mbedOS you can't control register level. This is tutorial for IO handling in mbedOS: https://os.mbed.com/docs/mbed-os/v5.13/tutorials/index.html and on the page search Using drivers APIs topic.

Regards, Pekka

19 Sep 2019

Hello Thomas,

An I/O pin is usually capable to provide various functions: a "basic" one or "alternate" ones. It means that it can be "connected/routed" to various different points on the chip. In other words, it can be configured for a selected function. Pins are usually configured for the selected function at program start up. In Mbed the particular API class constructors do the job.

For example, when you create an instance of SPI class (notice that the SPI controller's number is not specified):

SPI spi(PB_5, PB_3, PB_4);
  • Mbed checks whether the PB_5 I/O pin can be configured as ("connected/routed to") an SPI controller's MOSI pin and which one is the associated SPI controller (SPI1, SPI2 ... ?) .
  • Mbed repeats the check also for the PB_3 and PB_4 pins.
  • If Mbed finds an SPI controller (SPI1 or SPI2 or ...) with pin numbers matching the selected ones (MOSI == PB_5, MISO == PB_3 and SCK == PB_4) then it will proceed with configuration of those pins and initialization of the associated SPI controller . Otherwise it will report an error.

Quote:

Why is there two pins for SPI1 MISO, MOSI etc.?

As Pekka already said, this provides for more freedom when designing a product.

Quote:

What is the difference between, or meaning of PA_5 versus PB_3? Originally I thought the outlet routes to the same pin on the chip.

According to Table 10. STM32F745xx and STM32F746xx pin and ball definition and Table 12. STM32F745xx and STM32F746xx alternate function mapping in the Datasheet

  • Pin PA_5 can be configured as: TIM2_CH1 or TIM2_ETR or TIM8_CH1N or SPI1_SCK or I2S1_CK or OTG_HS_ULPI_CK or LCD_R4 or EVENTOUT or ADC12_IN5 or DAC_OUT2
  • Pin PB_3 can be connected/routed to: JTDO/TRACES or WOTIM2_CH2 or SPI1_SCK or I2S1_CK or SPI3_SCK or I2S3_CK or EVENTOUT

Please notice that not all functions are implemented by Mbed - see in the PeripheralPins.c file and Pinout pictures for more info.

Quote:

I tried SPI1 using the right column of CN7 for SPI1 (PA_5, PA_6, PA_7) but always read zeros.

The PA_7 pin has a dark blue background in the "Pinout" picture and the "Pins Legend" says that such pins are connected to other components (external to the STM32F746ZG chip but located on the NUCLEO board). After checking in PeripheralPins.c it seems that PA_7 is connected to RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV] (Ethernet controller chip) if jumper JP6 on the NUCLEO-F746ZG board is ON. So most likely that's why you always read zeros. You can try it again with JP6 in OFF position to see whether it works.