Mistake on this page?
Report an issue in GitHub or email us
Data Structures | Macros | Typedefs | Enumerations | Functions | Variables
shci.h File Reference

HCI command for the system channel. More...

#include "mbox_def.h"

Go to the source code of this file.

Data Structures

struct  WirelessFwInfo_t
 

Macros

#define SHCI_OPCODE_C2_FUS_FW_UPGRADE   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_UPGRADE)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_FW_DELETE   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_DELETE)
 No structure for command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_UPDATE_AUTH_KEY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_LOCK_AUTH_KEY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_AUTH_KEY)
 No response parameters. More...
 
#define SHCI_OPCODE_C2_FUS_STORE_USR_KEY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_STORE_USR_KEY)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_LOAD_USR_KEY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOAD_USR_KEY)
 Response parameters. More...
 
#define SHCI_OPCODE_C2_FUS_START_WS   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_START_WS)
 Command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_RESERVED2   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED2)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_RESERVED3   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED3)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_LOCK_USR_KEY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_USR_KEY)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_RESERVED5   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED5)
 Command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_RESERVED6   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED6)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_RESERVED7   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED7)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_RESERVED8   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED8)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_RESERVED9   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED9)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_RESERVED10   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED10)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_RESERVED11   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED11)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FUS_RESERVED12   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED12)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_BLE_INIT   (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_INIT)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_THREAD_INIT   (( SHCI_OGF << 10) + SHCI_OCF_C2_THREAD_INIT)
 No response parameters. More...
 
#define SHCI_OPCODE_C2_DEBUG_INIT   (( SHCI_OGF << 10) + SHCI_OCF_C2_DEBUG_INIT)
 No command parameters. More...
 
#define SHCI_OPCODE_C2_FLASH_ERASE_ACTIVITY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_ACTIVITY)
 No response parameters. More...
 
#define SHCI_OPCODE_C2_CONCURRENT_SET_MODE   (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_SET_MODE)
 No response parameters. More...
 
#define SHCI_OPCODE_C2_FLASH_STORE_DATA   (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_STORE_DATA)
 No response parameters. More...
 
#define SHCI_OPCODE_C2_RADIO_ALLOW_LOW_POWER   (( SHCI_OGF << 10) + SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER)
 No response parameters. More...
 
#define SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL   (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL)
 No response parameters. More...
 
#define SHCI_OPCODE_C2_CONFIG   (( SHCI_OGF << 10) + SHCI_OCF_C2_CONFIG)
 No response parameters. More...
 
#define SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE   (sizeof(SHCI_C2_CONFIG_Cmd_Param_t) - 1)
 PayloadCmdSize Value that shall be used. More...
 
#define SHCI_C2_CONFIG_CONFIG1_BIT0_BLE_NVM_DATA_TO_INTERNAL_FLASH   (0<<0)
 Config1 Each definition below may be added together to build the Config1 value WARNING : Only one definition per bit shall be added to build the Config1 value. More...
 
#define SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE   (1<<0)
 EvtMask1 Each definition below may be added together to build the EvtMask1 value. More...
 
#define BLE_NVM_SRAM_SIZE   (507)
 BleNvmRamAddress The buffer shall have a size of BLE_NVM_SRAM_SIZE number of 32bits The buffer shall be allocated in SRAM2. More...
 
#define THREAD_NVM_SRAM_SIZE   (1016)
 ThreadNvmRamAddress The buffer shall have a size of THREAD_NVM_SRAM_SIZE number of 32bits The buffer shall be allocated in SRAM2. More...
 

Typedefs

typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t
 No response parameters. More...
 

Enumerations

Functions

uint8_t SHCI_C2_FUS_GetState (SHCI_FUS_GetState_ErrorCode_t *p_rsp)
 For all SHCI_C2_FUS_xxx() command: When the wireless FW is running on the CPU2, the command returns SHCI_FUS_CMD_NOT_SUPPORTED When any FUS command is sent after the SHCI_FUS_CMD_NOT_SUPPORTED has been received, the CPU2 switches on the RSS ( This reboots automatically the device ) More...
 
SHCI_CmdStatus_t SHCI_C2_FUS_FwUpgrade (uint32_t fw_src_add, uint32_t fw_dest_add)
 SHCI_C2_FUS_FwUpgrade. More...
 
SHCI_CmdStatus_t SHCI_C2_FUS_FwDelete (void)
 SHCI_C2_FUS_FwDelete. More...
 
SHCI_CmdStatus_t SHCI_C2_FUS_UpdateAuthKey (SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t *pParam)
 SHCI_C2_FUS_UpdateAuthKey. More...
 
SHCI_CmdStatus_t SHCI_C2_FUS_LockAuthKey (void)
 SHCI_C2_FUS_LockAuthKey. More...
 
SHCI_CmdStatus_t SHCI_C2_FUS_StoreUsrKey (SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t *pParam, uint8_t *p_key_index)
 SHCI_C2_FUS_StoreUsrKey. More...
 
SHCI_CmdStatus_t SHCI_C2_FUS_LoadUsrKey (uint8_t key_index)
 SHCI_C2_FUS_LoadUsrKey. More...
 
SHCI_CmdStatus_t SHCI_C2_FUS_StartWs (void)
 SHCI_C2_FUS_StartWs. More...
 
SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey (uint8_t key_index)
 SHCI_C2_FUS_LockUsrKey. More...
 
SHCI_CmdStatus_t SHCI_C2_BLE_Init (SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket)
 SHCI_C2_BLE_Init. More...
 
SHCI_CmdStatus_t SHCI_C2_THREAD_Init (void)
 SHCI_C2_THREAD_Init. More...
 
SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init (uint8_t param_size, uint8_t *p_param)
 SHCI_C2_LLDTESTS_Init. More...
 
SHCI_CmdStatus_t SHCI_C2_LLD_BLE_Init (uint8_t param_size, uint8_t *p_param)
 SHCI_C2_LLD_BLE_Init. More...
 
SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init (void)
 SHCI_C2_ZIGBEE_Init. More...
 
SHCI_CmdStatus_t SHCI_C2_DEBUG_Init (SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket)
 SHCI_C2_DEBUG_Init. More...
 
SHCI_CmdStatus_t SHCI_C2_FLASH_EraseActivity (SHCI_EraseActivity_t erase_activity)
 SHCI_C2_FLASH_EraseActivity. More...
 
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode (SHCI_C2_CONCURRENT_Mode_Param_t Mode)
 SHCI_C2_CONCURRENT_SetMode. More...
 
SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData (SHCI_C2_FLASH_Ip_t Ip)
 SHCI_C2_FLASH_StoreData. More...
 
SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData (SHCI_C2_FLASH_Ip_t Ip)
 SHCI_C2_FLASH_EraseData. More...
 
SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower (SHCI_C2_FLASH_Ip_t Ip, uint8_t FlagRadioLowPowerOn)
 SHCI_C2_RADIO_AllowLowPower. More...
 
SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init (void)
 SHCI_C2_MAC_802_15_4_Init. More...
 
SHCI_CmdStatus_t SHCI_GetWirelessFwInfo (WirelessFwInfo_t *pWirelessInfo)
 SHCI_GetWirelessFwInfo. More...
 
SHCI_CmdStatus_t SHCI_C2_Reinit (void)
 SHCI_C2_Reinit. More...
 
SHCI_CmdStatus_t SHCI_C2_ExtpaConfig (uint32_t gpio_port, uint16_t gpio_pin_number, uint8_t gpio_polarity, uint8_t gpio_status)
 SHCI_C2_ExtpaConfig. More...
 
SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl (SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source)
 SHCI_C2_SetFlashActivityControl. More...
 
SHCI_CmdStatus_t SHCI_C2_Config (SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket)
 SHCI_C2_Config. More...
 

Variables

typedef PACKED_STRUCT
 SHCI_SUB_EVT_CODE_READY This notifies the CPU1 that the CPU2 is now ready to receive commands It reports as well which firmware is running on CPU2 : The wireless stack of the FUS (previously named RSS) More...
 
uint32_t BleBufferSize
 Size of the Buffer allocated in pBleBufferAddress. More...
 
SHCI_C2_Ble_Init_Cmd_Param_t Param
 Does not need to be initialized by the user. More...
 

Detailed Description

HCI command for the system channel.

Author
MCD Application Team
Attention

© Copyright (c) 2019 STMicroelectronics. All rights reserved.

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file shci.h.

Macro Definition Documentation

#define BLE_NVM_SRAM_SIZE   (507)

BleNvmRamAddress The buffer shall have a size of BLE_NVM_SRAM_SIZE number of 32bits The buffer shall be allocated in SRAM2.

Definition at line 526 of file shci.h.

#define SHCI_C2_CONFIG_CONFIG1_BIT0_BLE_NVM_DATA_TO_INTERNAL_FLASH   (0<<0)

Config1 Each definition below may be added together to build the Config1 value WARNING : Only one definition per bit shall be added to build the Config1 value.

Definition at line 504 of file shci.h.

#define SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE   (1<<0)

EvtMask1 Each definition below may be added together to build the EvtMask1 value.

Definition at line 513 of file shci.h.

#define SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE   (sizeof(SHCI_C2_CONFIG_Cmd_Param_t) - 1)

PayloadCmdSize Value that shall be used.

Definition at line 497 of file shci.h.

#define SHCI_OPCODE_C2_BLE_INIT   (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_INIT)

No command parameters.

No response parameters

Definition at line 341 of file shci.h.

#define SHCI_OPCODE_C2_CONCURRENT_SET_MODE   (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_SET_MODE)

No response parameters.

Definition at line 416 of file shci.h.

#define SHCI_OPCODE_C2_CONFIG   (( SHCI_OGF << 10) + SHCI_OCF_C2_CONFIG)

No response parameters.

Definition at line 482 of file shci.h.

#define SHCI_OPCODE_C2_DEBUG_INIT   (( SHCI_OGF << 10) + SHCI_OCF_C2_DEBUG_INIT)

No command parameters.

No response parameters

Definition at line 375 of file shci.h.

#define SHCI_OPCODE_C2_FLASH_ERASE_ACTIVITY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_ACTIVITY)

No response parameters.

Definition at line 406 of file shci.h.

#define SHCI_OPCODE_C2_FLASH_STORE_DATA   (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_STORE_DATA)

No response parameters.

Definition at line 426 of file shci.h.

#define SHCI_OPCODE_C2_FUS_FW_DELETE   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_DELETE)

No structure for command parameters.

No response parameters

Definition at line 242 of file shci.h.

#define SHCI_OPCODE_C2_FUS_FW_UPGRADE   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_UPGRADE)

No command parameters.

No response parameters

Definition at line 238 of file shci.h.

#define SHCI_OPCODE_C2_FUS_LOAD_USR_KEY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOAD_USR_KEY)

Response parameters.

It responds a 1 byte value holding the index given for the stored key

Definition at line 285 of file shci.h.

#define SHCI_OPCODE_C2_FUS_LOCK_AUTH_KEY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_AUTH_KEY)

No response parameters.

Definition at line 254 of file shci.h.

#define SHCI_OPCODE_C2_FUS_LOCK_USR_KEY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_USR_KEY)

No command parameters.

No response parameters

Definition at line 303 of file shci.h.

#define SHCI_OPCODE_C2_FUS_RESERVED10   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED10)

No command parameters.

No response parameters

Definition at line 329 of file shci.h.

#define SHCI_OPCODE_C2_FUS_RESERVED11   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED11)

No command parameters.

No response parameters

Definition at line 333 of file shci.h.

#define SHCI_OPCODE_C2_FUS_RESERVED12   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED12)

No command parameters.

No response parameters

Definition at line 337 of file shci.h.

#define SHCI_OPCODE_C2_FUS_RESERVED2   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED2)

No command parameters.

No response parameters

Definition at line 295 of file shci.h.

#define SHCI_OPCODE_C2_FUS_RESERVED3   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED3)

No command parameters.

No response parameters

Definition at line 299 of file shci.h.

#define SHCI_OPCODE_C2_FUS_RESERVED5   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED5)

Command parameters.

1 byte holding the key index value No response parameters

Definition at line 309 of file shci.h.

#define SHCI_OPCODE_C2_FUS_RESERVED6   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED6)

No command parameters.

No response parameters

Definition at line 313 of file shci.h.

#define SHCI_OPCODE_C2_FUS_RESERVED7   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED7)

No command parameters.

No response parameters

Definition at line 317 of file shci.h.

#define SHCI_OPCODE_C2_FUS_RESERVED8   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED8)

No command parameters.

No response parameters

Definition at line 321 of file shci.h.

#define SHCI_OPCODE_C2_FUS_RESERVED9   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED9)

No command parameters.

No response parameters

Definition at line 325 of file shci.h.

#define SHCI_OPCODE_C2_FUS_START_WS   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_START_WS)

Command parameters.

1 byte holding the key index value No response parameters

Definition at line 291 of file shci.h.

#define SHCI_OPCODE_C2_FUS_STORE_USR_KEY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_STORE_USR_KEY)

No command parameters.

No response parameters

Definition at line 258 of file shci.h.

#define SHCI_OPCODE_C2_FUS_UPDATE_AUTH_KEY   (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY)

No command parameters.

No response parameters

Definition at line 246 of file shci.h.

#define SHCI_OPCODE_C2_RADIO_ALLOW_LOW_POWER   (( SHCI_OGF << 10) + SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER)

No response parameters.

Definition at line 437 of file shci.h.

#define SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL   (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL)

No response parameters.

Definition at line 472 of file shci.h.

#define SHCI_OPCODE_C2_THREAD_INIT   (( SHCI_OGF << 10) + SHCI_OCF_C2_THREAD_INIT)

No response parameters.

Definition at line 371 of file shci.h.

#define THREAD_NVM_SRAM_SIZE   (1016)

ThreadNvmRamAddress The buffer shall have a size of THREAD_NVM_SRAM_SIZE number of 32bits The buffer shall be allocated in SRAM2.

Definition at line 533 of file shci.h.

Typedef Documentation

typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t

No response parameters.

Definition at line 540 of file shci.h.

Enumeration Type Documentation

anonymous enum

Command parameters.

Definition at line 261 of file shci.h.

anonymous enum

Command parameters.

Definition at line 451 of file shci.h.

command parameters

Definition at line 418 of file shci.h.

command parameters

Definition at line 429 of file shci.h.

Command parameters.

Definition at line 474 of file shci.h.

Command parameters.

Definition at line 408 of file shci.h.

No command parameters.

Response parameters

Definition at line 224 of file shci.h.

enum SHCI_OCF_t

THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU2 DEFINITION.

Definition at line 179 of file shci.h.

THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU1 DEFINITION.

Definition at line 62 of file shci.h.

Function Documentation

SHCI_CmdStatus_t SHCI_C2_BLE_Init ( SHCI_C2_Ble_Init_Cmd_Packet_t *  pCmdPacket)

SHCI_C2_BLE_Init.

Provides parameters and starts the BLE Stack

Parameters
pCmdPacket: Parameters to be provided to the BLE Stack
Return values
Status
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode ( SHCI_C2_CONCURRENT_Mode_Param_t  Mode)

SHCI_C2_CONCURRENT_SetMode.

Enable/Disable Thread on CPU2 (M0+)

Parameters
ModeBLE or Thread enable flag
Return values
Status
SHCI_CmdStatus_t SHCI_C2_Config ( SHCI_C2_CONFIG_Cmd_Param_t *  pCmdPacket)

SHCI_C2_Config.

Send the system configuration to the CPU2

Parameters
pCmdPacketaddress of the buffer holding following parameters uint8_t PayloadCmdSize : Size of the payload - shall be SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE uint8_t Config1 :
  • bit0 : 0 - BLE NVM Data data are flushed in internal secure flash 1 - BLE NVM Data are written in SRAM cache pointed by BleNvmRamAddress
  • bit1 : 0 - THREAD NVM Data data are flushed in internal secure flash 1 - THREAD NVM Data are written in SRAM cache pointed by ThreadNvmRamAddress
  • bit2 to bit7 : Unused, shall be set to 0 uint8_t EvtMask1 : When a bit is set to 0, the event is not reported bit0 : Asynchronous Event with Sub Evt Code 0x9201 (= SHCI_SUB_EVT_ERROR_NOTIF) ... bit31 : Asynchronous Event with Sub Evt Code 0x9220 uint8_t Spare1 : Unused, shall be set to 0 uint32_t BleNvmRamAddress : Only considered when Config1.bit0 = 1 When set to 0, data are kept in internal SRAM on CPU2 Otherwise, data are copied in the cache pointed by BleNvmRamAddress The size of the buffer shall be BLE_NVM_SRAM_SIZE (number of 32bits) The buffer shall be allocated in SRAM2 uint32_t ThreadNvmRamAddress : Only considered when Config1.bit1 = 1 When set to 0, data are kept in internal SRAM on CPU2 Otherwise, data are copied in the cache pointed by ThreadNvmRamAddress The size of the buffer shall be THREAD_NVM_SRAM_SIZE (number of 32bits) The buffer shall be allocated in SRAM2

Please check macro definition to be used for this function They are defined in this file next to the definition of SHCI_OPCODE_C2_CONFIG

Return values
Status
SHCI_CmdStatus_t SHCI_C2_DEBUG_Init ( SHCI_C2_DEBUG_Init_Cmd_Packet_t *  pCmdPacket)

SHCI_C2_DEBUG_Init.

Starts the Traces

Parameters
None
Return values
Status
SHCI_CmdStatus_t SHCI_C2_ExtpaConfig ( uint32_t  gpio_port,
uint16_t  gpio_pin_number,
uint8_t  gpio_polarity,
uint8_t  gpio_status 
)

SHCI_C2_ExtpaConfig.

Send the Ext PA configuration When the CPU2 receives the command, it controls the Ext PA as requested by the configuration This configures only which IO is used to enable/disable the ExtPA and the associated polarity This command has no effect on the other IO that is used to control the mode of the Ext PA (Rx/Tx)

Parameters
gpio_portGPIOx where x can be (A..F) to select the GPIO peripheral for STM32WBxx family
gpio_pin_numberThis parameter can be one of GPIO_PIN_x (= LL_GPIO_PIN_x) where x can be (0..15).
gpio_polarityThis parameter can be either
  • EXT_PA_ENABLED_LOW: ExtPA is enabled when GPIO is low
  • EXT_PA_ENABLED_HIGH: ExtPA is enabled when GPIO is high
gpio_statusThis parameter can be either
  • EXT_PA_DISABLED: Stop driving the ExtPA
  • EXT_PA_ENABLED: Drive the ExtPA according to radio activity (ON before the Event and OFF at the end of the event)
Return values
Status
SHCI_CmdStatus_t SHCI_C2_FLASH_EraseActivity ( SHCI_EraseActivity_t  erase_activity)

SHCI_C2_FLASH_EraseActivity.

Provides the information of the start and the end of a flash erase window on the CPU1

Parameters
erase_activityStart/End of erase activity
Return values
Status
SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData ( SHCI_C2_FLASH_Ip_t  Ip)

SHCI_C2_FLASH_EraseData.

Erase Data in Flash

Parameters
IpBLE or THREAD
Return values
Status
SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData ( SHCI_C2_FLASH_Ip_t  Ip)

SHCI_C2_FLASH_StoreData.

Store Data in Flash

Parameters
IpBLE or THREAD
Return values
Status
SHCI_CmdStatus_t SHCI_C2_FUS_FwDelete ( void  )

SHCI_C2_FUS_FwDelete.

Delete the wireless stack on CPU2

Parameters
None
Return values
Status
SHCI_CmdStatus_t SHCI_C2_FUS_FwUpgrade ( uint32_t  fw_src_add,
uint32_t  fw_dest_add 
)

SHCI_C2_FUS_FwUpgrade.

Request the FUS to install the CPU2 firmware update

Parameters
fw_src_addAddress of the firmware image location
fw_dest_addAddress of the firmware destination
Return values
Status
uint8_t SHCI_C2_FUS_GetState ( SHCI_FUS_GetState_ErrorCode_t p_rsp)

For all SHCI_C2_FUS_xxx() command: When the wireless FW is running on the CPU2, the command returns SHCI_FUS_CMD_NOT_SUPPORTED When any FUS command is sent after the SHCI_FUS_CMD_NOT_SUPPORTED has been received, the CPU2 switches on the RSS ( This reboots automatically the device )

SHCI_C2_FUS_GetState Read the FUS State If the user is not interested by the Error code response, a null value may be passed as parameter

Parameters
p_rsp: return the error code when the FUS State Value = 0xFF
Return values
FUSState Values
SHCI_CmdStatus_t SHCI_C2_FUS_LoadUsrKey ( uint8_t  key_index)

SHCI_C2_FUS_LoadUsrKey.

Request the FUS to load the user key into the AES

Parameters
key_index: index of the user key to load in AES1
Return values
Status
SHCI_CmdStatus_t SHCI_C2_FUS_LockAuthKey ( void  )

SHCI_C2_FUS_LockAuthKey.

Request the FUS to prevent any future update of the authentication key

Parameters
None
Return values
Status
SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey ( uint8_t  key_index)

SHCI_C2_FUS_LockUsrKey.

Request the FUS to lock the user key so that it cannot be updated later on

Parameters
key_index: index of the user key to lock
Return values
Status
SHCI_CmdStatus_t SHCI_C2_FUS_StartWs ( void  )

SHCI_C2_FUS_StartWs.

Request the FUS to reboot on the wireless stack

Parameters
None
Return values
Status
SHCI_CmdStatus_t SHCI_C2_FUS_StoreUsrKey ( SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t *  pParam,
uint8_t *  p_key_index 
)

SHCI_C2_FUS_StoreUsrKey.

Request the FUS to store the user key

Parameters
pParam: command parameter
p_key_index: Index allocated by the FUS to the stored key
Return values
Status
SHCI_CmdStatus_t SHCI_C2_FUS_UpdateAuthKey ( SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t *  pParam)

SHCI_C2_FUS_UpdateAuthKey.

Request the FUS to update the authentication key

Parameters
pCmdPacket
Return values
Status
SHCI_CmdStatus_t SHCI_C2_LLD_BLE_Init ( uint8_t  param_size,
uint8_t *  p_param 
)

SHCI_C2_LLD_BLE_Init.

Starts the LLD tests CLI

Parameters
param_size: Nb of bytes
p_param: pointeur with data to give from M4 to M0
Return values
Status
SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init ( uint8_t  param_size,
uint8_t *  p_param 
)

SHCI_C2_LLDTESTS_Init.

Starts the LLD tests CLI

Parameters
param_size: Nb of bytes
p_param: pointeur with data to give from M4 to M0
Return values
Status
SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init ( void  )

SHCI_C2_MAC_802_15_4_Init.

Starts the MAC 802.15.4 on M0

Parameters
None
Return values
Status
SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower ( SHCI_C2_FLASH_Ip_t  Ip,
uint8_t  FlagRadioLowPowerOn 
)

SHCI_C2_RADIO_AllowLowPower.

Allow or forbid IP_radio (802_15_4 or BLE) to enter in low power mode.

Parameters
IpBLE or 802_15_5
FlagRadioLowPowerOnTrue or false
Return values
Status
SHCI_CmdStatus_t SHCI_C2_Reinit ( void  )

SHCI_C2_Reinit.

This is required to allow the CPU1 to fake a set C2BOOT when it has already been set. In order to fake a C2BOOT, the CPU1 shall :

  • Send SHCI_C2_Reinit()
  • call SEV instruction WARNING: This function is intended to be used by the SBSFU
Parameters
None
Return values
Status
SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl ( SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t  Source)

SHCI_C2_SetFlashActivityControl.

Set the mechanism to be used on CPU2 to prevent the CPU1 to either write or erase in flash

Parameters
SourceIt can be one of the following list
  • FLASH_ACTIVITY_CONTROL_PES : The CPU2 set the PES bit to prevent the CPU1 to either read or write in flash
  • FLASH_ACTIVITY_CONTROL_SEM7 : The CPU2 gets the semaphore 7 to prevent the CPU1 to either read or write in flash. This requires the CPU1 to first get semaphore 7 before erasing or writing the flash.
Return values
Status
SHCI_CmdStatus_t SHCI_C2_THREAD_Init ( void  )

SHCI_C2_THREAD_Init.

Starts the THREAD Stack

Parameters
None
Return values
Status
SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init ( void  )

SHCI_C2_ZIGBEE_Init.

Starts the Zigbee Stack

Parameters
None
Return values
Status
SHCI_CmdStatus_t SHCI_GetWirelessFwInfo ( WirelessFwInfo_t pWirelessInfo)

SHCI_GetWirelessFwInfo.

This function read back the informations relative to the wireless binary loaded. Refer yourself to SHCI_WirelessFwInfoTable_t structure to get the significance of the different parameters returned.

Parameters
pWirelessInfo: Pointer to WirelessFwInfo_t.
Return values
SHCI_Success

Variable Documentation

uint32_t BleBufferSize

Size of the Buffer allocated in pBleBufferAddress.

Definition at line 345 of file shci.h.

typedef PACKED_STRUCT
Initial value:
{
SHCI_SysEvt_Ready_Rsp_t sysevt_ready_rsp

SHCI_SUB_EVT_CODE_READY This notifies the CPU1 that the CPU2 is now ready to receive commands It reports as well which firmware is running on CPU2 : The wireless stack of the FUS (previously named RSS)

Command parameters.

THE ORDER SHALL NOT BE CHANGED.

SHCI_SUB_EVT_NVM_END_ERASE This notifies the CPU1 that the CPU2 has erased all expected flash sectors.

SHCI_SUB_EVT_NVM_END_WRITE This notifies the CPU1 that the CPU2 has written all expected data in Flash.

SHCI_SUB_EVT_NVM_START_WRITE This notifies the CPU1 that the CPU2 has started a write procedure in Flash NumberOfWords : The number of 64bits data the CPU2 needs to write in Flash.

SHCI_SUB_EVT_OT_NVM_RAM_UPDATE This notifies the CPU1 which part of the OT NVM RAM has been updated so that only the modified section could be written in Flash/NVM StartAddress : Start address of the section that has been modified Size : Size (in bytes) of the section that has been modified.

SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE This notifies the CPU1 which part of the BLE NVM RAM has been updated so that only the modified section could be written in Flash/NVM StartAddress : Start address of the section that has been modified Size : Size (in bytes) of the section that has been modified.

SHCI_SUB_EVT_ERROR_NOTIF This reports to the CPU1 some error form the CPU2.

For each 64bits data, the algorithm as described in AN5289 is executed. When this number is reported to 0, it means the Number of 64bits to be written was unknown when the procedure has started. When all data are written, the SHCI_SUB_EVT_NVM_END_WRITE event is reported

SHCI_SUB_EVT_NVM_START_ERASE This notifies the CPU1 that the CPU2 has started a erase procedure in Flash NumberOfSectors : The number of sectors the CPU2 needs to erase in Flash. For each sector, the algorithm as described in AN5289 is executed. When this number is reported to 0, it means the Number of sectors to be erased was unknown when the procedure has started. When all sectors are erased, the SHCI_SUB_EVT_NVM_END_ERASE event is reported

NOT USED CURRENTLY

Definition at line 79 of file shci.h.

SHCI_C2_DEBUG_init_Cmd_Param_t Param

Does not need to be initialized by the user.

Definition at line 366 of file shci.h.

Important Information for this Arm website

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.