Keil Studio Cloud
Mistake on this page?
Report an issue in GitHub or email us
m480_eth.h
1 /*
2  * Copyright (c) 2018 Nuvoton Technology Corp.
3  * Copyright (c) 2018 ARM Limited
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the "License");
7  * you may not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  * http://www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an "AS IS" BASIS,
14  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  *
18  * Description: M480 EMAC driver header file
19  */
20 
21 #include "numaker_emac_config.h"
22 #include "M480.h"
23 #ifndef _M480_ETH_
24 #define _M480_ETH_
25 
26 /* Generic MII registers. */
27 
28 #define MII_BMCR 0x00 /* Basic mode control register */
29 #define MII_BMSR 0x01 /* Basic mode status register */
30 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
31 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
32 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
33 #define MII_LPA 0x05 /* Link partner ability reg */
34 #define MII_EXPANSION 0x06 /* Expansion register */
35 #define MII_DCOUNTER 0x12 /* Disconnect counter */
36 #define MII_FCSCOUNTER 0x13 /* False carrier counter */
37 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
38 #define MII_RERRCOUNTER 0x15 /* Receive error counter */
39 #define MII_SREVISION 0x16 /* Silicon revision */
40 #define MII_RESV1 0x17 /* Reserved... */
41 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
42 #define MII_PHYADDR 0x19 /* PHY address */
43 #define MII_RESV2 0x1a /* Reserved... */
44 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
45 #define MII_NCONFIG 0x1c /* Network interface config */
46 
47 /* Basic mode control register. */
48 #define BMCR_RESV 0x007f /* Unused... */
49 #define BMCR_CTST 0x0080 /* Collision test */
50 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
51 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
52 #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
53 #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
54 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
55 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
56 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
57 #define BMCR_RESET 0x8000 /* Reset the DP83840 */
58 
59 /* Basic mode status register. */
60 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
61 #define BMSR_JCD 0x0002 /* Jabber detected */
62 #define BMSR_LSTATUS 0x0004 /* Link status */
63 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
64 #define BMSR_RFAULT 0x0010 /* Remote fault detected */
65 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
66 #define BMSR_RESV 0x07c0 /* Unused... */
67 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
68 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
69 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
70 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
71 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
72 
73 /* Advertisement control register. */
74 #define ADVERTISE_SLCT 0x001f /* Selector bits */
75 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
76 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
77 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
78 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
79 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
80 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
81 #define ADVERTISE_RESV 0x1c00 /* Unused... */
82 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
83 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
84 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
85 
86 #define RX_DESCRIPTOR_NUM NU_RX_RING_LEN//4 //2 // 4: Max Number of Rx Frame Descriptors
87 #define TX_DESCRIPTOR_NUM NU_TX_RING_LEN//4 //2 // 4: Max number of Tx Frame Descriptors
88 
89 #define PACKET_BUFFER_SIZE ( NU_ETH_MAX_FLEN + ((NU_ETH_MAX_FLEN%4) ? (4 - (NU_ETH_MAX_FLEN%4)) : 0) ) //For DMA 4 bytes alignment
90 
91 #define CONFIG_PHY_ADDR 1
92 
93 
94 // Frame Descriptor's Owner bit
95 #define OWNERSHIP_EMAC 0x80000000 // 1 = EMAC
96 //#define OWNERSHIP_CPU 0x7fffffff // 0 = CPU
97 
98 
99 
100 // Rx Frame Descriptor Status
101 #define RXFD_RXGD 0x00100000 // Receiving Good Packet Received
102 #define RXFD_RTSAS 0x00800000 // RX Time Stamp Available
103 
104 
105 // Tx Frame Descriptor's Control bits
106 #define TXFD_TTSEN 0x08 // Tx Time Stamp Enable
107 #define TXFD_INTEN 0x04 // Interrupt Enable
108 #define TXFD_CRCAPP 0x02 // Append CRC
109 #define TXFD_PADEN 0x01 // Padding Enable
110 
111 // Tx Frame Descriptor Status
112 #define TXFD_TXCP 0x00080000 // Transmission Completion
113 #define TXFD_TTSAS 0x08000000 // TX Time Stamp Available
114 
115 // Tx/Rx buffer descriptor structure
116 struct eth_descriptor;
117 struct eth_descriptor {
118  uint32_t status1;
119  uint8_t *buf;
120  uint32_t status2;
121  struct eth_descriptor *next;
122 #ifdef TIME_STAMPING
123  uint32_t backup1;
124  uint32_t backup2;
125  uint32_t reserved1;
126  uint32_t reserved2;
127 #endif
128 };
129 
130 #ifdef TIME_STAMPING
131 
132 #define ETH_TS_ENABLE() do{EMAC->TSCTL = EMAC_TSCTL_TSEN_Msk;}while(0)
133 #define ETH_TS_START() do{EMAC->TSCTL |= (EMAC_TSCTL_TSMODE_Msk | EMAC_TSCTL_TSIEN_Msk);}while(0)
134 s32_t ETH_settime(u32_t sec, u32_t nsec);
135 s32_t ETH_gettime(u32_t *sec, u32_t *nsec);
136 s32_t ETH_updatetime(u32_t neg, u32_t sec, u32_t nsec);
137 s32_t ETH_adjtimex(int ppm);
138 void ETH_setinc(void);
139 
140 #endif
141 
142 #endif /* _M480_ETH_ */
eth_descriptor
Definition: m480_eth.h:117
Important Information for this Arm website

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies. If you are not happy with the use of these cookies, please review our Cookie Policy to learn how they can be disabled. By disabling cookies, some features of the site will not work.