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N25Q128A_config.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2018 ARM Limited
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 #ifndef MBED_QSPI_FLASH_N25Q128A_H
17 #define MBED_QSPI_FLASH_N25Q128A_H
18 
19 
20 #define QSPI_FLASH_CHIP_STRING "Micron N25Q128A"
21 
22 // Command for reading status register
23 #define QSPI_CMD_RDSR 0x05
24 // Command for reading configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
25 #define QSPI_CMD_RDCR0 0xB5
26 // Command for reading configuration register 1 (VOLATILE CONFIGURATION REGISTER)
27 #define QSPI_CMD_RDCR1 0x85
28 // Command for reading configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
29 #define QSPI_CMD_RDCR2 0x65
30 // Command for writing status
31 #define QSPI_CMD_WRSR 0x01
32 // Command for writing configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
33 #define QSPI_CMD_WRCR0 0xB1
34 // Command for writing configuration register 1 (VOLATILE CONFIGURATION REGISTER)
35 #define QSPI_CMD_WRCR1 0x81
36 // Command for writing configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
37 #define QSPI_CMD_WRCR2 0x61
38 // Command for reading security register
39 #define QSPI_CMD_RDSCUR 0x2B
40 
41 // Command for setting Reset Enable
42 #define QSPI_CMD_RSTEN 0x66
43 // Command for setting Reset
44 #define QSPI_CMD_RST 0x99
45 
46 // Command for setting write enable
47 #define QSPI_CMD_WREN 0x06
48 // Command for setting write disable
49 #define QSPI_CMD_WRDI 0x04
50 
51 // WRSR operations max time [us] (datasheet max time + 15%)
52 #define QSPI_WRSR_MAX_TIME 9200 // 8ms
53 // general wait max time [us]
54 #define QSPI_WAIT_MAX_TIME 100000 // 100ms
55 
56 
57 // Commands for writing (page programming)
58 #define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
59 #define QSPI_CMD_WRITE_2IO 0xD2 // 1-2-2 mode
60 #define QSPI_CMD_WRITE_4IO 0x12 // 1-4-4 mode
61 #define QSPI_CMD_WRITE_DPI 0xD2 // 2-2-2 mode
62 #define QSPI_CMD_WRITE_QPI 0x12 // 4-4-4 mode
63 
64 // write operations max time [us] (datasheet max time + 15%)
65 #define QSPI_PAGE_PROG_MAX_TIME 5750 // 5ms
66 
67 #define QSPI_PAGE_SIZE 256 // 256B
68 #define QSPI_SECTOR_SIZE 4096 // 4kB
69 #define QSPI_SECTOR_COUNT 4096
70 
71 // Commands for reading
72 #define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
73 #define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
74 #define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
75 #define QSPI_CMD_READ_DPI 0xBB // 2-2-2 mode
76 #define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
77 #define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
78 #define QSPI_CMD_READ_QPI 0xEB // 4-4-4 mode
79 #define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
80 
81 
82 #define QSPI_READ_1IO_DUMMY_CYCLE 0
83 #define QSPI_READ_FAST_DUMMY_CYCLE 8
84 // 8 dummy (10 dummy when quad SPI protocol is enabled)
85 #define QSPI_READ_2IO_DUMMY_CYCLE 8
86 #define QSPI_READ_1I2O_DUMMY_CYCLE 8
87 #define QSPI_READ_4IO_DUMMY_CYCLE 10
88 #define QSPI_READ_1I4O_DUMMY_CYCLE 8
89 
90 // Commands for erasing
91 #define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
92 #define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
93 #define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
94 #define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
95 
96 // erase operations max time [us] (datasheet max time + 15%)
97 #define QSPI_ERASE_SECTOR_MAX_TIME 920000 // 0.8s
98 #define QSPI_ERASE_BLOCK_32_MAX_TIME 3000000 // 3s
99 #define QSPI_ERASE_BLOCK_64_MAX_TIME 3500000 // 3.5s
100 
101 // max frequency for basic rw operation
102 #define QSPI_COMMON_MAX_FREQUENCY 50000000
103 
104 #define QSPI_STATUS_REG_SIZE 1
105 #define QSPI_CONFIG_REG_0_SIZE 2
106 #define QSPI_CONFIG_REG_1_SIZE 1
107 #define QSPI_CONFIG_REG_2_SIZE 1
108 #define QSPI_MAX_REG_SIZE 2
109 
110 // status register
111 #define STATUS_BIT_WIP (1 << 0) // write in progress bit
112 #define STATUS_BIT_WEL (1 << 1) // write enable latch
113 #define STATUS_BIT_BP0 (1 << 2) // block
114 #define STATUS_BIT_BP1 (1 << 3) //
115 #define STATUS_BIT_BP2 (1 << 4) //
116 #define STATUS_BIT_BP_TB (1 << 5) // Block protect top/bottom
117 #define STATUS_BIT_BP3 (1 << 6) //
118 #define STATUS_BIT_SRWD (1 << 7) // status register write protect
119 
120 // configuration register 0 (Nonvolatile Configuration Register)
121 // bit 1, 5, reserved
122 #define CONFIG0_BIT_LOCK (1 << 0) // Lock nonvolatile configuration register
123 #define CONFIG0_BIT_DE (1 << 2) // Dual Enable 0 = Enabled / 1 = Disabled
124 #define CONFIG0_BIT_QE (1 << 3) // Quad Enable 0 = Enabled / 1 = Disabled
125 #define CONFIG0_BIT_RH (1 << 4) // Reset/hold
126 #define CONFIG0_BIT_ODS0 (1 << 6) // Output driver strength
127 #define CONFIG0_BIT_ODS1 (1 << 7) // Output driver strength
128 #define CONFIG0_BIT_ODS2 (1 << 8) // Output driver strength
129 #define CONFIG0_BIT_XIP_MODE0 (1 << 9) // XIP mode at power-on reset
130 #define CONFIG0_BIT_XIP_MODE1 (1 << 10) // XIP mode at power-on reset
131 #define CONFIG0_BIT_XIP_MODE2 (1 << 11) // XIP mode at power-on reset
132 #define CONFIG0_BIT_DCYCLE0 (1 << 12) // Dummy Cycle
133 #define CONFIG0_BIT_DCYCLE1 (1 << 13) // Dummy Cycle
134 #define CONFIG0_BIT_DCYCLE2 (1 << 14) // Dummy Cycle
135 #define CONFIG0_BIT_DCYCLE3 (1 << 15) // Dummy Cycle
136 #define CONFIG0_BITS_DEFAULT 0xFFFF // reg default state
137 
138 
139 // configuration register 1 (Volatile Configuration Register)
140 // bit 2, reserved
141 #define CONFIG1_BIT_WRAP0 (1 << 0) // Output data wrap
142 #define CONFIG1_BIT_WRAP1 (1 << 1) // Output data wrap
143 #define CONFIG1_BIT_XIP (1 << 3) // 0 = Enable / 1 = Disable (default)
144 #define CONFIG1_BIT_DCYCLE0 (1 << 4) // Number of dummy clock cycles
145 #define CONFIG1_BIT_DCYCLE1 (1 << 5) // Number of dummy clock cycles
146 #define CONFIG1_BIT_DCYCLE2 (1 << 6) // Number of dummy clock cycles
147 #define CONFIG1_BIT_DCYCLE3 (1 << 7) // Number of dummy clock cycles
148 #define CONFIG1_BITS_DEFAULT 0xB // reg default state
149 
150 
151 // configuration register 2 (Enhanced Volatile Configuration Register)
152 // bit 5, reserved
153 #define CONFIG2_BIT_ODS0 (1 << 0) // Output driver strength 111 = 30 Ohms (Default)
154 #define CONFIG2_BIT_ODS1 (1 << 1) // Output driver strength
155 #define CONFIG2_BIT_ODS2 (1 << 2) // Output driver strength
156 #define CONFIG2_BIT_VPP (1 << 3) // VPP accelerator 1 = Disabled (Default)
157 #define CONFIG2_BIT_RH (1 << 4) // Reset/hold
158 #define CONFIG2_BIT_DE (1 << 6) // Dual I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
159 #define CONFIG2_BIT_QE (1 << 7) // Quad I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
160 #define CONFIG2_BITS_DEFAULT 0xDF // reg default state
161 
162 
163 #define DUAL_ENABLE() \
164  \
165  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
166  \
167  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
168  if (read_register(QSPI_CMD_RDCR2, reg_data, \
169  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
170  return QSPI_STATUS_ERROR; \
171  } \
172  if (write_enable(qspi) != QSPI_STATUS_OK) { \
173  return QSPI_STATUS_ERROR; \
174  } \
175  \
176  reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_DE); \
177  if (write_register(QSPI_CMD_WRCR2, reg_data, \
178  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
179  return QSPI_STATUS_ERROR; \
180  } \
181  qspi.cmd.configure(MODE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8); \
182  WAIT_FOR(WRSR_MAX_TIME, qspi); \
183  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
184  if (read_register(QSPI_CMD_RDCR2, reg_data, \
185  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
186  return QSPI_STATUS_ERROR; \
187  } \
188  \
189  return ((reg_data[0] & (CONFIG2_BIT_DE)) == 0 ? \
190  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
191 
192 
193 #define DUAL_DISABLE() \
194  \
195  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
196  \
197  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
198  if (read_register(QSPI_CMD_RDCR2, reg_data, \
199  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
200  return QSPI_STATUS_ERROR; \
201  } \
202  if (write_enable(qspi) != QSPI_STATUS_OK) { \
203  return QSPI_STATUS_ERROR; \
204  } \
205  \
206  reg_data[0] = reg_data[0] | (CONFIG2_BIT_DE); \
207  if (write_register(QSPI_CMD_WRCR2, reg_data, \
208  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
209  return QSPI_STATUS_ERROR; \
210  } \
211  WAIT_FOR(WRSR_MAX_TIME, qspi); \
212  qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
213  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
214  if (read_register(QSPI_CMD_RDCR2, reg_data, \
215  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
216  return QSPI_STATUS_ERROR; \
217  } \
218  \
219  return ((reg_data[0] & CONFIG2_BIT_DE) != 1 ? \
220  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
221 
222 
223 #define QUAD_ENABLE() \
224  \
225  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
226  \
227  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
228  if (read_register(QSPI_CMD_RDCR2, reg_data, \
229  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
230  return QSPI_STATUS_ERROR; \
231  } \
232  if (write_enable(qspi) != QSPI_STATUS_OK) { \
233  return QSPI_STATUS_ERROR; \
234  } \
235  \
236  reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_QE); \
237  if (write_register(QSPI_CMD_WRCR2, reg_data, \
238  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
239  return QSPI_STATUS_ERROR; \
240  } \
241  qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
242  WAIT_FOR(WRSR_MAX_TIME, qspi); \
243  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
244  if (read_register(QSPI_CMD_RDCR2, reg_data, \
245  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
246  return QSPI_STATUS_ERROR; \
247  } \
248  \
249  return ((reg_data[0] & (CONFIG2_BIT_QE)) == 0 ? \
250  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
251 
252 
253 #define QUAD_DISABLE() \
254  \
255  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
256  \
257  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
258  if (read_register(QSPI_CMD_RDCR2, reg_data, \
259  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
260  return QSPI_STATUS_ERROR; \
261  } \
262  if (write_enable(qspi) != QSPI_STATUS_OK) { \
263  return QSPI_STATUS_ERROR; \
264  } \
265  \
266  reg_data[0] = reg_data[0] | (CONFIG2_BIT_QE); \
267  if (write_register(QSPI_CMD_WRCR2, reg_data, \
268  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
269  return QSPI_STATUS_ERROR; \
270  } \
271  WAIT_FOR(WRSR_MAX_TIME, qspi); \
272  qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
273  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
274  if (read_register(QSPI_CMD_RDCR2, reg_data, \
275  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
276  return QSPI_STATUS_ERROR; \
277  } \
278  \
279  return ((reg_data[0] & CONFIG2_BIT_QE) != 1 ? \
280  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
281 
282 #endif // MBED_QSPI_FLASH_N25Q128A_H
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