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MX25RXX35F_config.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2018 ARM Limited
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 #ifndef MBED_QSPI_FLASH_MX25RXX35F_H
17 #define MBED_QSPI_FLASH_MX25RXX35F_H
18 
19 
20 #define QSPI_FLASH_CHIP_STRING "macronix MX25RXX35F"
21 
22 // Command for reading status register
23 #define QSPI_CMD_RDSR 0x05
24 // Command for reading configuration register
25 #define QSPI_CMD_RDCR0 0x15
26 // Command for writing status/configuration register
27 #define QSPI_CMD_WRSR 0x01
28 // Command for reading security register
29 #define QSPI_CMD_RDSCUR 0x2B
30 
31 // Command for setting Reset Enable
32 #define QSPI_CMD_RSTEN 0x66
33 // Command for setting Reset
34 #define QSPI_CMD_RST 0x99
35 
36 // Command for setting write enable
37 #define QSPI_CMD_WREN 0x06
38 // Command for setting write disable
39 #define QSPI_CMD_WRDI 0x04
40 
41 // WRSR operations max time [us] (datasheet max time + 15%)
42 #define QSPI_WRSR_MAX_TIME 34500 // 30ms
43 // general wait max time [us]
44 #define QSPI_WAIT_MAX_TIME 100000 // 100ms
45 
46 
47 // Commands for writing (page programming)
48 #define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
49 #define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
50 
51 // write operations max time [us] (datasheet max time + 15%)
52 #define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
53 
54 #define QSPI_PAGE_SIZE 256 // 256B
55 #define QSPI_SECTOR_SIZE 4096 // 4kB
56 #define QSPI_SECTOR_COUNT 32 // adjusted to MX25R1035F smallest one from MX25RXX35F family
57 
58 // Commands for reading
59 #define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
60 #define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
61 #define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
62 #define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
63 #define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
64 #define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
65 
66 #define QSPI_READ_1IO_DUMMY_CYCLE 0
67 #define QSPI_READ_FAST_DUMMY_CYCLE 8
68 #define QSPI_READ_2IO_DUMMY_CYCLE 4
69 #define QSPI_READ_1I2O_DUMMY_CYCLE 8
70 #define QSPI_READ_4IO_DUMMY_CYCLE 6
71 #define QSPI_READ_1I4O_DUMMY_CYCLE 8
72 
73 // Commands for erasing
74 #define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
75 #define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
76 #define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
77 #define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
78 
79 // erase operations max time [us] (datasheet max time + 15%)
80 #define QSPI_ERASE_SECTOR_MAX_TIME 276000 // 240 ms
81 #define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s
82 #define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
83 
84 // max frequency for basic rw operation (for fast mode)
85 #define QSPI_COMMON_MAX_FREQUENCY 32000000
86 
87 #define QSPI_STATUS_REG_SIZE 1
88 #define QSPI_CONFIG_REG_0_SIZE 2
89 #define QSPI_SECURITY_REG_SIZE 1
90 #define QSPI_MAX_REG_SIZE 2
91 
92 // status register
93 #define STATUS_BIT_WIP (1 << 0) // write in progress bit
94 #define STATUS_BIT_WEL (1 << 1) // write enable latch
95 #define STATUS_BIT_BP0 (1 << 2) //
96 #define STATUS_BIT_BP1 (1 << 3) //
97 #define STATUS_BIT_BP2 (1 << 4) //
98 #define STATUS_BIT_BP3 (1 << 5) //
99 #define STATUS_BIT_QE (1 << 6) // Quad Enable
100 #define STATUS_BIT_SRWD (1 << 7) // status register write protect
101 
102 // configuration register 0
103 // bit 0, 1, 2, 4, 5, 7 reserved
104 #define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
105 #define CONFIG0_BIT_DC (1 << 6) // Dummy Cycle
106 
107 // configuration register 1
108 // bit 0, 2, 3, 4, 5, 6, 7 reserved
109 #define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
110 
111 
112 
113 #define EXTENDED_SPI_ENABLE() \
114  \
115  const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
116  uint8_t reg_data[reg_size] = { 0 }; \
117  \
118  if (read_register(STATUS_REG, reg_data, \
119  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
120  return QSPI_STATUS_ERROR; \
121  } \
122  if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
123  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
124  return QSPI_STATUS_ERROR; \
125  } \
126  \
127  if (write_enable(qspi) != QSPI_STATUS_OK) { \
128  return QSPI_STATUS_ERROR; \
129  } \
130  \
131  reg_data[0] = STATUS_BIT_QE; \
132  if (write_register(QSPI_CMD_WRSR, reg_data, \
133  reg_size, qspi) != QSPI_STATUS_OK) { \
134  return QSPI_STATUS_ERROR; \
135  } \
136  WAIT_FOR(WRSR_MAX_TIME, qspi); \
137  \
138  memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
139  if (read_register(STATUS_REG, reg_data, \
140  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
141  return QSPI_STATUS_ERROR; \
142  } \
143  \
144  return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
145  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
146 
147 
148 
149 #define EXTENDED_SPI_DISABLE() \
150  \
151  const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
152  uint8_t reg_data[reg_size] = { 0 }; \
153  \
154  if (read_register(STATUS_REG, reg_data, \
155  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
156  return QSPI_STATUS_ERROR; \
157  } \
158  if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
159  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
160  return QSPI_STATUS_ERROR; \
161  } \
162  \
163  if (write_enable(qspi) != QSPI_STATUS_OK) { \
164  return QSPI_STATUS_ERROR; \
165  } \
166  \
167  reg_data[0] &= ~(STATUS_BIT_QE); \
168  \
169  if (write_register(QSPI_CMD_WRSR, reg_data, \
170  reg_size, qspi) != QSPI_STATUS_OK) { \
171  return QSPI_STATUS_ERROR; \
172  } \
173  WAIT_FOR(WRSR_MAX_TIME, qspi); \
174  \
175  reg_data[0] = 0; \
176  if (read_register(STATUS_REG, reg_data, \
177  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
178  return QSPI_STATUS_ERROR; \
179  } \
180  \
181  return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
182  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
183 
184 
185 
186 #define FAST_MODE_ENABLE() \
187  \
188  const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
189  uint8_t reg_data[reg_size]; \
190  \
191  if (read_register(STATUS_REG, reg_data, \
192  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
193  return QSPI_STATUS_ERROR; \
194  } \
195  if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
196  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
197  return QSPI_STATUS_ERROR; \
198  } \
199  \
200  if (write_enable(qspi) != QSPI_STATUS_OK) { \
201  return QSPI_STATUS_ERROR; \
202  } \
203  \
204  reg_data[2] |= CONFIG1_BIT_LH; \
205  if (write_register(QSPI_CMD_WRSR, reg_data, \
206  reg_size, qspi) != QSPI_STATUS_OK) { \
207  return QSPI_STATUS_ERROR; \
208  } \
209  WAIT_FOR(WRSR_MAX_TIME, qspi); \
210  \
211  if (read_register(CONFIG_REG0, reg_data, \
212  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
213  return QSPI_STATUS_ERROR; \
214  } \
215  \
216  return ((reg_data[1] & CONFIG1_BIT_LH) != 0 ? \
217  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
218 
219 
220 #define FAST_MODE_DISABLE() \
221  \
222  const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
223  uint8_t reg_data[reg_size]; \
224  \
225  if (read_register(STATUS_REG, reg_data, \
226  QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
227  return QSPI_STATUS_ERROR; \
228  } \
229  if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
230  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
231  return QSPI_STATUS_ERROR; \
232  } \
233  \
234  if (write_enable(qspi) != QSPI_STATUS_OK) { \
235  return QSPI_STATUS_ERROR; \
236  } \
237  \
238  reg_data[2] &= ~(CONFIG1_BIT_LH); \
239  if (write_register(QSPI_CMD_WRSR, reg_data, \
240  reg_size, qspi) != QSPI_STATUS_OK) { \
241  return QSPI_STATUS_ERROR; \
242  } \
243  WAIT_FOR(WRSR_MAX_TIME, qspi); \
244  \
245  if (read_register(CONFIG_REG0, reg_data, \
246  QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
247  return QSPI_STATUS_ERROR; \
248  } \
249  \
250  return ((reg_data[1] & CONFIG1_BIT_LH) == 0 ? \
251  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
252 
253 
254 #endif // MBED_QSPI_FLASH_MX25RXX35F_H
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