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MT25Q_config.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018 ARM Limited
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 #ifndef MBED_QSPI_FLASH_MT25Q_H
18 #define MBED_QSPI_FLASH_MT25Q_H
19 #define QSPI_FLASH_CHIP_STRING "Micron MT25Q"
20 // Command for reading status register
21 #define QSPI_CMD_RDSR 0x05
22 // Command for reading configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
23 #define QSPI_CMD_RDCR0 0xB5
24 // Command for reading configuration register 1 (VOLATILE CONFIGURATION REGISTER)
25 #define QSPI_CMD_RDCR1 0x85
26 // Command for reading configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
27 #define QSPI_CMD_RDCR2 0x65
28 // Command for writing status register
29 #define QSPI_CMD_WRSR 0x01
30 // Command for writing configuration register 0 (NONVOLATILE CONFIGURATION REGISTER)
31 #define QSPI_CMD_WRCR0 0xB1
32 // Command for writing configuration register 1 (VOLATILE CONFIGURATION REGISTER)
33 #define QSPI_CMD_WRCR1 0x81
34 // Command for writing configuration register 2 (ENHANCED VOLATILE CONFIGURATION REGISTER)
35 #define QSPI_CMD_WRCR2 0x61
36 // Command for setting Reset Enable
37 #define QSPI_CMD_RSTEN 0x66
38 // Command for setting Reset
39 #define QSPI_CMD_RST 0x99
40 // Command for setting write enable
41 #define QSPI_CMD_WREN 0x06
42 // Command for setting write disable
43 #define QSPI_CMD_WRDI 0x04
44 // WRSR operations max time [us] (datasheet max time + 15%)
45 #define QSPI_WRSR_MAX_TIME 9200 // 8ms
46 // general wait max time [us]
47 #define QSPI_WAIT_MAX_TIME 100000 // 100ms
48 // Commands for writing (page programming)
49 #define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
50 #define QSPI_CMD_WRITE_1I2O 0xA2 // 1-1-2 mode
51 #define QSPI_CMD_WRITE_2IO 0xD2 // 1-2-2 mode
52 #define QSPI_CMD_WRITE_1I4O 0x32 // 1-1-4 mode
53 #define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
54 #define QSPI_CMD_WRITE_DPI 0xD2 // 2-2-2 mode
55 #define QSPI_CMD_WRITE_QPI 0x38 // 4-4-4 mode
56 // write operations max time [us] (datasheet max time + 15%)
57 #define QSPI_PAGE_PROG_MAX_TIME 2070 // 1.8ms
58 #define QSPI_PAGE_SIZE 256 // 256B
59 #define QSPI_SECTOR_SIZE 4096 // 4kB
60 #define QSPI_SECTOR_COUNT 4096 // for 128Mb chip
61 // Commands for reading
62 #define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
63 #define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
64 #define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
65 #define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
66 #define QSPI_CMD_READ_DPI 0xBB // 2-2-2 mode
67 #define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
68 #define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
69 #define QSPI_CMD_READ_QPI 0xEB // 4-4-4 mode
70 #define QSPI_READ_1IO_DUMMY_CYCLE 0 // 1-1-1 mode
71 #define QSPI_READ_FAST_DUMMY_CYCLE 8 // 1-1-1 mode
72 #define QSPI_READ_1I2O_DUMMY_CYCLE 8 // 1-1-2 mode
73 #define QSPI_READ_2IO_DUMMY_CYCLE 8 // 1-2-2 mode
74 #define QSPI_READ_DPI_DUMMY_CYCLE 8 // 2-2-2 mode
75 #define QSPI_READ_1I4O_DUMMY_CYCLE 8 // 1-1-4 mode
76 #define QSPI_READ_4IO_DUMMY_CYCLE 10 // 1-4-4 mode
77 #define QSPI_READ_QPI_DUMMY_CYCLE 10 // 4-4-4 mode
78 // Commands for erasing
79 #define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
80 #define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
81 #define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
82 #define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
83 // erase operations max time [us] (datasheet max time + 15%)
84 #define QSPI_ERASE_SECTOR_MAX_TIME 460000 // 0.4s
85 #define QSPI_ERASE_BLOCK_32_MAX_TIME 1150000 // 1s
86 #define QSPI_ERASE_BLOCK_64_MAX_TIME 1150000 // 1s
87 // max frequency for basic rw operation
88 #define QSPI_COMMON_MAX_FREQUENCY 50000000
89 #define QSPI_STATUS_REG_SIZE 1
90 #define QSPI_CONFIG_REG_0_SIZE 2
91 #define QSPI_CONFIG_REG_1_SIZE 1
92 #define QSPI_CONFIG_REG_2_SIZE 1
93 #define QSPI_MAX_REG_SIZE 2
94 // status register
95 #define STATUS_BIT_WIP (1 << 0) // write in progress bit
96 #define STATUS_BIT_WEL (1 << 1) // write enable latch
97 #define STATUS_BIT_BP0 (1 << 2) // Block protect
98 #define STATUS_BIT_BP1 (1 << 3) // Block protect
99 #define STATUS_BIT_BP2 (1 << 4) // Block protect
100 #define STATUS_BIT_BP_TB (1 << 5) // Block protect top/bottom
101 #define STATUS_BIT_BP3 (1 << 6) // Block protect
102 #define STATUS_BIT_SRWD (1 << 7) // status register write protect
103 // configuration register 0 (Nonvolatile Configuration Register)
104 // bit 0, 1 reserved
105 #define CONFIG0_BIT_DE (1 << 2) // Dual Enable 0 = Enabled / 1 = Disabled
106 #define CONFIG0_BIT_QE (1 << 3) // Quad Enable 0 = Enabled / 1 = Disabled
107 #define CONFIG0_BIT_RH (1 << 4) // Reset/hold
108 #define CONFIG0_BIT_DTR (1 << 5) // Double transfer rate protocol
109 #define CONFIG0_BIT_ODS0 (1 << 6) // Output driver strength
110 #define CONFIG0_BIT_ODS1 (1 << 7) // Output driver strength
111 #define CONFIG0_BIT_ODS2 (1 << 8) // Output driver strength
112 #define CONFIG0_BIT_XIP_MODE0 (1 << 9) // XIP mode at power-on reset
113 #define CONFIG0_BIT_XIP_MODE1 (1 << 10) // XIP mode at power-on reset
114 #define CONFIG0_BIT_XIP_MODE2 (1 << 11) // XIP mode at power-on reset
115 #define CONFIG0_BIT_DCYCLE0 (1 << 12) // Dummy Cycle
116 #define CONFIG0_BIT_DCYCLE1 (1 << 13) // Dummy Cycle
117 #define CONFIG0_BIT_DCYCLE2 (1 << 14) // Dummy Cycle
118 #define CONFIG0_BIT_DCYCLE3 (1 << 15) // Dummy Cycle
119 // configuration register 1 (Volatile Configuration Register)
120 // bit 2, reserved
121 #define CONFIG1_BIT_WRAP0 (1 << 0) // Output data wrap
122 #define CONFIG1_BIT_WRAP1 (1 << 1) // Output data wrap
123 #define CONFIG1_BIT_XIP (1 << 3) // 0 = Enable / 1 = Disable (default)
124 #define CONFIG1_BIT_DCYCLE0 (1 << 4) // Number of dummy clock cycles
125 #define CONFIG1_BIT_DCYCLE1 (1 << 5) // Number of dummy clock cycles
126 #define CONFIG1_BIT_DCYCLE2 (1 << 6) // Number of dummy clock cycles
127 #define CONFIG1_BIT_DCYCLE3 (1 << 7) // Number of dummy clock cycles
128 // configuration register 2 (Enhanced Volatile Configuration Register)
129 // bit 3, reserved
130 #define CONFIG2_BIT_ODS0 (1 << 0) // Output driver strength 111 = 30 Ohms (Default)
131 #define CONFIG2_BIT_ODS1 (1 << 1) // Output driver strength
132 #define CONFIG2_BIT_ODS2 (1 << 2) // Output driver strength
133 #define CONFIG2_BIT_RH (1 << 4) // Reset/hold
134 #define CONFIG2_BIT_DTR (1 << 5) // Double transfer rate protocol
135 #define CONFIG2_BIT_DE (1 << 6) // Dual I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
136 #define CONFIG2_BIT_QE (1 << 7) // Quad I/O protocol 0 = Enabled / 1 = Disabled (Default, extended SPI protocol)
137 #define DUAL_ENABLE() \
138  \
139  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
140  \
141  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
142  if (read_register(QSPI_CMD_RDCR2, reg_data, \
143  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
144  return QSPI_STATUS_ERROR; \
145  } \
146  if (write_enable(qspi) != QSPI_STATUS_OK) { \
147  return QSPI_STATUS_ERROR; \
148  } \
149  \
150  reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_DE); \
151  if (write_register(QSPI_CMD_WRCR2, reg_data, \
152  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
153  return QSPI_STATUS_ERROR; \
154  } \
155  qspi.cmd.configure(MODE_2_2_2, ADDR_SIZE_24, ALT_SIZE_8); \
156  WAIT_FOR(WRSR_MAX_TIME, qspi); \
157  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
158  if (read_register(QSPI_CMD_RDCR2, reg_data, \
159  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
160  return QSPI_STATUS_ERROR; \
161  } \
162  \
163  return ((reg_data[0] & (CONFIG2_BIT_DE)) == 0 ? \
164  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
165 #define DUAL_DISABLE() \
166  \
167  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
168  \
169  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
170  if (read_register(QSPI_CMD_RDCR2, reg_data, \
171  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
172  return QSPI_STATUS_ERROR; \
173  } \
174  if (write_enable(qspi) != QSPI_STATUS_OK) { \
175  return QSPI_STATUS_ERROR; \
176  } \
177  \
178  reg_data[0] = reg_data[0] | (CONFIG2_BIT_DE); \
179  if (write_register(QSPI_CMD_WRCR2, reg_data, \
180  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
181  return QSPI_STATUS_ERROR; \
182  } \
183  qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
184  WAIT_FOR(WRSR_MAX_TIME, qspi); \
185  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
186  if (read_register(QSPI_CMD_RDCR2, reg_data, \
187  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
188  return QSPI_STATUS_ERROR; \
189  } \
190  \
191  return ((reg_data[0] & CONFIG2_BIT_DE) != 1 ? \
192  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
193 #define QUAD_ENABLE() \
194  \
195  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
196  \
197  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
198  if (read_register(QSPI_CMD_RDCR2, reg_data, \
199  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
200  return QSPI_STATUS_ERROR; \
201  } \
202  if (write_enable(qspi) != QSPI_STATUS_OK) { \
203  return QSPI_STATUS_ERROR; \
204  } \
205  \
206  reg_data[0] = reg_data[0] & ~(CONFIG2_BIT_QE); \
207  if (write_register(QSPI_CMD_WRCR2, reg_data, \
208  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
209  return QSPI_STATUS_ERROR; \
210  } \
211  qspi.cmd.configure(MODE_4_4_4, ADDR_SIZE_24, ALT_SIZE_8); \
212  WAIT_FOR(WRSR_MAX_TIME, qspi); \
213  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
214  if (read_register(QSPI_CMD_RDCR2, reg_data, \
215  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
216  return QSPI_STATUS_ERROR; \
217  } \
218  \
219  return ((reg_data[0] & (CONFIG2_BIT_QE)) == 0 ? \
220  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
221 #define QUAD_DISABLE() \
222  \
223  uint8_t reg_data[QSPI_CONFIG_REG_2_SIZE]; \
224  \
225  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
226  if (read_register(QSPI_CMD_RDCR2, reg_data, \
227  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
228  return QSPI_STATUS_ERROR; \
229  } \
230  if (write_enable(qspi) != QSPI_STATUS_OK) { \
231  return QSPI_STATUS_ERROR; \
232  } \
233  \
234  reg_data[0] = reg_data[0] | (CONFIG2_BIT_QE); \
235  if (write_register(QSPI_CMD_WRCR2, reg_data, \
236  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
237  return QSPI_STATUS_ERROR; \
238  } \
239  qspi.cmd.configure(MODE_1_1_1, ADDR_SIZE_24, ALT_SIZE_8); \
240  WAIT_FOR(WRSR_MAX_TIME, qspi); \
241  memset(reg_data, 0, QSPI_CONFIG_REG_2_SIZE); \
242  if (read_register(QSPI_CMD_RDCR2, reg_data, \
243  QSPI_CONFIG_REG_2_SIZE, qspi) != QSPI_STATUS_OK) { \
244  return QSPI_STATUS_ERROR; \
245  } \
246  \
247  return ((reg_data[0] & CONFIG2_BIT_QE) != 1 ? \
248  QSPI_STATUS_OK : QSPI_STATUS_ERROR)
249 #endif // MBED_QSPI_FLASH_MT25Q_H
250 
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