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val.h
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1 /** @file
2  * Copyright (c) 2018-2019, Arm Limited or its affiliates. All rights reserved.
3  * SPDX-License-Identifier : Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16 **/
17 
18 #ifndef _VAL_COMMON_H_
19 #define _VAL_COMMON_H_
20 
21 #include "pal_common.h"
22 
23 #ifndef VAL_NSPE_BUILD
24 #define STATIC_DECLARE static
25 #else
26 #define STATIC_DECLARE
27 #endif
28 
29 #ifndef __WEAK
30 #define __WEAK __attribute__((weak))
31 #endif
32 
33 #ifndef __UNUSED
34 #define __UNUSED __attribute__((unused))
35 #endif
36 
37 #ifndef TRUE
38 #define TRUE 0
39 #endif
40 #ifndef FALSE
41 #define FALSE 1
42 #endif
43 
44 #ifndef INT_MAX
45 #define INT_MAX 0xFFFFFFFF
46 #endif
47 
48 #define _CONCAT(A,B) A##B
49 #define CONCAT(A,B) _CONCAT(A,B)
50 
51 /* test status defines */
52 #define TEST_START 0x01
53 #define TEST_END 0x02
54 #define TEST_PASS 0x04
55 #define TEST_FAIL 0x08
56 #define TEST_SKIP 0x10
57 #define TEST_PENDING 0x20
58 
59 #define TEST_NUM_BIT 32
60 #define TEST_STATE_BIT 8
61 #define TEST_STATUS_BIT 0
62 
63 #define TEST_NUM_MASK 0xFFFFFFFF
64 #define TEST_STATE_MASK 0xFF
65 #define TEST_STATUS_MASK 0xFF
66 
67 #define RESULT_START(status) (((TEST_START) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
68 #define RESULT_END(status) (((TEST_END) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
69 #define RESULT_PASS(status) (((TEST_PASS) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
70 #define RESULT_FAIL(status) (((TEST_FAIL) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
71 #define RESULT_SKIP(status) (((TEST_SKIP) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
72 #define RESULT_PENDING(status) (((TEST_PENDING) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
73 
74 #define IS_TEST_FAIL(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_FAIL)
75 #define IS_TEST_PASS(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_PASS)
76 #define IS_TEST_SKIP(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_SKIP)
77 #define IS_TEST_PENDING(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_PENDING)
78 #define IS_TEST_START(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_START)
79 #define IS_TEST_END(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_END)
80 #define VAL_ERROR(status) ((status & TEST_STATUS_MASK) ? 1 : 0)
81 
82 
83 
84 /* Test Defines */
85 #define TEST_PUBLISH(test_id, entry)
86 
87 #define VAL_MAX_TEST_PER_COMP 200
88 #define VAL_FF_BASE 0
89 #define VAL_CRYPTO_BASE 1
90 #define VAL_PROTECTED_STORAGE_BASE 2
91 #define VAL_INTERNAL_TRUSTED_STORAGE_BASE 3
92 #define VAL_INITIAL_ATTESTATION_BASE 4
93 
94 #define VAL_GET_COMP_NUM(test_id) \
95  ((test_id - (test_id % VAL_MAX_TEST_PER_COMP)) / VAL_MAX_TEST_PER_COMP)
96 #define VAL_GET_TEST_NUM(test_id) (test_id % VAL_MAX_TEST_PER_COMP)
97 #define VAL_CREATE_TEST_ID(comp,num) ((comp*VAL_MAX_TEST_PER_COMP) + num)
98 
99 #define TEST_FIELD(num1,num2) (num2 << 8 | num1)
100 #define GET_TEST_ISOLATION_LEVEL(num) (num & 0x3)
101 #define GET_WD_TIMOUT_TYPE(num) ((num >> 8) & 0x7)
102 
103 #define TEST_CHECKPOINT_NUM(n) n
104 #define TEST(n) n
105 #define BLOCK(n) n
106 
107 #define BLOCK_NUM_POS 8
108 #define ACTION_POS 16
109 #define GET_TEST_NUM(n) (0xff & n)
110 #define GET_BLOCK_NUM(n) ((n >> BLOCK_NUM_POS) & 0xff)
111 
112 #define GET_ACTION_NUM(n) ((n >> ACTION_POS) & 0xff)
113 #define TEST_EXECUTE_FUNC 1
114 #define TEST_RETURN_RESULT 2
115 #define INVALID_HANDLE 0x1234DEAD
116 
117 #define VAL_NVMEM_BLOCK_SIZE 4
118 #define VAL_NVMEM_OFFSET(nvmem_idx) (nvmem_idx * VAL_NVMEM_BLOCK_SIZE)
119 
120 #define UART_INIT_SIGN 0xff
121 #define UART_PRINT_SIGN 0xfe
122 
123 #define TEST_PANIC() \
124  do { \
125  } while(1)
126 
127 #define TEST_ASSERT_EQUAL(arg1, arg2, checkpoint) \
128  do { \
129  if ((arg1) != arg2) \
130  { \
131  val->print(PRINT_ERROR, "\tFailed at Checkpoint: %d\n", checkpoint); \
132  val->print(PRINT_ERROR, "\tActual: %d\n", arg1); \
133  val->print(PRINT_ERROR, "\tExpected: %d\n", arg2); \
134  return 1; \
135  } \
136  } while (0)
137 
138 #define TEST_ASSERT_DUAL(arg1, status1, status2, checkpoint) \
139  do { \
140  if ((arg1) != status1 && (arg1) != status2) \
141  { \
142  val->print(PRINT_ERROR, "\tFailed at Checkpoint: %d\n", checkpoint); \
143  val->print(PRINT_ERROR, "\tActual: %d\n", arg1); \
144  val->print(PRINT_ERROR, "\tExpected: %d", status1); \
145  val->print(PRINT_ERROR, "or %d\n", status2); \
146  return 1; \
147  } \
148  } while (0)
149 
150 #define TEST_ASSERT_NOT_EQUAL(arg1, arg2, checkpoint) \
151  do { \
152  if ((arg1) == arg2) \
153  { \
154  val->print(PRINT_ERROR, "\tFailed at Checkpoint: %d\n", checkpoint); \
155  val->print(PRINT_ERROR, "\tValue: %d\n", arg1); \
156  return 1; \
157  } \
158  } while (0)
159 
160 #define TEST_ASSERT_MEMCMP(buf1, buf2, size, checkpoint) \
161  do { \
162  if (memcmp(buf1, buf2, size)) \
163  { \
164  val->print(PRINT_ERROR, "\tFailed at Checkpoint: %d : ", checkpoint); \
165  val->print(PRINT_ERROR, "Unequal data in compared buffers\n", 0); \
166  return 1; \
167  } \
168  } while (0)
169 
170 /* enums */
171 typedef enum {
172  NONSECURE = 0x0,
173  SECURE = 0x1,
174 } security_t;
175 
176 typedef enum {
177  TEST_ISOLATION_L1 = 0x1,
178  TEST_ISOLATION_L2 = 0x2,
179  TEST_ISOLATION_L3 = 0x3,
180 } test_isolation_level_t;
181 
182 typedef enum {
183  BOOT_UNKNOWN = 0x1,
184  BOOT_NOT_EXPECTED = 0x2,
185  BOOT_EXPECTED_NS = 0x3,
186  BOOT_EXPECTED_S = 0x4,
187  BOOT_EXPECTED_BUT_FAILED = 0x5,
188  BOOT_EXPECTED_CRYPTO = 0x6,
189 } boot_state_t;
190 
191 typedef enum {
192  NV_BOOT = 0x0,
193  NV_TEST_ID_PREVIOUS = 0x1,
194  NV_TEST_ID_CURRENT = 0x2,
195  NV_TEST_CNT = 0x3,
196 } nvmem_index_t;
197 
198 /* enums to report test sub-state */
199 typedef enum {
200  VAL_STATUS_SUCCESS = 0x0,
201  VAL_STATUS_INVALID = 0x10,
202  VAL_STATUS_ERROR = 0x11,
203  VAL_STATUS_NOT_FOUND = 0x12,
204  VAL_STATUS_LOAD_ERROR = 0x13,
205  VAL_STATUS_INSUFFICIENT_SIZE = 0x14,
206  VAL_STATUS_CONNECTION_FAILED = 0x15,
207  VAL_STATUS_CALL_FAILED = 0x16,
208  VAL_STATUS_READ_FAILED = 0x17,
209  VAL_STATUS_WRITE_FAILED = 0x18,
210  VAL_STATUS_ISOLATION_LEVEL_NOT_SUPP = 0x19,
211  VAL_STATUS_INIT_FAILED = 0x1A,
212  VAL_STATUS_SPM_FAILED = 0x1B,
213  VAL_STATUS_SPM_UNEXPECTED_BEH = 0x1C,
214  VAL_STATUS_FRAMEWORK_VERSION_FAILED = 0x1D,
215  VAL_STATUS_VERSION_API_FAILED = 0x1E,
216  VAL_STATUS_INVALID_HANDLE = 0x1F,
217  VAL_STATUS_INVALID_MSG_TYPE = 0x20,
218  VAL_STATUS_WRONG_IDENTITY = 0x21,
219  VAL_STATUS_MSG_INSIZE_FAILED = 0x22,
220  VAL_STATUS_MSG_OUTSIZE_FAILED = 0x23,
221  VAL_STATUS_SKIP_FAILED = 0x24,
222  VAL_STATUS_CRYPTO_FAILURE = 0x25,
223  VAL_STATUS_INVALID_SIZE = 0x26,
224  VAL_STATUS_DATA_MISMATCH = 0x27,
225  VAL_STATUS_BOOT_EXPECTED_BUT_FAILED = 0x28,
226  VAL_STATUS_INIT_ALREADY_DONE = 0x29,
227  VAL_STATUS_HEAP_NOT_AVAILABLE = 0x2A,
228  VAL_STATUS_UNSUPPORTED = 0x2B,
229  VAL_STATUS_ERROR_MAX = INT_MAX,
230 } val_status_t;
231 
232 /* verbosity enums */
233 typedef enum {
234  PRINT_INFO = 1,
235  PRINT_DEBUG = 2,
236  PRINT_TEST = 3,
237  PRINT_WARN = 4,
238  PRINT_ERROR = 5,
239  PRINT_ALWAYS = 9
240 } print_verbosity_t;
241 
242 /* Interrupt test function id enums */
243 typedef enum {
244  TEST_PSA_EOI_WITH_NON_INTR_SIGNAL = 1,
245  TEST_PSA_EOI_WITH_MULTIPLE_SIGNALS = 2,
246  TEST_PSA_EOI_WITH_UNASSERTED_SIGNAL = 3,
247  TEST_INTR_SERVICE = 4,
248 } test_intr_fn_id_t;
249 
250 /* typedef's */
251 typedef struct {
252  boot_state_t state;
253 } boot_t;
254 
255 typedef struct {
256  uint32_t pass_cnt:8;
257  uint32_t skip_cnt:8;
258  uint32_t fail_cnt:8;
259  uint32_t sim_error_cnt:8;
260 } test_count_t;
261 
262 typedef struct {
263  uint16_t test_num;
264  uint8_t block_num;
265 } test_info_t;
266 
267 
268 /* struture to capture test state */
269 typedef struct {
270  uint16_t reserved;
271  uint8_t state;
272  uint8_t status;
273 } test_status_buffer_t;
274 
275 typedef int32_t (*client_test_t)(security_t caller);
276 typedef int32_t (*server_test_t)(void);
277 #endif /* VAL_COMMON_H */
pal_common.h
Copyright (c) 2018, Arm Limited or its affiliates.
test_info_t
Definition: val.h:262
test_count_t
Definition: val.h:255
boot_t
Definition: val.h:251
test_status_buffer_t
Definition: val.h:269
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