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whd_chip_reg.h
1 /*
2  * Copyright 2021, Cypress Semiconductor Corporation (an Infineon company)
3  * SPDX-License-Identifier: Apache-2.0
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  */
17 
18 #ifndef INCLUDED_WHD_CHIP_REG_H_
19 #define INCLUDED_WHD_CHIP_REG_H_
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
25 /******************************************************
26 * Architecture Constants
27 ******************************************************/
28 
29 /* D11 registers and SHM */
30 #define D11_BASE_ADDR 0x18001000
31 #define D11_AXI_BASE_ADDR 0xE8000000
32 #define D11_SHM_BASE_ADDR (D11_AXI_BASE_ADDR + 0x4000)
33 
34 #define D11REG_ADDR(offset) (D11_BASE_ADDR + offset)
35 #define D11IHR_ADDR(offset) (D11_AXI_BASE_ADDR + 0x400 + (2 * offset) )
36 #define D11SHM_ADDR(offset) (D11_SHM_BASE_ADDR + offset)
37 
38 #define M_DS1_CTRL_STATUS (0xe0b * 2)
39 
40 /* RMC operational modes */
41 enum ds1_ctrl_status
42 {
43  DS1_SLEEP = 0, /* DS1_SLEEP */
44  MAC_ON = 1, /* MAC_ON */
45  RADIO_PHY_ON = 2, /* RADIO_PHY_ON */
46  DS1_EXIT = 3 /* DS1_EXIT.*/
47 };
48 
49 #define M_DS1_CTRL_SDIO (0xe0c * 2)
50 
51 #define C_DS1_CTRL_SDIO_DS1_SLEEP (1 << 0)
52 #define C_DS1_CTRL_SDIO_MAC_ON (1 << 1)
53 #define C_DS1_CTRL_SDIO_RADIO_PHY_ON (1 << 2)
54 #define C_DS1_CTRL_SDIO_DS1_EXIT (1 << 3)
55 #define C_DS1_CTRL_PROC_DONE (1 << 8)
56 #define C_DS1_CTRL_REQ_VALID (1 << 9)
57 /* MacControl register */
58 #define D11_MACCONTROL_REG D11REG_ADDR(0x120)
59 #define D11_MACCONTROL_REG_SIZE 4
60 #define D11_MACCONTROL_REG_WAKE (1 << 26)
61 #define D11_MACCONTROL_CLEAR_WAKE (0xFBFFFFFF)
62 #define PMU_MINRESMASK (PMU_BASE_ADDRESS + 0x618)
63 #define DEFAULT_43012_MIN_RES_MASK 0x0f8bfe77
64 
65 /* Backplane architecture */
66 #define CHIPCOMMON_BASE_ADDRESS 0x18000000 /* Chipcommon core register region */
67 #define I2S0_BASE_ADDRESS 0x18001000 /* I2S0 core register region */
68 #define I2S1_BASE_ADDRESS 0x18002000 /* I2S1 core register region */
69 #define APPS_ARMCR4_BASE_ADDRESS 0x18003000 /* Apps Cortex-R4 core register region */
70 #define DMA_BASE_ADDRESS 0x18004000 /* DMA core register region */
71 #define GMAC_BASE_ADDRESS 0x18005000 /* GMAC core register region */
72 #define USB20H0_BASE_ADDRESS 0x18006000 /* USB20H0 core register region */
73 #define USB20D_BASE_ADDRESS 0x18007000 /* USB20D core register region */
74 #define SDIOH_BASE_ADDRESS 0x18008000 /* SDIOH Device core register region */
75 #define DOT11MAC_BASE_ADDRESS 0x18001000
76 
77 #define BACKPLANE_ADDRESS_MASK 0x7FFF
78 #define BACKPLANE_WINDOW_SIZE (BACKPLANE_ADDRESS_MASK + 1)
79 
80 #define CHIP_STA_INTERFACE 0
81 #define CHIP_AP_INTERFACE 1
82 #define CHIP_P2P_INTERFACE 2
83 
84 /* Chipcommon registers */
85 #define CHIPCOMMON_CORE_CAPEXT_ADDR ( (uint32_t)(CHIPCOMMON_BASE_ADDRESS + 0x64c) )
86 #define CHIPCOMMON_CORE_CAPEXT_SR_SUPPORTED ( (uint32_t)(1 << 1) )
87 #define CHIPCOMMON_CORE_RCTL_LOGIC_DISABLE ( (uint32_t)(1 << 27) )
88 #define CHIPCOMMON_CORE_RCTL_MACPHY_DISABLE ( (uint32_t)(1 << 26) )
89 #define CHIPCOMMON_CORE_RETENTION_CTL ( (uint32_t)(CHIPCOMMON_BASE_ADDRESS + 0x670) )
90 
91 #define CHIPCOMMON_GPIO_CONTROL ( (uint32_t)(CHIPCOMMON_BASE_ADDRESS + 0x6C) )
92 #define CHIPCOMMON_SR_CONTROL0 ( (uint32_t)(CHIPCOMMON_BASE_ADDRESS + 0x504) )
93 #define CHIPCOMMON_SR_CONTROL1 ( (uint32_t)(CHIPCOMMON_BASE_ADDRESS + 0x508) )
94 
95 /* SOCSRAM core registers */
96 #define SOCSRAM_BANKX_INDEX(wd) ( (uint32_t)(GET_C_VAR(wd, SOCSRAM_BASE_ADDRESS) + 0x10) )
97 #define SOCSRAM_BANKX_PDA(wd) ( (uint32_t)(GET_C_VAR(wd, SOCSRAM_BASE_ADDRESS) + 0x44) )
98 
99 /* PMU core registers */
100 #define RETENTION_CTL(wd) ( (uint32_t)(GET_C_VAR(wd, PMU_BASE_ADDRESS) + 0x670) )
101 #define RCTL_MACPHY_DISABLE ( (uint32_t)(1 << 26) )
102 #define RCTL_LOGIC_DISABLE ( (uint32_t)(1 << 27) )
103 
104 #ifdef __cplusplus
105 } /* extern "C" */
106 #endif
107 
108 #endif /* ifndef INCLUDED_WHD_CHIP_REG_H_ */
109 
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