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hal/tests/TESTS/mbed_hal/ospi/flash_configs/MX25LM51245G_config.h
1 /* mbed Microcontroller Library
2  * Copyright (c) 2018-2020 ARM Limited
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 #ifndef MBED_OSPI_FLASH_MX25LM51245G_H
17 #define MBED_OSPI_FLASH_MX25LM51245G_H
18 
19 
20 #define OSPI_FLASH_CHIP_STRING "macronix MX25LM51245G"
21 
22 #define OSPI_CMD_RDID 0x9F
23 // Command for reading status register
24 #define OSPI_CMD_RDSR 0x05
25 // Command for reading configuration register
26 #define OSPI_CMD_RDCR0 0x15
27 #define OSPI_CMD_RDCR2 0x71
28 // Command for writing status/configuration register
29 #define OSPI_CMD_WRSR 0x01
30 
31 #define OSPI_CMD_WRCR2 0x72
32 
33 // Command for reading security register
34 #define OSPI_CMD_RDSCUR 0x2B
35 
36 // Command for setting Reset Enable
37 #define OSPI_CMD_RSTEN 0x66
38 // Command for setting Reset
39 #define OSPI_CMD_RST 0x99
40 
41 // Command for setting write enable
42 #define OSPI_CMD_WREN 0x06
43 // Command for setting write disable
44 #define OSPI_CMD_WRDI 0x04
45 
46 // WRSR operations max time [us] (datasheet max time + 15%)
47 #define OSPI_WRSR_MAX_TIME 34500 // 30ms
48 // general wait max time [us]
49 #define OSPI_WAIT_MAX_TIME 100000 // 100ms
50 
51 
52 // Commands for writing (page programming)
53 // Only single/octal mode supported with this memory
54 // So only single 1-1-1 mode in this OSPI config
55 //#define OSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
56 #define OSPI_CMD_WRITE_1IO 0x12 // 4 byte addr 1-1-1 mode
57 #define OSPI_CMD_WRITE_OPI 0x12 // 8-8-8 mode
58 
59 // write operations max time [us] (datasheet max time + 15%)
60 #define OSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
61 
62 #define OSPI_PAGE_SIZE 256 // 256B
63 #define OSPI_SECTOR_SIZE 4096 // 4kB
64 #define OSPI_SECTOR_COUNT 2048
65 
66 // Commands for reading
67 // Only single/octal mode supported with this memory
68 // So only single 1-1-1 mode in this OSPI config
69 #define OSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
70 //#define OSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
71 #define OSPI_CMD_READ_1IO 0x13 // 4 byte addr 1-1-1 mode
72 #define OSPI_CMD_READ_OPI 0xEC // 8-8-8 mode
73 #define OSPI_CMD_READ_DOPI 0xEE // 8D-8D-8D mode
74 
75 #define OSPI_READ_1IO_DUMMY_CYCLE 0
76 #define OSPI_READ_FAST_DUMMY_CYCLE 8
77 #define OSPI_READ_8IO_DUMMY_CYCLE 20
78 
79 // Commands for erasing
80 #define OSPI_CMD_ERASE_SECTOR 0x21 // 4kB
81 #define OSPI_CMD_ERASE_SECTOR_4B 0x21 // 4kB
82 //#define OSPI_CMD_ERASE_BLOCK_32 // not supported, only ersae block 64
83 #define OSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
84 #define OSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
85 
86 // erase operations max time [us] (datasheet max time + 15%)
87 #define OSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
88 #define OSPI_ERASE_BLOCK_64_MAX_TIME 2400000 // 2s
89 
90 // max frequency for basic rw operation (for fast mode)
91 #define OSPI_COMMON_MAX_FREQUENCY 66000000
92 
93 #define OSPI_STATUS_REG_SIZE 2 //2 ??
94 #define OSPI_CONFIG_REG_0_SIZE 1
95 #define OSPI_CONFIG_REG_1_SIZE 2
96 #define OSPI_CONFIG_REG_2_SIZE 2 //1 byte in spi and sopi mode;2 byte in dopi
97 #define OSPI_SECURITY_REG_SIZE 1
98 #define OSPI_MAX_REG_SIZE 2
99 
100 // status register
101 #define STATUS_BIT_WIP (1 << 0) // write in progress bit
102 #define STATUS_BIT_WEL (1 << 1) // write enable latch
103 #define STATUS_BIT_BP0 (1 << 2) //
104 #define STATUS_BIT_BP1 (1 << 3) //
105 #define STATUS_BIT_BP2 (1 << 4) //
106 #define STATUS_BIT_BP3 (1 << 5) //
107 //#define STATUS_BIT_QE (1 << 6) // Not supported
108 //#define STATUS_BIT_SRWD (1 << 7) // Not supported
109 
110 // configuration register 0
111 // bit 0, 1, 2, 4, 5, 7 reserved
112 #define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
113 
114 #define CONFIG2_OPI_EN_ADDR 0x00000000
115 
116 // configuration register 2
117 #define CONFIG2_BIT_SOPI_EN (1 << 0) // sopi mode enable
118 #define CONFIG2_BIT_DOPI_EN (1 << 1) // dopi mode enable
119 #define CONFIG2_SPI_EN 0 // spi mode enable
120 
121 #define OCTA_ENABLE() \
122  \
123  uint8_t reg_data[OSPI_CONFIG_REG_2_SIZE]; \
124  \
125  memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
126  if (write_enable(ospi) != OSPI_STATUS_OK) { \
127  return OSPI_STATUS_ERROR; \
128  } \
129  \
130  reg_data[0] = CONFIG2_BIT_SOPI_EN; \
131  ospi.cmd.configure(MODE_1_1_1, ADDR_SIZE_32, ALT_SIZE_8); \
132  if (write_config_register_2(OSPI_CMD_WRCR2, CONFIG2_OPI_EN_ADDR, \
133  reg_data, 1, ospi) != OSPI_STATUS_OK) { \
134  return OSPI_STATUS_ERROR; \
135  } \
136  ospi.cmd.configure(MODE_8_8_8, ADDR_SIZE_32, ALT_SIZE_8); \
137  WAIT_FOR(WRSR_MAX_TIME, ospi); \
138  memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
139  \
140  if (read_config_register_2(OSPI_CMD_RDCR2, CONFIG2_OPI_EN_ADDR, \
141  reg_data, OSPI_CONFIG_REG_2_SIZE, ospi) != OSPI_STATUS_OK) { \
142  return OSPI_STATUS_ERROR; \
143  } \
144  return (reg_data[0] == CONFIG2_BIT_SOPI_EN ? \
145  OSPI_STATUS_OK : OSPI_STATUS_ERROR)
146 
147 
148 #define OCTA_DISABLE() \
149  \
150  uint8_t reg_data[OSPI_CONFIG_REG_2_SIZE]; \
151  \
152  memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
153  if (write_enable(ospi) != OSPI_STATUS_OK) { \
154  return OSPI_STATUS_ERROR; \
155  } \
156  \
157  reg_data[0] = CONFIG2_SPI_EN; \
158  if (write_config_register_2(OSPI_CMD_WRCR2, CONFIG2_OPI_EN_ADDR, \
159  reg_data, 1, ospi) != OSPI_STATUS_OK) { \
160  return OSPI_STATUS_ERROR; \
161  } \
162  ospi.cmd.configure(MODE_1_1_1, ADDR_SIZE_32, ALT_SIZE_8); \
163  WAIT_FOR(WRSR_MAX_TIME, ospi); \
164  memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
165  if (read_config_register_2(OSPI_CMD_RDCR2, CONFIG2_OPI_EN_ADDR, \
166  reg_data, 1, ospi) != OSPI_STATUS_OK) { \
167  return OSPI_STATUS_ERROR; \
168  } \
169  return (reg_data[0] == CONFIG2_SPI_EN ? \
170  OSPI_STATUS_OK : OSPI_STATUS_ERROR)
171 
172 #define OCTA_DTR_ENABLE() \
173  \
174  uint8_t reg_data[OSPI_CONFIG_REG_2_SIZE]; \
175  \
176  memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
177  if (write_enable(ospi) != OSPI_STATUS_OK) { \
178  return OSPI_STATUS_ERROR; \
179  } \
180  \
181  reg_data[0] = CONFIG2_BIT_DOPI_EN; \
182  ospi.cmd.configure(MODE_1_1_1, ADDR_SIZE_32, ALT_SIZE_8); \
183  if (write_config_register_2(OSPI_CMD_WRCR2, CONFIG2_OPI_EN_ADDR, \
184  reg_data, 1, ospi) != OSPI_STATUS_OK) { \
185  return OSPI_STATUS_ERROR; \
186  } \
187  ospi.cmd.configure(MODE_8D_8D_8D, ADDR_SIZE_32, ALT_SIZE_8); \
188  WAIT_FOR(WRSR_MAX_TIME, ospi); \
189  memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
190  if (read_config_register_2(OSPI_CMD_RDCR2, CONFIG2_OPI_EN_ADDR, \
191  reg_data, OSPI_CONFIG_REG_2_SIZE, ospi) != OSPI_STATUS_OK) { \
192  return OSPI_STATUS_ERROR; \
193  } \
194  return (reg_data[0] == CONFIG2_BIT_DOPI_EN ? \
195  OSPI_STATUS_OK : OSPI_STATUS_ERROR)
196 
197 
198 #define OCTA_DTR_DISABLE() \
199  \
200  uint8_t reg_data[OSPI_CONFIG_REG_2_SIZE]; \
201  \
202  memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
203  if (write_enable(ospi) != OSPI_STATUS_OK) { \
204  return OSPI_STATUS_ERROR; \
205  } \
206  \
207  reg_data[0] = CONFIG2_SPI_EN; \
208  if (write_config_register_2(OSPI_CMD_WRCR2, CONFIG2_OPI_EN_ADDR, \
209  reg_data, OSPI_CONFIG_REG_2_SIZE, ospi) != OSPI_STATUS_OK) { \
210  return OSPI_STATUS_ERROR; \
211  } \
212  ospi.cmd.configure(MODE_1_1_1, ADDR_SIZE_32, ALT_SIZE_8); \
213  WAIT_FOR(WRSR_MAX_TIME, ospi); \
214  memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
215  if (read_config_register_2(OSPI_CMD_RDCR2, CONFIG2_OPI_EN_ADDR, \
216  reg_data, OSPI_CONFIG_REG_2_SIZE, ospi) != OSPI_STATUS_OK) { \
217  return OSPI_STATUS_ERROR; \
218  } \
219  return (reg_data[0] == CONFIG2_SPI_EN ? \
220  OSPI_STATUS_OK : OSPI_STATUS_ERROR)
221 
222 #endif // MBED_OSPI_FLASH_MX25LM51245G_H
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