FPGA Pullup mode.

Definition at line 403 of file MbedTester.h.

Read FPGA CI Test Shield firmware.

Read the firmware on the FPGA CI Test Shield. An optional progress callback can be supplied to display progress while the firmware is being read.

Parameters

dest	File to write the firmware to. This file must have been opened as writeable
progress	Optional progress callback called when the percent complete changes

Returns

true if firmware was successfully read, false otherwise

Read FPGA CI Test Shield flash.

Read the entire flash contents of the FPGA CI Test Shield. An optional progress callback can be supplied to display progress while the firmware is being read.

Parameters

dest	File to write the firmware to. This file must have been opened as writeable
progress	Optional progress callback called when the percent complete changes

Returns

true if firmware was successfully read, false otherwise

Program new FPGA CI Test Shield firmware.

Program firmware from the file given. The binary bitstream must be in the correct format and contain a correct CRC or the update will fail. To correctly format a bitstream binary the post_process_bitstream.py script in the fpga-ci-test-shield repository should be used.

Note - release binaries for the FPGA CI Test Shield have already been formatted and can be loaded directly with this function

Parameters

src	File containing the new firmware to program
progress	Optional progress callback called when the percent complete changes

Returns

true if firmware was successfully applied, false otherwise

Get the result of the analog to digital conversion computed on the FPGA in the form of a voltage reading.

The FPGA ADC operates on 0V-1V, which means this function will only ever return a float ranging from 0.0-1.0.

Returns

The conversion result in the form of a voltage measurement for AnalogMuxIn, Eg. a return value of 0.7 means the ADC on the FPGA read 0.7 volts on its analog input

Get the 12-bit analog to digital conversion result from the FPGA.

Returns

12-bit FPGA ADC result for AnalogMuxIn

Similar to 'get_analogmuxin_measurement' but returns the current XADC measurement for ANIN0-3.

Parameters

index

ANIN pin to read (0-3)

Returns

12-bit FPGA ADC result for ANIN0-3

Gets (by reference) the sum of all ANIN ADC results for any of the 4 ANIN pins specified by the index, number of ADC sample sequences that have completed since the XADC was turned on, and the number of FPGA clk cycles that have taken place since the ADC was turned on.

Parameters

index	ANIN pin of which to get sum of results (0-3)
sum	The sum of all specified ANIN pin's ADC results
samples	The number of ADC sample sequences that have completed since the XADC was turned on
cycles	The number of FPGA clk cycles that have taken place since the ADC was turned on

Similar to 'get_analog_in' but returns a voltage reading from ANIN0-3.

Parameters

index

ANIN pin to read (0-3)

Returns

The conversion result in the form of a voltage measurement for ANIN0-3

Get nano seconds between chip select assertion and the first spi clock edge.

Returns

nano seconds between chip select assertion and the first spi clock edge.

Note

Number of nano seconds is calculated based of number of counted clk changes and clk frequency (100 MHz => 1 clk tick corresponds to 10 ns). Accuracy of the returned value is +/- 10 ns.

Get nano seconds between last spi clock edge and chip select de-assertion.

Returns

nano seconds between last spi clock edge and chip select de-assertion.

Note

Number of nano seconds is calculated based of number of counted clk changes and clk frequency (100 MHz => 1 clk tick corresponds to 10 ns). Accuracy of the returned value is +/- 10 ns.

Get the number of cycles that are high (duty cycle) from FPGA pwm.

Returns

FPGA pwm output cycles high

Check if FPGA pwm out is on or off.

Returns

FPGA enable bit (false: off, true: on)

Get the pwm output period of the FPGA.

Returns

FPGA pwm output period in units of clk cycles

Read a checksum of data send to the tester.

Returns

The sum of all bytes sent to the tester since reset.

Get SCLK and SIN states on transmission start and stop.

Returns

latched SCLK and SIN states on transmission start and stop.

Note

Stats are encoded as fallows (bit 0 - LSB):

• bit 0: start SCLK
• bit 1: start SIN
• bit 2: stop SCLK,
• bit 3: stop SIN,
• other: unused

Read the number of transfers which have occurred.

Returns

The number of SPI transfers that have completed since spi was reset.

Read a gpio pin.

Parameters

gpio	Logical pin to read from

Returns

1 if the pin is high 0 if the pin is low

Set value and drive of a gpio pin.

Parameters

gpio	Logical pin to write to
value	0 to set the pin low or non-zero to set it high
driver	0 to set the pin to Hi-Z or non-zero to drive the pin

I2C read on I2C system channels 0, 1, or 2.

Parameters

i2c_index	The number corresponding to the system i2c bus being used (0, 1, or 2)
dev_addr	The I2C address of the device being read from
start_reg	The internal device address where the read will start
data	Data buffer for data to be read into
length	The number of bytes to read

Returns

0 on success (ACK), nonzero on failure (NACK)

I2C read on I2C system channels 0, 1, or 2 (bit banged version of function, bit banged over control channel)

Parameters

sda	System pin used for sda
scl	System pin used for scl
dev_addr	The I2C address of the device being read from
start_reg	The internal device address where the read will start
data	Data buffer for data to be read into
length	The number of bytes to read

Returns

0 on success (ACK), nonzero on failure (NACK)

I2C write on I2C system channels 0, 1, or 2.

Parameters

i2c_index	The number corresponding to the system i2c bus being used (0, 1, or 2)
dev_addr	The I2C address of the device being written to
data	The data to be written
length	The number of bytes to be written

Returns

0 on success (ACK), nonzero on failure (NACK)

I2C write on I2C system channels 0, 1, or 2 (bit banged version of function, bit banged over control channel)

Parameters

sda	System pin used for sda
scl	System pin used for scl
dev_addr	The I2C address of the device being written to
data	The data to be written
length	The number of bytes to be written

Returns

0 on success (ACK), nonzero on failure (NACK)

Read a bit for a specific Mbed pin that is set in the input, output, or configuration registers inside of the IO expander via PinName.

Parameters

pin	Mbed pin whose register bit is being read
reg_type	Pin register to access, options are: MbedTester::RegInput, MbedTester::RegOutput, or MbedTester::RegConfig

Returns

The value of the bit read

Read a bit for a specific Mbed pin that is set in the input, output, or configuration registers inside of the IO expander (this version of the function uses io_expander_i2c_read_bb)

Parameters

pin	Mbed pin whose register bit is being read
reg_type	Pin register to access, options are: MbedTester::RegInput, MbedTester::RegOutput, or MbedTester::RegConfig

Returns

The value of the bit read

Read a bit for a specific Mbed pin that is set in the input, output, or configuration registers inside of the IO expander via pin index.

Parameters

index	Mbed pin index whose register bit is being read
reg_type	Pin register to access, options are: MbedTester::RegInput, MbedTester::RegOutput, or MbedTester::RegConfig

Returns

The value of the bit read

Continue recording metrics on all logical pins.

Resume recording metrics.

Get the number of falling edges.

Parameters

pin	Pin to read the metrics for

Returns

The number of falling edges

Get the longest high pulse recorded.

Parameters

pin	Pin to read the metrics for

Returns

The longest number of 100MHz clock cycles the pin was high

Get the longest low pulse recorded.

Parameters

pin	Pin to read the metrics for

Returns

The longest number of 100MHz clock cycles the pin was low

Get the shortest high pulse recorded.

Parameters

pin	Pin to read the metrics for

Returns

The shortest number of 100MHz clock cycles the pin was high

Get the shortest low pulse recorded.

Parameters

pin	Pin to read the metrics for

Returns

The shortest number of 100MHz clock cycles the pin was low

Get the number of rising edges.

Parameters

pin	Pin to read the metrics for

Returns

The number of rising edges

Start recording metrics on all logical pins.

This function resets all past metrics to 0. To preserve these call io_metrics_continue instead.

Stop recording metrics on all logical pins.

This function should be called before any metrics are read to ensure the value does not change while they are being read.

Reset all peripherals.

This does not reset the pin mappings

Map a physical pin index to the given logical pin.

This function will automatically move the control channel pins to avoid interfering with the mapped pin. The physical pin index does not need to be part of the form factor.

Parameters

physical_index	Index of the physical pin on the board
logical	Logical pin to map to

Reset all pin mappings.

After this call all pins will be unmapped

Map a physical pin to the given logical pin.

This function will automatically move the control channel pins to avoid interfering with the mapped pin.

Parameters

physical	Physical pin on the board
logical	Logical pin to map to

Reset the IO expander modules.

Configure an Mbed pin for a pulldown resistor, pullup resistor, or tristate mode via PinName.

Parameters

pin	Mbed pin whose mode is being set
mode	(MbedTester::PullUp, MbedTester::PullDown, or MbedTester::PullNone)

Returns

0 on success, nonzero on failure

Configure an Mbed pin for a pulldown resistor, pullup resistor, or tristate mode (this version of the function uses io_expander_i2c_read_bb and io_expander_i2c_write_bb)

Parameters

pin	Mbed pin whose mode is being set
mode	(MbedTester::PullUp, MbedTester::PullDown, or MbedTester::PullNone)

Returns

0 on success, nonzero on failure

Configure an Mbed pin for a pulldown resistor, pullup resistor, or tristate mode via pin index.

Parameters

index	Mbed pin index whose mode is being set
mode	(MbedTester::PullUp, MbedTester::PullDown, or MbedTester::PullNone)

Returns

0 on success, nonzero on failure

Read from tester memory.

addr Address to read from

Parameters

data	Buffer to fill with data
size	Number of bytes to read

Reprogram the FPGA.

This function causes the FPGA to reboot and reload RAM contents. This should be used after MbedTester::firmware_update to load the new image.

Reset everything.

This function resets the state of both the FPGA CI Test Shield and the MbedTester object itself.

Reset effects on the FPGA CI Test Shield include:

• All pins are tristated
• All pin mappings are reset
• All pullup/pulldown settings are reset
• All peripherals are reset

Reset effects on the MbedTester object include

• Control channels tristated and freed
• Control channel selection set to automatic
• Most internal state reinitialized

Select the currently active peripheral.

Parameters

peripheral

Active peripheral

Run all self tests.

Returns

true if all self tests pass, false otherwise

Test that all allowed control channels can be used.

Check that all pairs of clk and mosi which aren't in the restricted list can be used.

Note

CLK and MOSI lines are paired, where CLK is always on an even index and MOSI is always on an oddd index: clk_index_N = N * 2 mosi_index_N = N * 2 + 1

This functions sets the control pin management mode to automatic when it completes.

Returns

true if all control channel pairs (clk and mosi) of this configuration can be used, false otherwise

Test that the current control channel works.

Returns

true if communication is successful, false otherwise

Test that all allowed control miso lines can be used.

Check that every pin of this form factor aside from the pins in the restricted list can be used as miso.

Note

This functions sets the control pin management mode to automatic when it completes.

Returns

true if all control channel miso lines of this configuration can be used, false otherwise

Create an analog voltage via the FPGA sys pwm in order to test Mbed AnalogIn.

Parameters

enable	Enable the FPGA system PWM (false: of, true: on)
voltage	The analog voltage that will be created by the FPGA CI test shield (float: 0.0 to 1.0)

Set bit order durring transmission of the spi_slave module.

Parameters

mode	Spi clock mode

Enable automatic selection and update of control pins.

Calling this function configures MbedTester to automatically select and update the control pins. The control pins are moved if the function MbedTester::pin_map_set is called and maps a pin that is being used for control.

Note

Automatic selection and update of control pins is the default. Unless MbedTester::set_control_pins_manual has been called to manually set the control pins this function has no effect.

Set the control pins to use for communication.

Manually set the control pins. Calling this function disables automatic control pin selection and updates. The function MbedTester::pin_map_set must not be used to map over control pins when in this mode.

Parameters

clk	Clock pin to use as the control channel
mosi	Mosi pin to use as the control channel
miso	Miso pin to use as the control channel
aux	Auxillary pin to use as the control cannel

Set full-duplex/half-duplex transmission mode of the spi_slave module.

Parameters

duplex

duplex mode used for the transmission

Set tx/rx symbol count.

TX symbol count RX symbol count

Note

Required only in Half-Duplex mode.

Set the clock mode of the spi_slave module.

Parameters

mode	Spi clock mode

Set the AnalogMuxAddr pins on the FPGA via PinName.

Parameters

pin	The Mbed pin that the analog signal will be routed to

Returns

0 on success, nonzero on failure

Set the AnalogMuxAddr pins on the FPGA via pin index.

Parameters

index

The Mbed pin index that the analog signal will be routed to

Returns

0 on success, nonzero on failure

Turn on/off the analog muxes.

Parameters

val	false: off, true: on

Turn on/off pwm output on FPGA to test Mbed AnalogIn.

Parameters

val	false: off, true: on

Set the pwm output period and number of cycles high (duty cycle) on the FPGA.

Parameters

period	In units of clk cycles
cycles_high	In units of clk cycles

Turn the FPGA ADC on and off (power management data will be collected while the ADC is on)

Parameters

val	FPGA ADC enable bit (false: off, true: on)

Allows safe reading of FPGA ADC related values while the FPGA ADC is on If snapshot is set then the ADC values will be safely latched in the FPGA and safe to read.

The RTL will set snapshot to 0 after 1 clk cycle.

Set symbol size used durring transmission of the spi_slave module.

Parameters

mode	Spi clock mode

Set the current system pin mode to disabled.

This releases any pin mappings that were set by the previous pin mode.

Set the current system pin mode to io expander I2C bus.

Remap physical pins to the io expander I2C bus. The IO expanders are used for setting pullups and pulldowns.

Parameters

index	The index of the I2C bus to connect to
sda_in	Physical pin index for the FPGA to output the state of SDA on
sda_val	Physical pin index for the FPGA to read SDA from. When in this mode the Mbed board must always drive this pin. Driving a 0 causes the FPGA to pull the SDA on the I2C bus low. Setting a 1 causes the FPGA to let SDA on the I2C bus float (and get pulled to 1).
scl_in	Physical pin index for the FPGA to output the state of SCL on
scl_val	Physical pin index for the FPGA to read SCL from. When in this mode the Mbed board must always drive this pin. Driving a 0 causes the FPGA to pull the SCL on the I2C bus low. Setting a 1 causes the FPGA to let SDA on the SCL bus float (and get pulled to 1).

Set the current system pin mode to serial flash.

Remap physical pins to the serial flash the FPGA boots from. This is used for firmware updates.

Parameters

mosi	The physical pin index to connect to serial flash mosi
miso	The physical pin index to connect to serial flash miso
clk	The physical pin index to connect to serial flash clk
ssel	The physical pin index to connect to serial flash cs

Read from the given system pin.

Parameters

pin	The pin to read from

Returns

true if 1 was read, false if 0

Write to the given system pin.

Parameters

pin	The pin to write to
value	The value to output on the pin when driven
true	to drive the output, false to set the output high-z

Returns

true if 1 was read, false if 0

Get the running FPGA firmware version.

Returns

The version of firmware running on the FPGA.

Write to tester memory.

addr Address to write to

Parameters

data	Data to write
size	Number of bytes to write