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targets/hal/TARGET_Freescale/TARGET_K20XX/clk_freqs.h@445:3312ed629f01, 2015-01-15 (annotated)

Committer:
mbed_official
Date:
Thu Jan 15 19:30:07 2015 +0000
Revision:
445:3312ed629f01
Synchronized with git revision e21c65041d9a718f866ed6438e5791b13f9c6d91



Full URL: https://github.com/mbedmicro/mbed/commit/e21c65041d9a718f866ed6438e5791b13f9c6d91/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 445:3312ed629f01 1 /* mbed Microcontroller Library
mbed_official 445:3312ed629f01 2 * Copyright (c) 2006-2015 ARM Limited
mbed_official 445:3312ed629f01 3 *
mbed_official 445:3312ed629f01 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 445:3312ed629f01 5 * you may not use this file except in compliance with the License.
mbed_official 445:3312ed629f01 6 * You may obtain a copy of the License at
mbed_official 445:3312ed629f01 7 *
mbed_official 445:3312ed629f01 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 445:3312ed629f01 9 *
mbed_official 445:3312ed629f01 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 445:3312ed629f01 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 445:3312ed629f01 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 445:3312ed629f01 13 * See the License for the specific language governing permissions and
mbed_official 445:3312ed629f01 14 * limitations under the License.
mbed_official 445:3312ed629f01 15 */
mbed_official 445:3312ed629f01 16 #ifndef CLK_FREQS_H
mbed_official 445:3312ed629f01 17 #define CLK_FREQS_H
mbed_official 445:3312ed629f01 18
mbed_official 445:3312ed629f01 19 #ifdef __cplusplus
mbed_official 445:3312ed629f01 20 extern "C" {
mbed_official 445:3312ed629f01 21 #endif
mbed_official 445:3312ed629f01 22
mbed_official 445:3312ed629f01 23 /*!
mbed_official 445:3312ed629f01 24 * \brief Get the peripheral bus clock frequency
mbed_official 445:3312ed629f01 25 * \return Bus frequency
mbed_official 445:3312ed629f01 26 */
mbed_official 445:3312ed629f01 27 static inline uint32_t bus_frequency(void) {
mbed_official 445:3312ed629f01 28 return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1);
mbed_official 445:3312ed629f01 29 }
mbed_official 445:3312ed629f01 30
mbed_official 445:3312ed629f01 31 /*!
mbed_official 445:3312ed629f01 32 * \brief Get external oscillator (crystal) frequency
mbed_official 445:3312ed629f01 33 * \return External osc frequency
mbed_official 445:3312ed629f01 34 */
mbed_official 445:3312ed629f01 35 static uint32_t extosc_frequency(void) {
mbed_official 445:3312ed629f01 36 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
mbed_official 445:3312ed629f01 37
mbed_official 445:3312ed629f01 38 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
mbed_official 445:3312ed629f01 39 return MCGClock;
mbed_official 445:3312ed629f01 40
mbed_official 445:3312ed629f01 41 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
mbed_official 445:3312ed629f01 42 uint32_t divider, multiplier;
mbed_official 445:3312ed629f01 43 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
mbed_official 445:3312ed629f01 44 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
mbed_official 445:3312ed629f01 45 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 445:3312ed629f01 46 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
mbed_official 445:3312ed629f01 47 divider <<= 5u;
mbed_official 445:3312ed629f01 48 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 445:3312ed629f01 49 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 445:3312ed629f01 50 case 0x0u:
mbed_official 445:3312ed629f01 51 multiplier = 640u;
mbed_official 445:3312ed629f01 52 break;
mbed_official 445:3312ed629f01 53 case 0x20u:
mbed_official 445:3312ed629f01 54 multiplier = 1280u;
mbed_official 445:3312ed629f01 55 break;
mbed_official 445:3312ed629f01 56 case 0x40u:
mbed_official 445:3312ed629f01 57 multiplier = 1920u;
mbed_official 445:3312ed629f01 58 break;
mbed_official 445:3312ed629f01 59 case 0x60u:
mbed_official 445:3312ed629f01 60 multiplier = 2560u;
mbed_official 445:3312ed629f01 61 break;
mbed_official 445:3312ed629f01 62 case 0x80u:
mbed_official 445:3312ed629f01 63 multiplier = 732u;
mbed_official 445:3312ed629f01 64 break;
mbed_official 445:3312ed629f01 65 case 0xA0u:
mbed_official 445:3312ed629f01 66 multiplier = 1464u;
mbed_official 445:3312ed629f01 67 break;
mbed_official 445:3312ed629f01 68 case 0xC0u:
mbed_official 445:3312ed629f01 69 multiplier = 2197u;
mbed_official 445:3312ed629f01 70 break;
mbed_official 445:3312ed629f01 71 case 0xE0u:
mbed_official 445:3312ed629f01 72 default:
mbed_official 445:3312ed629f01 73 multiplier = 2929u;
mbed_official 445:3312ed629f01 74 break;
mbed_official 445:3312ed629f01 75 }
mbed_official 445:3312ed629f01 76
mbed_official 445:3312ed629f01 77 return MCGClock * divider / multiplier;
mbed_official 445:3312ed629f01 78 }
mbed_official 445:3312ed629f01 79 } else { //PLL is selected
mbed_official 445:3312ed629f01 80 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
mbed_official 445:3312ed629f01 81 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
mbed_official 445:3312ed629f01 82 return MCGClock * divider / multiplier;
mbed_official 445:3312ed629f01 83 }
mbed_official 445:3312ed629f01 84 }
mbed_official 445:3312ed629f01 85
mbed_official 445:3312ed629f01 86 //In all other cases either there is no crystal or we cannot determine it
mbed_official 445:3312ed629f01 87 //For example when the FLL is running on the internal reference, and there is also an
mbed_official 445:3312ed629f01 88 //external crystal. However these are unlikely situations
mbed_official 445:3312ed629f01 89 return 0;
mbed_official 445:3312ed629f01 90 }
mbed_official 445:3312ed629f01 91
mbed_official 445:3312ed629f01 92 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
mbed_official 445:3312ed629f01 93 static uint32_t mcgpllfll_frequency(void) {
mbed_official 445:3312ed629f01 94 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
mbed_official 445:3312ed629f01 95 return 0;
mbed_official 445:3312ed629f01 96
mbed_official 445:3312ed629f01 97 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
mbed_official 445:3312ed629f01 98 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
mbed_official 445:3312ed629f01 99 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
mbed_official 445:3312ed629f01 100 return MCGClock;
mbed_official 445:3312ed629f01 101 } else { //PLL is selected
mbed_official 445:3312ed629f01 102 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
mbed_official 445:3312ed629f01 103 return MCGClock;
mbed_official 445:3312ed629f01 104 }
mbed_official 445:3312ed629f01 105
mbed_official 445:3312ed629f01 106 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
mbed_official 445:3312ed629f01 107 //for the peripherals, this is however an unlikely setup
mbed_official 445:3312ed629f01 108 }
mbed_official 445:3312ed629f01 109
mbed_official 445:3312ed629f01 110
mbed_official 445:3312ed629f01 111 #ifdef __cplusplus
mbed_official 445:3312ed629f01 112 }
mbed_official 445:3312ed629f01 113 #endif
mbed_official 445:3312ed629f01 114
mbed_official 445:3312ed629f01 115 #endif