Diff: targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld

Revision:

482:d9a48e768ce0

Parent:

390:35c2c1cf29cd

--- a/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld	Thu Feb 26 09:30:08 2015 +0000
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld	Fri Feb 27 10:00:08 2015 +0000
@@ -1,13 +1,14 @@
-/* Linker script for mbed LPC1768 */
+/* Linker script for mbed RZ_A1H */
 
 /* Linker script to configure memory regions. */
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 512K
-  RAM (rwx) : ORIGIN = 0x20080000, LENGTH = (1M)
-
-  USB_RAM(rwx) : ORIGIN = 0x20180000, LENGTH = 16K
-  ETH_RAM(rwx) : ORIGIN = 0x20280000, LENGTH = 16K
+  ROM   (rx)  : ORIGIN = 0x00000000, LENGTH = 0x02000000
+  BOOT_LOADER (rx) : ORIGIN = 0x18000000, LENGTH = 0x00004000 
+  SFLASH (rx) : ORIGIN = 0x18004000, LENGTH = 0x07FFC000 
+  L_TTB (rw)  : ORIGIN = 0x20000000, LENGTH = 0x00004000 
+  RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000
+  RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000
 }
 
 /* Linker script to place sections and symbol values. Should be used together
@@ -40,9 +41,21 @@
 
 SECTIONS
 {
+    .boot :
+    {
+        KEEP(*(.boot_loader)) 
+    } > BOOT_LOADER 
+
     .text :
     {
+
+        Image$$VECTORS$$Base = .;
+        * (RESET)
+        Image$$VECTORS$$Limit = .;
+        . += 0x00000400;
+
         KEEP(*(.isr_vector))
+        *(SVC_TABLE)
         *(.text*)
 
         KEEP(*(.init))
@@ -62,31 +75,66 @@
         *(SORT(.dtors.*))
         *(.dtors)
 
+        Image$$RO_DATA$$Base = .;
         *(.rodata*)
+        Image$$RO_DATA$$Limit = .;
 
         KEEP(*(.eh_frame*))
-    } > FLASH
+    } > SFLASH
 
     .ARM.extab : 
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
+    } > SFLASH
 
     __exidx_start = .;
     .ARM.exidx :
     {
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
+    } > SFLASH
     __exidx_end = .;
 
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__nc_data_start)
+        LONG (__nc_data_end - __nc_data_start)
+        __copy_table_end__ = .;
+    } > SFLASH
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__nc_bss_start)
+        LONG (__nc_bss_end - __nc_bss_start)
+        __zero_table_end__ = .;
+    } > SFLASH
+
     __etext = .;
         
+    .ttb :
+    {
+        Image$$TTB$$ZI$$Base = .;
+        . += 0x00004000;
+        Image$$TTB$$ZI$$Limit = .;
+    } > L_TTB
+
     .data : AT (__etext)
     {
+        Image$$RW_DATA$$Base = .;
         __data_start__ = .;
-        Image$$RW_RAM1$$Base = .;
         *(vtable)
         *(.data*)
+        Image$$RW_DATA$$Limit = .;
 
         . = ALIGN(4);
         /* preinit data */
@@ -116,13 +164,14 @@
     } > RAM
 
     
-    .bss :
+    .bss ALIGN(0x400):
     {
+        Image$$ZI_DATA$$Base = .;
         __bss_start__ = .;
         *(.bss*)
         *(COMMON)
         __bss_end__ = .;
-        Image$$RW_RAM1$$ZI$$Limit = . ;
+        Image$$ZI_DATA$$Limit = .;
     } > RAM
 
     
@@ -142,6 +191,29 @@
         *(.stack)
     } > RAM
 
+    __etext2 = __etext + SIZEOF(.data);
+    .nc_data : AT (__etext2)
+    {
+        Image$$RW_DATA_NC$$Base = .;
+        __nc_data_start = .;
+        *(NC_DATA)
+
+        . = ALIGN(4);
+        __nc_data_end = .;
+        Image$$RW_DATA_NC$$Limit = .;
+    } > RAM_NC
+
+    .nc_bss (NOLOAD) :
+    {
+        Image$$ZI_DATA_NC$$Base = .;
+        __nc_bss_start = .;
+        *(NC_BSS)
+
+        . = ALIGN(4);
+        __nc_bss_end = .;
+        Image$$ZI_DATA_NC$$Limit = .;
+    } > RAM_NC
+
     /* Set stack top to end of RAM, and stack limit move down by
      * size of stack_dummy section */
     __StackTop = ORIGIN(RAM) + LENGTH(RAM);