Zakaria ElQotbi
mbed library sources for airmote
Fork of
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by 
mbed official
targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scux_iodefine.h@625:88d3fa07e462, 2015-11-24 (annotated)
- Committer:
- zskdan
- Date:
- Tue Nov 24 14:02:46 2015 +0000
- Revision:
- 625:88d3fa07e462
- Parent:
- 390:35c2c1cf29cd
remove unused service
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 390:35c2c1cf29cd | 1 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 2 | * DISCLAIMER |
| mbed_official | 390:35c2c1cf29cd | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| mbed_official | 390:35c2c1cf29cd | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| mbed_official | 390:35c2c1cf29cd | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| mbed_official | 390:35c2c1cf29cd | 6 | * all applicable laws, including copyright laws. |
| mbed_official | 390:35c2c1cf29cd | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| mbed_official | 390:35c2c1cf29cd | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| mbed_official | 390:35c2c1cf29cd | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| mbed_official | 390:35c2c1cf29cd | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| mbed_official | 390:35c2c1cf29cd | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| mbed_official | 390:35c2c1cf29cd | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| mbed_official | 390:35c2c1cf29cd | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| mbed_official | 390:35c2c1cf29cd | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| mbed_official | 390:35c2c1cf29cd | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| mbed_official | 390:35c2c1cf29cd | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| mbed_official | 390:35c2c1cf29cd | 17 | * and to discontinue the availability of this software. By using this software, |
| mbed_official | 390:35c2c1cf29cd | 18 | * you agree to the additional terms and conditions found by accessing the |
| mbed_official | 390:35c2c1cf29cd | 19 | * following link: |
| mbed_official | 390:35c2c1cf29cd | 20 | * http://www.renesas.com/disclaimer* |
| mbed_official | 390:35c2c1cf29cd | 21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. |
| mbed_official | 390:35c2c1cf29cd | 22 | *******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 23 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 24 | * File Name : scux_iodefine.h |
| mbed_official | 390:35c2c1cf29cd | 25 | * $Rev: $ |
| mbed_official | 390:35c2c1cf29cd | 26 | * $Date:: $ |
| mbed_official | 390:35c2c1cf29cd | 27 | * Description : Definition of I/O Register (V1.00a) |
| mbed_official | 390:35c2c1cf29cd | 28 | ******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 29 | #ifndef SCUX_IODEFINE_H |
| mbed_official | 390:35c2c1cf29cd | 30 | #define SCUX_IODEFINE_H |
| mbed_official | 390:35c2c1cf29cd | 31 | /* ->QAC 0639 : Over 127 members (C90) */ |
| mbed_official | 390:35c2c1cf29cd | 32 | /* ->SEC M1.10.1 : Not magic number */ |
| mbed_official | 390:35c2c1cf29cd | 33 | |
| mbed_official | 390:35c2c1cf29cd | 34 | struct st_scux |
| mbed_official | 390:35c2c1cf29cd | 35 | { /* SCUX */ |
| mbed_official | 390:35c2c1cf29cd | 36 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 37 | volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 38 | volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 39 | volatile uint8_t dummy259[248]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 40 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 41 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 42 | volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 43 | volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 44 | volatile uint8_t dummy260[248]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 45 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 46 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 47 | volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 48 | volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 49 | volatile uint8_t dummy261[248]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 50 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 51 | /* start of struct st_scux_from_ipcir_ipc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 52 | volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 53 | volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 54 | volatile uint8_t dummy262[248]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 55 | /* end of struct st_scux_from_ipcir_ipc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 56 | /* start of struct st_scux_from_opcir_opc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 57 | volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 58 | volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 59 | volatile uint8_t dummy263[248]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 60 | /* end of struct st_scux_from_opcir_opc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 61 | /* start of struct st_scux_from_opcir_opc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 62 | volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 63 | volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 64 | volatile uint8_t dummy264[248]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 65 | /* end of struct st_scux_from_opcir_opc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 66 | /* start of struct st_scux_from_opcir_opc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 67 | volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 68 | volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 69 | volatile uint8_t dummy265[248]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 70 | /* end of struct st_scux_from_opcir_opc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 71 | /* start of struct st_scux_from_opcir_opc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 72 | volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 73 | volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 74 | volatile uint8_t dummy266[248]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 75 | /* end of struct st_scux_from_opcir_opc0_n */ |
| mbed_official | 390:35c2c1cf29cd | 76 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
| mbed_official | 390:35c2c1cf29cd | 77 | volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 78 | volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 79 | volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 80 | volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 81 | volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 82 | volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 83 | volatile uint8_t dummy267[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 84 | volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 85 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
| mbed_official | 390:35c2c1cf29cd | 86 | volatile uint8_t dummy268[224]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 87 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
| mbed_official | 390:35c2c1cf29cd | 88 | volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 89 | volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 90 | volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 91 | volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 92 | volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 93 | volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 94 | volatile uint8_t dummy269[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 95 | volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 96 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
| mbed_official | 390:35c2c1cf29cd | 97 | volatile uint8_t dummy270[224]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 98 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
| mbed_official | 390:35c2c1cf29cd | 99 | volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 100 | volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 101 | volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 102 | volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 103 | volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 104 | volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 105 | volatile uint8_t dummy271[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 106 | volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 107 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
| mbed_official | 390:35c2c1cf29cd | 108 | volatile uint8_t dummy272[224]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 109 | /* start of struct st_scux_from_ffdir_ffd0_n */ |
| mbed_official | 390:35c2c1cf29cd | 110 | volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 111 | volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 112 | volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 113 | volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 114 | volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 115 | volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 116 | volatile uint8_t dummy273[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 117 | volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 118 | /* end of struct st_scux_from_ffdir_ffd0_n */ |
| mbed_official | 390:35c2c1cf29cd | 119 | volatile uint8_t dummy274[224]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 120 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 121 | volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 122 | volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 123 | volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 124 | volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 125 | volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 126 | volatile uint8_t dummy275[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 127 | volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 128 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 129 | volatile uint8_t dummy276[228]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 130 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 131 | volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 132 | volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 133 | volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 134 | volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 135 | volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 136 | volatile uint8_t dummy277[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 137 | volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 138 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 139 | volatile uint8_t dummy278[228]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 140 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 141 | volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 142 | volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 143 | volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 144 | volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 145 | volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 146 | volatile uint8_t dummy279[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 147 | volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 148 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 149 | volatile uint8_t dummy280[228]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 150 | /* start of struct st_scux_from_ffuir_ffu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 151 | volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 152 | volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 153 | volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 154 | volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 155 | volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 156 | volatile uint8_t dummy281[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 157 | volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 158 | /* end of struct st_scux_from_ffuir_ffu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 159 | volatile uint8_t dummy282[228]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 160 | /* start of struct st_scux_from_srcir0_2src0_n */ |
| mbed_official | 390:35c2c1cf29cd | 161 | volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 162 | volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 163 | volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 164 | volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 165 | volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 166 | volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 167 | volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 168 | volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 169 | volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 170 | volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 171 | volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 172 | volatile uint8_t dummy283[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 173 | volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 174 | volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 175 | volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 176 | volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 177 | volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 178 | volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 179 | volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 180 | volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 181 | volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 182 | volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 183 | volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 184 | volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 185 | volatile uint8_t dummy284[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 186 | volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 187 | volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 188 | /* end of struct st_scux_from_srcir0_2src0_n */ |
| mbed_official | 390:35c2c1cf29cd | 189 | volatile uint8_t dummy285[148]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 190 | /* start of struct st_scux_from_srcir0_2src0_n */ |
| mbed_official | 390:35c2c1cf29cd | 191 | volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 192 | volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 193 | volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 194 | volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 195 | volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 196 | volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 197 | volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 198 | volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 199 | volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 200 | volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 201 | volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 202 | volatile uint8_t dummy286[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 203 | volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 204 | volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 205 | volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 206 | volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 207 | volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 208 | volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 209 | volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 210 | volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 211 | volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 212 | volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 213 | volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 214 | volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 215 | volatile uint8_t dummy287[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 216 | volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 217 | volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 218 | /* end of struct st_scux_from_srcir0_2src0_n */ |
| mbed_official | 390:35c2c1cf29cd | 219 | volatile uint8_t dummy288[148]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 220 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 221 | volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 222 | volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 223 | volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 224 | volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 225 | volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 226 | volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 227 | volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 228 | volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 229 | volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 230 | volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 231 | volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 232 | volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 233 | volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 234 | volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 235 | volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 236 | volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 237 | volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 238 | volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 239 | volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 240 | volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 241 | volatile uint8_t dummy289[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 242 | volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 243 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 244 | volatile uint8_t dummy290[168]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 245 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 246 | volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 247 | volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 248 | volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 249 | volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 250 | volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 251 | volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 252 | volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 253 | volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 254 | volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 255 | volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 256 | volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 257 | volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 258 | volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 259 | volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 260 | volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 261 | volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 262 | volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 263 | volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 264 | volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 265 | volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 266 | volatile uint8_t dummy291[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 267 | volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 268 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 269 | volatile uint8_t dummy292[168]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 270 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 271 | volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 272 | volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 273 | volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 274 | volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 275 | volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 276 | volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 277 | volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 278 | volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 279 | volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 280 | volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 281 | volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 282 | volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 283 | volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 284 | volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 285 | volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 286 | volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 287 | volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 288 | volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 289 | volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 290 | volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 291 | volatile uint8_t dummy293[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 292 | volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 293 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 294 | volatile uint8_t dummy294[168]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 295 | /* start of struct st_scux_from_dvuir_dvu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 296 | volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 297 | volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 298 | volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 299 | volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 300 | volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 301 | volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 302 | volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 303 | volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 304 | volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 305 | volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 306 | volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 307 | volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 308 | volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 309 | volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 310 | volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 311 | volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 312 | volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 313 | volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 314 | volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 315 | volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 316 | volatile uint8_t dummy295[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 317 | volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 318 | /* end of struct st_scux_from_dvuir_dvu0_n */ |
| mbed_official | 390:35c2c1cf29cd | 319 | volatile uint8_t dummy296[168]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 320 | volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 321 | volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 322 | volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 323 | volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 324 | volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 325 | volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 326 | volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 327 | volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 328 | volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 329 | volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 330 | volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 331 | volatile uint8_t dummy297[212]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 332 | volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 333 | volatile uint32_t DMACR_CIM; /* DMACR_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 334 | #define SCUX_DMATDn_CIM_COUNT 4 |
| mbed_official | 390:35c2c1cf29cd | 335 | union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 336 | union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 337 | union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 338 | union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 339 | #define SCUX_DMATUn_CIM_COUNT 4 |
| mbed_official | 390:35c2c1cf29cd | 340 | union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 341 | union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 342 | union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 343 | union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 344 | |
| mbed_official | 390:35c2c1cf29cd | 345 | volatile uint8_t dummy298[16]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 346 | volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 347 | #define SCUX_FDTSELn_CIM_COUNT 4 |
| mbed_official | 390:35c2c1cf29cd | 348 | volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 349 | volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 350 | volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 351 | volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 352 | #define SCUX_FUTSELn_CIM_COUNT 4 |
| mbed_official | 390:35c2c1cf29cd | 353 | volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 354 | volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 355 | volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 356 | volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 357 | volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 358 | volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 359 | #define SCUX_SRCRSELn_CIM_COUNT 4 |
| mbed_official | 390:35c2c1cf29cd | 360 | volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 361 | volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 362 | volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 363 | volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 364 | volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */ |
| mbed_official | 390:35c2c1cf29cd | 365 | }; |
| mbed_official | 390:35c2c1cf29cd | 366 | |
| mbed_official | 390:35c2c1cf29cd | 367 | |
| mbed_official | 390:35c2c1cf29cd | 368 | struct st_scux_from_ipcir_ipc0_n |
| mbed_official | 390:35c2c1cf29cd | 369 | { |
| mbed_official | 390:35c2c1cf29cd | 370 | volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 371 | volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 372 | volatile uint8_t dummy1[248]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 373 | }; |
| mbed_official | 390:35c2c1cf29cd | 374 | |
| mbed_official | 390:35c2c1cf29cd | 375 | |
| mbed_official | 390:35c2c1cf29cd | 376 | struct st_scux_from_opcir_opc0_n |
| mbed_official | 390:35c2c1cf29cd | 377 | { |
| mbed_official | 390:35c2c1cf29cd | 378 | volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 379 | volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 380 | volatile uint8_t dummy1[248]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 381 | }; |
| mbed_official | 390:35c2c1cf29cd | 382 | |
| mbed_official | 390:35c2c1cf29cd | 383 | |
| mbed_official | 390:35c2c1cf29cd | 384 | struct st_scux_from_ffdir_ffd0_n |
| mbed_official | 390:35c2c1cf29cd | 385 | { |
| mbed_official | 390:35c2c1cf29cd | 386 | volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 387 | volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 388 | volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 389 | volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 390 | volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 391 | volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 392 | volatile uint8_t dummy1[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 393 | volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 394 | }; |
| mbed_official | 390:35c2c1cf29cd | 395 | |
| mbed_official | 390:35c2c1cf29cd | 396 | |
| mbed_official | 390:35c2c1cf29cd | 397 | struct st_scux_from_ffuir_ffu0_n |
| mbed_official | 390:35c2c1cf29cd | 398 | { |
| mbed_official | 390:35c2c1cf29cd | 399 | volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 400 | volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 401 | volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 402 | volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 403 | volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 404 | volatile uint8_t dummy1[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 405 | volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 406 | }; |
| mbed_official | 390:35c2c1cf29cd | 407 | |
| mbed_official | 390:35c2c1cf29cd | 408 | |
| mbed_official | 390:35c2c1cf29cd | 409 | struct st_scux_from_srcir0_2src0_n |
| mbed_official | 390:35c2c1cf29cd | 410 | { |
| mbed_official | 390:35c2c1cf29cd | 411 | volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 412 | volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 413 | volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 414 | volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 415 | volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 416 | volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 417 | volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 418 | volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 419 | volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 420 | volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 421 | volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 422 | volatile uint8_t dummy1[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 423 | volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 424 | volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 425 | volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 426 | volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 427 | volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 428 | volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 429 | volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 430 | volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 431 | volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 432 | volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 433 | volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 434 | volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 435 | volatile uint8_t dummy2[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 436 | volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 437 | volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 438 | }; |
| mbed_official | 390:35c2c1cf29cd | 439 | |
| mbed_official | 390:35c2c1cf29cd | 440 | |
| mbed_official | 390:35c2c1cf29cd | 441 | struct st_scux_from_dvuir_dvu0_n |
| mbed_official | 390:35c2c1cf29cd | 442 | { |
| mbed_official | 390:35c2c1cf29cd | 443 | volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 444 | volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 445 | volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 446 | volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 447 | volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 448 | volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 449 | volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 450 | volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 451 | volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 452 | volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 453 | volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 454 | volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 455 | volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 456 | volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 457 | volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 458 | volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 459 | volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 460 | volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 461 | volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 462 | volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 463 | volatile uint8_t dummy1[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 464 | volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 465 | }; |
| mbed_official | 390:35c2c1cf29cd | 466 | |
| mbed_official | 390:35c2c1cf29cd | 467 | |
| mbed_official | 390:35c2c1cf29cd | 468 | #define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ |
| mbed_official | 390:35c2c1cf29cd | 469 | |
| mbed_official | 390:35c2c1cf29cd | 470 | |
| mbed_official | 390:35c2c1cf29cd | 471 | /* Start of channnel array defines of SCUX */ |
| mbed_official | 390:35c2c1cf29cd | 472 | |
| mbed_official | 390:35c2c1cf29cd | 473 | /* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ |
| mbed_official | 390:35c2c1cf29cd | 474 | /*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ |
| mbed_official | 390:35c2c1cf29cd | 475 | #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4 |
| mbed_official | 390:35c2c1cf29cd | 476 | #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ |
| mbed_official | 390:35c2c1cf29cd | 477 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| mbed_official | 390:35c2c1cf29cd | 478 | &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ |
| mbed_official | 390:35c2c1cf29cd | 479 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| mbed_official | 390:35c2c1cf29cd | 480 | #define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 481 | #define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 482 | #define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 483 | #define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 484 | |
| mbed_official | 390:35c2c1cf29cd | 485 | |
| mbed_official | 390:35c2c1cf29cd | 486 | /* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ |
| mbed_official | 390:35c2c1cf29cd | 487 | /*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ |
| mbed_official | 390:35c2c1cf29cd | 488 | #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2 |
| mbed_official | 390:35c2c1cf29cd | 489 | #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ |
| mbed_official | 390:35c2c1cf29cd | 490 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| mbed_official | 390:35c2c1cf29cd | 491 | &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ |
| mbed_official | 390:35c2c1cf29cd | 492 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| mbed_official | 390:35c2c1cf29cd | 493 | #define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 494 | #define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 495 | |
| mbed_official | 390:35c2c1cf29cd | 496 | |
| mbed_official | 390:35c2c1cf29cd | 497 | /* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ |
| mbed_official | 390:35c2c1cf29cd | 498 | /*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ |
| mbed_official | 390:35c2c1cf29cd | 499 | #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4 |
| mbed_official | 390:35c2c1cf29cd | 500 | #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ |
| mbed_official | 390:35c2c1cf29cd | 501 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| mbed_official | 390:35c2c1cf29cd | 502 | &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ |
| mbed_official | 390:35c2c1cf29cd | 503 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| mbed_official | 390:35c2c1cf29cd | 504 | #define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 505 | #define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 506 | #define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 507 | #define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 508 | |
| mbed_official | 390:35c2c1cf29cd | 509 | |
| mbed_official | 390:35c2c1cf29cd | 510 | /* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ |
| mbed_official | 390:35c2c1cf29cd | 511 | /*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ |
| mbed_official | 390:35c2c1cf29cd | 512 | #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4 |
| mbed_official | 390:35c2c1cf29cd | 513 | #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ |
| mbed_official | 390:35c2c1cf29cd | 514 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| mbed_official | 390:35c2c1cf29cd | 515 | &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ |
| mbed_official | 390:35c2c1cf29cd | 516 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| mbed_official | 390:35c2c1cf29cd | 517 | #define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 518 | #define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 519 | #define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 520 | #define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 521 | |
| mbed_official | 390:35c2c1cf29cd | 522 | |
| mbed_official | 390:35c2c1cf29cd | 523 | /* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ |
| mbed_official | 390:35c2c1cf29cd | 524 | /*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ |
| mbed_official | 390:35c2c1cf29cd | 525 | #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4 |
| mbed_official | 390:35c2c1cf29cd | 526 | #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ |
| mbed_official | 390:35c2c1cf29cd | 527 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| mbed_official | 390:35c2c1cf29cd | 528 | &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ |
| mbed_official | 390:35c2c1cf29cd | 529 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| mbed_official | 390:35c2c1cf29cd | 530 | #define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 531 | #define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 532 | #define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 533 | #define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 534 | |
| mbed_official | 390:35c2c1cf29cd | 535 | |
| mbed_official | 390:35c2c1cf29cd | 536 | /* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ |
| mbed_official | 390:35c2c1cf29cd | 537 | /*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ |
| mbed_official | 390:35c2c1cf29cd | 538 | #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4 |
| mbed_official | 390:35c2c1cf29cd | 539 | #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ |
| mbed_official | 390:35c2c1cf29cd | 540 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| mbed_official | 390:35c2c1cf29cd | 541 | &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ |
| mbed_official | 390:35c2c1cf29cd | 542 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| mbed_official | 390:35c2c1cf29cd | 543 | #define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ |
| mbed_official | 390:35c2c1cf29cd | 544 | #define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ |
| mbed_official | 390:35c2c1cf29cd | 545 | #define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ |
| mbed_official | 390:35c2c1cf29cd | 546 | #define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ |
| mbed_official | 390:35c2c1cf29cd | 547 | |
| mbed_official | 390:35c2c1cf29cd | 548 | /* End of channnel array defines of SCUX */ |
| mbed_official | 390:35c2c1cf29cd | 549 | |
| mbed_official | 390:35c2c1cf29cd | 550 | |
| mbed_official | 390:35c2c1cf29cd | 551 | #define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0 |
| mbed_official | 390:35c2c1cf29cd | 552 | #define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0 |
| mbed_official | 390:35c2c1cf29cd | 553 | #define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1 |
| mbed_official | 390:35c2c1cf29cd | 554 | #define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1 |
| mbed_official | 390:35c2c1cf29cd | 555 | #define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2 |
| mbed_official | 390:35c2c1cf29cd | 556 | #define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2 |
| mbed_official | 390:35c2c1cf29cd | 557 | #define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3 |
| mbed_official | 390:35c2c1cf29cd | 558 | #define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3 |
| mbed_official | 390:35c2c1cf29cd | 559 | #define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0 |
| mbed_official | 390:35c2c1cf29cd | 560 | #define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0 |
| mbed_official | 390:35c2c1cf29cd | 561 | #define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1 |
| mbed_official | 390:35c2c1cf29cd | 562 | #define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1 |
| mbed_official | 390:35c2c1cf29cd | 563 | #define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2 |
| mbed_official | 390:35c2c1cf29cd | 564 | #define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2 |
| mbed_official | 390:35c2c1cf29cd | 565 | #define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3 |
| mbed_official | 390:35c2c1cf29cd | 566 | #define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3 |
| mbed_official | 390:35c2c1cf29cd | 567 | #define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0 |
| mbed_official | 390:35c2c1cf29cd | 568 | #define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0 |
| mbed_official | 390:35c2c1cf29cd | 569 | #define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0 |
| mbed_official | 390:35c2c1cf29cd | 570 | #define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0 |
| mbed_official | 390:35c2c1cf29cd | 571 | #define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0 |
| mbed_official | 390:35c2c1cf29cd | 572 | #define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0 |
| mbed_official | 390:35c2c1cf29cd | 573 | #define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0 |
| mbed_official | 390:35c2c1cf29cd | 574 | #define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1 |
| mbed_official | 390:35c2c1cf29cd | 575 | #define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1 |
| mbed_official | 390:35c2c1cf29cd | 576 | #define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1 |
| mbed_official | 390:35c2c1cf29cd | 577 | #define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1 |
| mbed_official | 390:35c2c1cf29cd | 578 | #define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1 |
| mbed_official | 390:35c2c1cf29cd | 579 | #define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1 |
| mbed_official | 390:35c2c1cf29cd | 580 | #define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1 |
| mbed_official | 390:35c2c1cf29cd | 581 | #define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2 |
| mbed_official | 390:35c2c1cf29cd | 582 | #define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2 |
| mbed_official | 390:35c2c1cf29cd | 583 | #define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2 |
| mbed_official | 390:35c2c1cf29cd | 584 | #define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2 |
| mbed_official | 390:35c2c1cf29cd | 585 | #define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2 |
| mbed_official | 390:35c2c1cf29cd | 586 | #define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2 |
| mbed_official | 390:35c2c1cf29cd | 587 | #define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2 |
| mbed_official | 390:35c2c1cf29cd | 588 | #define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3 |
| mbed_official | 390:35c2c1cf29cd | 589 | #define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3 |
| mbed_official | 390:35c2c1cf29cd | 590 | #define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3 |
| mbed_official | 390:35c2c1cf29cd | 591 | #define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3 |
| mbed_official | 390:35c2c1cf29cd | 592 | #define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3 |
| mbed_official | 390:35c2c1cf29cd | 593 | #define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3 |
| mbed_official | 390:35c2c1cf29cd | 594 | #define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3 |
| mbed_official | 390:35c2c1cf29cd | 595 | #define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0 |
| mbed_official | 390:35c2c1cf29cd | 596 | #define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0 |
| mbed_official | 390:35c2c1cf29cd | 597 | #define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0 |
| mbed_official | 390:35c2c1cf29cd | 598 | #define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0 |
| mbed_official | 390:35c2c1cf29cd | 599 | #define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0 |
| mbed_official | 390:35c2c1cf29cd | 600 | #define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0 |
| mbed_official | 390:35c2c1cf29cd | 601 | #define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1 |
| mbed_official | 390:35c2c1cf29cd | 602 | #define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1 |
| mbed_official | 390:35c2c1cf29cd | 603 | #define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1 |
| mbed_official | 390:35c2c1cf29cd | 604 | #define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1 |
| mbed_official | 390:35c2c1cf29cd | 605 | #define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1 |
| mbed_official | 390:35c2c1cf29cd | 606 | #define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1 |
| mbed_official | 390:35c2c1cf29cd | 607 | #define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2 |
| mbed_official | 390:35c2c1cf29cd | 608 | #define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2 |
| mbed_official | 390:35c2c1cf29cd | 609 | #define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2 |
| mbed_official | 390:35c2c1cf29cd | 610 | #define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2 |
| mbed_official | 390:35c2c1cf29cd | 611 | #define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2 |
| mbed_official | 390:35c2c1cf29cd | 612 | #define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2 |
| mbed_official | 390:35c2c1cf29cd | 613 | #define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3 |
| mbed_official | 390:35c2c1cf29cd | 614 | #define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3 |
| mbed_official | 390:35c2c1cf29cd | 615 | #define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3 |
| mbed_official | 390:35c2c1cf29cd | 616 | #define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3 |
| mbed_official | 390:35c2c1cf29cd | 617 | #define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3 |
| mbed_official | 390:35c2c1cf29cd | 618 | #define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3 |
| mbed_official | 390:35c2c1cf29cd | 619 | #define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 620 | #define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 621 | #define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 622 | #define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 623 | #define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 624 | #define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 625 | #define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 626 | #define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 627 | #define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 628 | #define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 629 | #define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 630 | #define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 631 | #define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 632 | #define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 633 | #define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 634 | #define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 635 | #define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 636 | #define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 637 | #define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 638 | #define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 639 | #define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 640 | #define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 641 | #define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 642 | #define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 643 | #define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0 |
| mbed_official | 390:35c2c1cf29cd | 644 | #define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 645 | #define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 646 | #define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 647 | #define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 648 | #define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 649 | #define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 650 | #define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 651 | #define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 652 | #define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 653 | #define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 654 | #define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 655 | #define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 656 | #define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 657 | #define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 658 | #define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 659 | #define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 660 | #define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 661 | #define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 662 | #define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 663 | #define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 664 | #define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 665 | #define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 666 | #define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 667 | #define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 668 | #define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1 |
| mbed_official | 390:35c2c1cf29cd | 669 | #define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 670 | #define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 671 | #define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 672 | #define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 673 | #define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 674 | #define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 675 | #define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 676 | #define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 677 | #define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 678 | #define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 679 | #define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 680 | #define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 681 | #define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 682 | #define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 683 | #define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 684 | #define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 685 | #define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 686 | #define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 687 | #define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 688 | #define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 689 | #define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0 |
| mbed_official | 390:35c2c1cf29cd | 690 | #define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 691 | #define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 692 | #define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 693 | #define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 694 | #define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 695 | #define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 696 | #define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 697 | #define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 698 | #define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 699 | #define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 700 | #define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 701 | #define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 702 | #define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 703 | #define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 704 | #define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 705 | #define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 706 | #define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 707 | #define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 708 | #define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 709 | #define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 710 | #define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1 |
| mbed_official | 390:35c2c1cf29cd | 711 | #define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 712 | #define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 713 | #define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 714 | #define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 715 | #define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 716 | #define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 717 | #define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 718 | #define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 719 | #define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 720 | #define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 721 | #define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 722 | #define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 723 | #define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 724 | #define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 725 | #define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 726 | #define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 727 | #define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 728 | #define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 729 | #define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 730 | #define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 731 | #define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2 |
| mbed_official | 390:35c2c1cf29cd | 732 | #define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 733 | #define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 734 | #define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 735 | #define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 736 | #define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 737 | #define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 738 | #define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 739 | #define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 740 | #define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 741 | #define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 742 | #define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 743 | #define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 744 | #define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 745 | #define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 746 | #define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 747 | #define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 748 | #define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 749 | #define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 750 | #define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 751 | #define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 752 | #define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3 |
| mbed_official | 390:35c2c1cf29cd | 753 | #define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 754 | #define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 755 | #define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 756 | #define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 757 | #define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 758 | #define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 759 | #define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 760 | #define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 761 | #define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 762 | #define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 763 | #define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0 |
| mbed_official | 390:35c2c1cf29cd | 764 | #define SCUXSWRSR_CIM SCUX.SWRSR_CIM |
| mbed_official | 390:35c2c1cf29cd | 765 | #define SCUXDMACR_CIM SCUX.DMACR_CIM |
| mbed_official | 390:35c2c1cf29cd | 766 | #define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32 |
| mbed_official | 390:35c2c1cf29cd | 767 | #define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L] |
| mbed_official | 390:35c2c1cf29cd | 768 | #define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H] |
| mbed_official | 390:35c2c1cf29cd | 769 | #define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32 |
| mbed_official | 390:35c2c1cf29cd | 770 | #define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L] |
| mbed_official | 390:35c2c1cf29cd | 771 | #define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H] |
| mbed_official | 390:35c2c1cf29cd | 772 | #define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32 |
| mbed_official | 390:35c2c1cf29cd | 773 | #define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L] |
| mbed_official | 390:35c2c1cf29cd | 774 | #define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H] |
| mbed_official | 390:35c2c1cf29cd | 775 | #define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32 |
| mbed_official | 390:35c2c1cf29cd | 776 | #define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L] |
| mbed_official | 390:35c2c1cf29cd | 777 | #define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H] |
| mbed_official | 390:35c2c1cf29cd | 778 | #define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32 |
| mbed_official | 390:35c2c1cf29cd | 779 | #define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L] |
| mbed_official | 390:35c2c1cf29cd | 780 | #define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H] |
| mbed_official | 390:35c2c1cf29cd | 781 | #define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32 |
| mbed_official | 390:35c2c1cf29cd | 782 | #define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L] |
| mbed_official | 390:35c2c1cf29cd | 783 | #define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H] |
| mbed_official | 390:35c2c1cf29cd | 784 | #define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32 |
| mbed_official | 390:35c2c1cf29cd | 785 | #define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L] |
| mbed_official | 390:35c2c1cf29cd | 786 | #define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H] |
| mbed_official | 390:35c2c1cf29cd | 787 | #define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32 |
| mbed_official | 390:35c2c1cf29cd | 788 | #define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L] |
| mbed_official | 390:35c2c1cf29cd | 789 | #define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H] |
| mbed_official | 390:35c2c1cf29cd | 790 | #define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM |
| mbed_official | 390:35c2c1cf29cd | 791 | #define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM |
| mbed_official | 390:35c2c1cf29cd | 792 | #define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM |
| mbed_official | 390:35c2c1cf29cd | 793 | #define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM |
| mbed_official | 390:35c2c1cf29cd | 794 | #define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM |
| mbed_official | 390:35c2c1cf29cd | 795 | #define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM |
| mbed_official | 390:35c2c1cf29cd | 796 | #define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM |
| mbed_official | 390:35c2c1cf29cd | 797 | #define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM |
| mbed_official | 390:35c2c1cf29cd | 798 | #define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM |
| mbed_official | 390:35c2c1cf29cd | 799 | #define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM |
| mbed_official | 390:35c2c1cf29cd | 800 | #define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM |
| mbed_official | 390:35c2c1cf29cd | 801 | #define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM |
| mbed_official | 390:35c2c1cf29cd | 802 | #define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM |
| mbed_official | 390:35c2c1cf29cd | 803 | #define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM |
| mbed_official | 390:35c2c1cf29cd | 804 | #define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM |
| mbed_official | 390:35c2c1cf29cd | 805 | #define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM |
| mbed_official | 390:35c2c1cf29cd | 806 | /* <-SEC M1.10.1 */ |
| mbed_official | 390:35c2c1cf29cd | 807 | /* <-QAC 0639 */ |
| mbed_official | 390:35c2c1cf29cd | 808 | #endif |