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Dependencies: DS1307 MAX17048 MODSERIAL SSD1308_128x64_I2C mbed-rpc mbed
Fork of ECGAFE_copy by
ADS1298.cpp
00001 #include "ADS1298.h" 00002 00003 00004 ADS1298::ADS1298(PinName mosi, 00005 PinName miso, 00006 PinName sck, 00007 PinName csn, 00008 PinName reset, 00009 PinName drdy, 00010 PinName start) : spi_(mosi, miso, sck), cs_(csn), reset_(reset), drdy_(drdy), start_(start) { 00011 } 00012 00013 void ADS1298::sendCommand(uint8_t cmd) 00014 { 00015 // Select the device by seting chip select low 00016 cs_ = 0; 00017 wait_us(TCSSC); 00018 00019 // Send SDATAC, as device comes up in RDATAC 00020 spi_.write(cmd); 00021 wait_us(TCMD); 00022 00023 // Deselect the device 00024 wait_us(TSCCS); 00025 cs_ = 1; 00026 // Wait between commands 00027 wait_us(TCSH); 00028 } 00029 00030 void ADS1298::writeRegister(uint8_t reg, uint8_t val) 00031 { 00032 // Select the device by seting chip select low 00033 cs_ = 0; 00034 wait_us(TCSSC); 00035 00036 // Write register address 00037 spi_.write(WREG|reg); 00038 wait_us(TCMD); 00039 00040 // Writing one register 00041 spi_.write(0x00); 00042 wait_us(TCMD); 00043 00044 // Write the value 00045 spi_.write(val); 00046 wait_us(TCMD); 00047 00048 // Deselect the device 00049 wait_us(TSCCS); 00050 cs_ = 1; 00051 00052 // Wait between commands 00053 wait_us(TCSH); 00054 } 00055 00056 uint8_t ADS1298::readRegister(uint8_t reg) 00057 { 00058 uint8_t res; 00059 // Select the device by seting chip select low 00060 cs_ = 0; 00061 wait_us(TCSSC); 00062 00063 // Write register address 00064 spi_.write(RREG|reg); 00065 wait_us(TCMD); 00066 00067 // Reading one register 00068 spi_.write(0x00); 00069 wait_us(TCMD); 00070 00071 // Write a dummy value to read the register 00072 res = spi_.write(0x00); 00073 wait_us(TCMD); 00074 00075 // Deselect the device 00076 wait_us(TSCCS); 00077 cs_ = 1; 00078 00079 // Wait between commands 00080 wait_us(TCSH); 00081 return res; 00082 } 00083 00084 void ADS1298::readData(uint8_t *data) 00085 { 00086 // Select the device by seting chip select low 00087 cs_ = 0; 00088 wait_us(TCSSC); 00089 00090 for (int i=0; i<27; i++) { 00091 // Write a dummy value to read the register 00092 *(data+i) = spi_.write(0x00); 00093 } 00094 wait_us(TCMD); 00095 00096 // Deselect the device 00097 wait_us(TSCCS); 00098 cs_ = 1; 00099 00100 // Wait between commands 00101 wait_us(TCSH); 00102 } 00103 00104 void ADS1298::initialize(void (*dataReady)(void)) 00105 { 00106 // Initialize signals 00107 cs_ = 1; 00108 start_ = 0; 00109 reset_ = 1; 00110 drdy_.fall(dataReady); 00111 00112 // Set up SPI 00113 spi_.format(8,1); 00114 // Choosing 1MHz arbitrarily for now 00115 spi_.frequency(1000000); 00116 00117 00118 // Power on reset 00119 wait_us(TPOR); 00120 00121 // Reset the device 00122 reset_ = 0; 00123 wait_us(TRST); 00124 reset_ = 1; 00125 wait_us(TRST2); 00126 00127 // Send SDATAC, as device comes up in RDATAC 00128 sendCommand(SDATAC); 00129 00130 //pc.printf("ID = 0x%02X\r\n", readRegister(ID)); 00131 //pc.printf("CONFIG1 = 0x%02X\r\n", readRegister(CONFIG1)); 00132 //pc.printf("CONFIG2 = 0x%02X\r\n", readRegister(CONFIG2)); 00133 //pc.printf("CONFIG3 = 0x%02X\r\n", readRegister(CONFIG3)); 00134 00135 // Turn on internal reference and wait for it to settle 00136 writeRegister(CONFIG3, CONFIG3_DEFAULT | CONFIG3_PD_REFBUF); 00137 wait_us(TINTREF); 00138 //pc.printf("CONFIG3 = 0x%02X\r\n", readRegister(CONFIG3)); 00139 00140 /* 00141 // Set up device 00142 writeRegister(CONFIG1, CONFIG1_HR | CONFIG1_DR2 | CONFIG1_DR1); 00143 pc.printf("CONFIG1 = 0x%02X\r\n", readRegister(CONFIG1)); 00144 writeRegister(CONFIG2, CONFIG2_DEFAULT); 00145 pc.printf("CONFIG2 = 0x%02X\r\n", readRegister(CONFIG2)); 00146 00147 // Input short on all channels 00148 writeRegister(CH1SET, CHNSET_MUXN0); 00149 writeRegister(CH2SET, CHNSET_MUXN0); 00150 writeRegister(CH3SET, CHNSET_MUXN0); 00151 writeRegister(CH4SET, CHNSET_MUXN0); 00152 writeRegister(CH5SET, CHNSET_MUXN0); 00153 writeRegister(CH6SET, CHNSET_MUXN0); 00154 writeRegister(CH7SET, CHNSET_MUXN0); 00155 writeRegister(CH8SET, CHNSET_MUXN0); 00156 pc.printf("CH1SET = 0x%02X\r\n", readRegister(CH1SET)); 00157 pc.printf("CH2SET = 0x%02X\r\n", readRegister(CH2SET)); 00158 pc.printf("CH3SET = 0x%02X\r\n", readRegister(CH3SET)); 00159 pc.printf("CH4SET = 0x%02X\r\n", readRegister(CH4SET)); 00160 pc.printf("CH5SET = 0x%02X\r\n", readRegister(CH5SET)); 00161 pc.printf("CH6SET = 0x%02X\r\n", readRegister(CH6SET)); 00162 pc.printf("CH7SET = 0x%02X\r\n", readRegister(CH7SET)); 00163 pc.printf("CH8SET = 0x%02X\r\n", readRegister(CH8SET)); 00164 */ 00165 00166 /* 00167 // Set up device 00168 writeRegister(CONFIG1, CONFIG1_HR | CONFIG1_DR2 | CONFIG1_DR1); 00169 writeRegister(CONFIG2, CONFIG2_DEFAULT | CONFIG2_INTTEST); 00170 00171 // Input test on all channels 00172 writeRegister(CH1SET, CHNSET_MUXN2 | CHNSET_MUXN0); 00173 writeRegister(CH2SET, CHNSET_MUXN2 | CHNSET_MUXN0); 00174 writeRegister(CH3SET, CHNSET_MUXN2 | CHNSET_MUXN0); 00175 writeRegister(CH4SET, CHNSET_MUXN2 | CHNSET_MUXN0); 00176 writeRegister(CH5SET, CHNSET_MUXN2 | CHNSET_MUXN0); 00177 writeRegister(CH6SET, CHNSET_MUXN2 | CHNSET_MUXN0); 00178 writeRegister(CH7SET, CHNSET_MUXN2 | CHNSET_MUXN0); 00179 writeRegister(CH8SET, CHNSET_MUXN2 | CHNSET_MUXN0); 00180 */ 00181 00182 // Set up device 00183 writeRegister(CONFIG1, CONFIG1_HR | CONFIG1_DR2 | CONFIG1_DR1); 00184 writeRegister(CONFIG2, CONFIG2_DEFAULT); 00185 writeRegister(CONFIG3, CONFIG3_DEFAULT | CONFIG3_PD_REFBUF | 00186 CONFIG3_RLDREF_INT | CONFIG3_PD_RLD); 00187 writeRegister(CONFIG4, CONFIG4_PD_LOFF_COMP); 00188 writeRegister(LOFF, LOFF_VLEAD_OFF_EN | LOFF_FLEAD_OFF1 | LOFF_FLEAD_OFF0); 00189 writeRegister(LOFF_SENSP, 0xFF); // for V6, LA, LL, V2, V3, V4, V5, V1 00190 writeRegister(LOFF_SENSN, 0x02); // for RA only 00191 writeRegister(RLD_SENSP, 0x06); // for LA, LL 00192 writeRegister(RLD_SENSN, 0x02); // for RA 00193 writeRegister(WCT1, WCT1_PD_WCTA | WCT1_WCTA1); // WCTA to CH2P = LA 00194 writeRegister(WCT2, WCT2_PD_WCTC | WCT2_PD_WCTB | 00195 WCT2_WCTB2 | WCT2_WCTC1 | 00196 WCT2_WCTC0); // WCTB to CH3P = LL, WCTC to CH2N = RA 00197 00198 // Input test on all channels 00199 writeRegister(CH1SET, CHNSET_DEFAULT); 00200 writeRegister(CH2SET, CHNSET_DEFAULT); 00201 writeRegister(CH3SET, CHNSET_DEFAULT); 00202 writeRegister(CH4SET, CHNSET_DEFAULT); 00203 writeRegister(CH5SET, CHNSET_DEFAULT); 00204 writeRegister(CH6SET, CHNSET_DEFAULT); 00205 writeRegister(CH7SET, CHNSET_DEFAULT); 00206 writeRegister(CH8SET, CHNSET_DEFAULT); 00207 00208 } 00209 00210 void ADS1298::startCapture() { 00211 //Start conversion 00212 start_ = 1; 00213 00214 // Send RDATAC to start data collection 00215 sendCommand(RDATAC); 00216 } 00217 00218 void ADS1298::stopCapture() { 00219 //Stop conversion 00220 start_ = 0; 00221 00222 // Send SDATAC to stop data collection 00223 sendCommand(SDATAC); 00224 } 00225 00226 int ADS1298::updateLeadOff(uint8_t *buf) { 00227 00228 // Buffer contains 9 fields of 24 bits each 00229 // First field contains an identifier and the status bits 00230 // First nibble of first byte is always 0b1100 00231 // Second nibble of third byte is always 0x00 because GPIO are not used 00232 if ((buf[0] & 0xf0) != 0xc0 || (buf[2] & 0x0f) != 0x00) 00233 return -1; 00234 00235 // Second nibble of first byte has IN8P_OFF (V1), IN7P_OFF (V5), IN6P_OFF (V4), IN5P_OFF (V3) 00236 lOff_ = 0; 00237 lOff_ |= (buf[0] & 0x08) ? (1 << LOFFV1) : 0; 00238 lOff_ |= (buf[0] & 0x04) ? (1 << LOFFV5) : 0; 00239 lOff_ |= (buf[0] & 0x02) ? (1 << LOFFV4) : 0; 00240 lOff_ |= (buf[0] & 0x01) ? (1 << LOFFV3) : 0; 00241 // First nibble of second byte has IN4P_OFF (V2), IN3P_OFF (LL), IN2P_OFF (LA), IN1P_OFF (V6) 00242 lOff_ |= (buf[1] & 0x80) ? (1 << LOFFV2) : 0; 00243 lOff_ |= (buf[1] & 0x40) ? (1 << LOFFLL) : 0; 00244 lOff_ |= (buf[1] & 0x20) ? (1 << LOFFLA) : 0; 00245 lOff_ |= (buf[1] & 0x10) ? (1 << LOFFV6) : 0; 00246 // First nibble of third byte has IN2N_OFF (RA) 00247 lOff_ |= (buf[2] & 0x20) ? (1 << LOFFRA) : 0; 00248 00249 return 0; 00250 }
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