Priliminary
Dependencies: DS1307 MAX17048 MODSERIAL SSD1308_128x64_I2C WatchDog mbed-rpc mbed
Fork of ECGAFE_copy by
ADS1298.h@0:ee0649a9025a, 2015-09-30 (annotated)
- Committer:
- zainulcharbiwala
- Date:
- Wed Sep 30 11:30:56 2015 +0000
- Revision:
- 0:ee0649a9025a
Priliminary
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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zainulcharbiwala | 0:ee0649a9025a | 1 | // Copyright 2013, Zainul Charbiwala |
zainulcharbiwala | 0:ee0649a9025a | 2 | |
zainulcharbiwala | 0:ee0649a9025a | 3 | #ifndef _ADS1298_h_ |
zainulcharbiwala | 0:ee0649a9025a | 4 | #define _ADS1298_h_ |
zainulcharbiwala | 0:ee0649a9025a | 5 | |
zainulcharbiwala | 0:ee0649a9025a | 6 | #include "mbed.h" |
zainulcharbiwala | 0:ee0649a9025a | 7 | |
zainulcharbiwala | 0:ee0649a9025a | 8 | #define TCSSC 1 // 6 ns |
zainulcharbiwala | 0:ee0649a9025a | 9 | #define TSCCS 2 // 4 TCLKs |
zainulcharbiwala | 0:ee0649a9025a | 10 | #define TPOR 32768 // 2^16 TCLKs |
zainulcharbiwala | 0:ee0649a9025a | 11 | #define TRST 1 // 2 TCLKs |
zainulcharbiwala | 0:ee0649a9025a | 12 | #define TRST2 9 // 18 TCLKs |
zainulcharbiwala | 0:ee0649a9025a | 13 | #define TINTREF 150000 // 150ms |
zainulcharbiwala | 0:ee0649a9025a | 14 | #define TCMD 2 // 4 TCLKs |
zainulcharbiwala | 0:ee0649a9025a | 15 | #define TCSH 1 // 2 TCLKs |
zainulcharbiwala | 0:ee0649a9025a | 16 | |
zainulcharbiwala | 0:ee0649a9025a | 17 | #define RDATA 0x12 |
zainulcharbiwala | 0:ee0649a9025a | 18 | #define RDATAC 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 19 | #define SDATAC 0x11 |
zainulcharbiwala | 0:ee0649a9025a | 20 | #define WREG 0x40 |
zainulcharbiwala | 0:ee0649a9025a | 21 | #define RREG 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 22 | |
zainulcharbiwala | 0:ee0649a9025a | 23 | #define ID 0x00 |
zainulcharbiwala | 0:ee0649a9025a | 24 | #define CONFIG1 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 25 | #define CONFIG2 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 26 | #define CONFIG3 0x03 |
zainulcharbiwala | 0:ee0649a9025a | 27 | #define LOFF 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 28 | #define CH1SET 0x05 |
zainulcharbiwala | 0:ee0649a9025a | 29 | #define CH2SET 0x06 |
zainulcharbiwala | 0:ee0649a9025a | 30 | #define CH3SET 0x07 |
zainulcharbiwala | 0:ee0649a9025a | 31 | #define CH4SET 0x08 |
zainulcharbiwala | 0:ee0649a9025a | 32 | #define CH5SET 0x09 |
zainulcharbiwala | 0:ee0649a9025a | 33 | #define CH6SET 0x0A |
zainulcharbiwala | 0:ee0649a9025a | 34 | #define CH7SET 0x0B |
zainulcharbiwala | 0:ee0649a9025a | 35 | #define CH8SET 0x0C |
zainulcharbiwala | 0:ee0649a9025a | 36 | #define RLD_SENSP 0x0D |
zainulcharbiwala | 0:ee0649a9025a | 37 | #define RLD_SENSN 0x0E |
zainulcharbiwala | 0:ee0649a9025a | 38 | #define LOFF_SENSP 0x0F |
zainulcharbiwala | 0:ee0649a9025a | 39 | #define LOFF_SENSN 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 40 | #define LOFF_FLIP 0x11 |
zainulcharbiwala | 0:ee0649a9025a | 41 | #define LOFF_STATP 0x12 |
zainulcharbiwala | 0:ee0649a9025a | 42 | #define LOFF_STATN 0x13 |
zainulcharbiwala | 0:ee0649a9025a | 43 | #define GPIO 0x14 |
zainulcharbiwala | 0:ee0649a9025a | 44 | #define PACE 0x15 |
zainulcharbiwala | 0:ee0649a9025a | 45 | #define RESP 0x16 |
zainulcharbiwala | 0:ee0649a9025a | 46 | #define CONFIG4 0x17 |
zainulcharbiwala | 0:ee0649a9025a | 47 | #define WCT1 0x18 |
zainulcharbiwala | 0:ee0649a9025a | 48 | #define WCT2 0x19 |
zainulcharbiwala | 0:ee0649a9025a | 49 | |
zainulcharbiwala | 0:ee0649a9025a | 50 | |
zainulcharbiwala | 0:ee0649a9025a | 51 | #define CONFIG1_HR 0x80 |
zainulcharbiwala | 0:ee0649a9025a | 52 | #define CONFIG1_DAISYEN 0x40 |
zainulcharbiwala | 0:ee0649a9025a | 53 | #define CONFIG1_CLKEN 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 54 | #define CONFIG1_DR2 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 55 | #define CONFIG1_DR1 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 56 | #define CONFIG1_DR0 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 57 | |
zainulcharbiwala | 0:ee0649a9025a | 58 | #define CONFIG2_WCTCHOP 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 59 | #define CONFIG2_INTTEST 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 60 | #define CONFIG2_TESTAMP 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 61 | #define CONFIG2_TESTFREQ1 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 62 | #define CONFIG2_TESTFREQ0 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 63 | #define CONFIG2_DEFAULT 0x00 |
zainulcharbiwala | 0:ee0649a9025a | 64 | |
zainulcharbiwala | 0:ee0649a9025a | 65 | #define CONFIG3_PD_REFBUF 0x80 |
zainulcharbiwala | 0:ee0649a9025a | 66 | #define CONFIG3_VREF_4V 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 67 | #define CONFIG3_RLD_MEAS 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 68 | #define CONFIG3_RLDREF_INT 0x08 |
zainulcharbiwala | 0:ee0649a9025a | 69 | #define CONFIG3_PD_RLD 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 70 | #define CONFIG3_RLD_LOFF_SENS 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 71 | #define CONFIG3_RLD_STAT 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 72 | #define CONFIG3_DEFAULT 0x40 |
zainulcharbiwala | 0:ee0649a9025a | 73 | |
zainulcharbiwala | 0:ee0649a9025a | 74 | #define LOFF_COMP_TH2 0x80 |
zainulcharbiwala | 0:ee0649a9025a | 75 | #define LOFF_COMP_TH1 0x40 |
zainulcharbiwala | 0:ee0649a9025a | 76 | #define LOFF_COMP_TH0 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 77 | #define LOFF_VLEAD_OFF_EN 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 78 | #define LOFF_ILEAD_OFF1 0x08 |
zainulcharbiwala | 0:ee0649a9025a | 79 | #define LOFF_ILEAD_OFF0 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 80 | #define LOFF_FLEAD_OFF1 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 81 | #define LOFF_FLEAD_OFF0 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 82 | |
zainulcharbiwala | 0:ee0649a9025a | 83 | #define CHNSET_PD 0x80 |
zainulcharbiwala | 0:ee0649a9025a | 84 | #define CHNSET_GAIN2 0x40 |
zainulcharbiwala | 0:ee0649a9025a | 85 | #define CHNSET_GAIN1 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 86 | #define CHNSET_GAIN0 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 87 | #define CHNSET_MUXN2 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 88 | #define CHNSET_MUXN1 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 89 | #define CHNSET_MUXN0 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 90 | #define CHNSET_DEFAULT 0x00 |
zainulcharbiwala | 0:ee0649a9025a | 91 | |
zainulcharbiwala | 0:ee0649a9025a | 92 | #define GPIO_GPIOD4 0x80 |
zainulcharbiwala | 0:ee0649a9025a | 93 | #define GPIO_GPIOD3 0x40 |
zainulcharbiwala | 0:ee0649a9025a | 94 | #define GPIO_GPIOD2 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 95 | #define GPIO_GPIOD1 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 96 | #define GPIO_GPIOC4 0x08 |
zainulcharbiwala | 0:ee0649a9025a | 97 | #define GPIO_GPIOC3 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 98 | #define GPIO_GPIOC2 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 99 | #define GPIO_GPIOC1 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 100 | |
zainulcharbiwala | 0:ee0649a9025a | 101 | #define PACE_PACEE1 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 102 | #define PACE_PACEE0 0x08 |
zainulcharbiwala | 0:ee0649a9025a | 103 | #define PACE_PACEO1 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 104 | #define PACE_PACEO0 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 105 | #define PACE_PD_PACE 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 106 | |
zainulcharbiwala | 0:ee0649a9025a | 107 | #define RESP_DEMOD_EN1 0x80 |
zainulcharbiwala | 0:ee0649a9025a | 108 | #define RESP_MOD_EN1 0x40 |
zainulcharbiwala | 0:ee0649a9025a | 109 | #define RESP_DEFAULT 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 110 | #define RESP_PH2 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 111 | #define RESP_PH1 0x08 |
zainulcharbiwala | 0:ee0649a9025a | 112 | #define RESP_PH0 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 113 | #define RESP_CTRL1 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 114 | #define RESP_CTRL0 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 115 | |
zainulcharbiwala | 0:ee0649a9025a | 116 | #define CONFIG4_RESP_FREQ2 0x80 |
zainulcharbiwala | 0:ee0649a9025a | 117 | #define CONFIG4_RESP_FREQ1 0x40 |
zainulcharbiwala | 0:ee0649a9025a | 118 | #define CONFIG4_RESP_FREQ0 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 119 | #define CONFIG4_SINGLE_SHOT 0x08 |
zainulcharbiwala | 0:ee0649a9025a | 120 | #define CONFIG4_WCT_TO_RLD 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 121 | #define CONFIG4_PD_LOFF_COMP 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 122 | |
zainulcharbiwala | 0:ee0649a9025a | 123 | #define WCT1_AVF_CH6 0x80 |
zainulcharbiwala | 0:ee0649a9025a | 124 | #define WCT1_AVL_CH5 0x40 |
zainulcharbiwala | 0:ee0649a9025a | 125 | #define WCT1_AVR_CH7 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 126 | #define WCT1_AVR_CH4 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 127 | #define WCT1_PD_WCTA 0x08 |
zainulcharbiwala | 0:ee0649a9025a | 128 | #define WCT1_WCTA2 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 129 | #define WCT1_WCTA1 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 130 | #define WCT1_WCTA0 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 131 | |
zainulcharbiwala | 0:ee0649a9025a | 132 | #define WCT2_PD_WCTC 0x80 |
zainulcharbiwala | 0:ee0649a9025a | 133 | #define WCT2_PD_WCTB 0x40 |
zainulcharbiwala | 0:ee0649a9025a | 134 | #define WCT2_WCTB2 0x20 |
zainulcharbiwala | 0:ee0649a9025a | 135 | #define WCT2_WCTB1 0x10 |
zainulcharbiwala | 0:ee0649a9025a | 136 | #define WCT2_WCTB0 0x08 |
zainulcharbiwala | 0:ee0649a9025a | 137 | #define WCT2_WCTC2 0x04 |
zainulcharbiwala | 0:ee0649a9025a | 138 | #define WCT2_WCTC1 0x02 |
zainulcharbiwala | 0:ee0649a9025a | 139 | #define WCT2_WCTC0 0x01 |
zainulcharbiwala | 0:ee0649a9025a | 140 | |
zainulcharbiwala | 0:ee0649a9025a | 141 | // Bit positions of the lead off status bits |
zainulcharbiwala | 0:ee0649a9025a | 142 | #define LOFFRA 15 |
zainulcharbiwala | 0:ee0649a9025a | 143 | #define LOFFLA 14 |
zainulcharbiwala | 0:ee0649a9025a | 144 | #define LOFFLL 13 |
zainulcharbiwala | 0:ee0649a9025a | 145 | #define LOFFRL 12 |
zainulcharbiwala | 0:ee0649a9025a | 146 | #define LOFFV1 11 |
zainulcharbiwala | 0:ee0649a9025a | 147 | #define LOFFV2 10 |
zainulcharbiwala | 0:ee0649a9025a | 148 | #define LOFFV3 9 |
zainulcharbiwala | 0:ee0649a9025a | 149 | #define LOFFV4 8 |
zainulcharbiwala | 0:ee0649a9025a | 150 | #define LOFFV5 7 |
zainulcharbiwala | 0:ee0649a9025a | 151 | #define LOFFV6 6 |
zainulcharbiwala | 0:ee0649a9025a | 152 | |
zainulcharbiwala | 0:ee0649a9025a | 153 | /** Class to control an ADS1298 AFE |
zainulcharbiwala | 0:ee0649a9025a | 154 | * |
zainulcharbiwala | 0:ee0649a9025a | 155 | * Example: |
zainulcharbiwala | 0:ee0649a9025a | 156 | * @code |
zainulcharbiwala | 0:ee0649a9025a | 157 | * |
zainulcharbiwala | 0:ee0649a9025a | 158 | * @endcode |
zainulcharbiwala | 0:ee0649a9025a | 159 | */ |
zainulcharbiwala | 0:ee0649a9025a | 160 | class ADS1298 { |
zainulcharbiwala | 0:ee0649a9025a | 161 | public: |
zainulcharbiwala | 0:ee0649a9025a | 162 | |
zainulcharbiwala | 0:ee0649a9025a | 163 | /** |
zainulcharbiwala | 0:ee0649a9025a | 164 | * @brief Constructor |
zainulcharbiwala | 0:ee0649a9025a | 165 | * @param mosi mbed pin to use for MOSI line of SPI interface. |
zainulcharbiwala | 0:ee0649a9025a | 166 | * @param miso mbed pin to use for MISO line of SPI interface. |
zainulcharbiwala | 0:ee0649a9025a | 167 | * @param sck mbed pin to use for SCK line of SPI interface. |
zainulcharbiwala | 0:ee0649a9025a | 168 | * @param csn mbed pin to use for not chip select line of SPI interface. |
zainulcharbiwala | 0:ee0649a9025a | 169 | * @param reset mbed pin to use for the reset line. |
zainulcharbiwala | 0:ee0649a9025a | 170 | * @param drdy mbed pin to use for the data ready line. |
zainulcharbiwala | 0:ee0649a9025a | 171 | * @param start mbed pin to use for the start conversion line. |
zainulcharbiwala | 0:ee0649a9025a | 172 | */ |
zainulcharbiwala | 0:ee0649a9025a | 173 | ADS1298(PinName mosi, PinName miso, PinName sck, PinName csn, PinName reset, PinName drdy, PinName start); |
zainulcharbiwala | 0:ee0649a9025a | 174 | |
zainulcharbiwala | 0:ee0649a9025a | 175 | |
zainulcharbiwala | 0:ee0649a9025a | 176 | // High Level methods |
zainulcharbiwala | 0:ee0649a9025a | 177 | |
zainulcharbiwala | 0:ee0649a9025a | 178 | /** |
zainulcharbiwala | 0:ee0649a9025a | 179 | * @brief High level Init, most settings remain at Power-On reset value |
zainulcharbiwala | 0:ee0649a9025a | 180 | */ |
zainulcharbiwala | 0:ee0649a9025a | 181 | void initialize(void (*dataready)(void)); |
zainulcharbiwala | 0:ee0649a9025a | 182 | |
zainulcharbiwala | 0:ee0649a9025a | 183 | /** |
zainulcharbiwala | 0:ee0649a9025a | 184 | * @brief Start capturing data |
zainulcharbiwala | 0:ee0649a9025a | 185 | */ |
zainulcharbiwala | 0:ee0649a9025a | 186 | void startCapture(); |
zainulcharbiwala | 0:ee0649a9025a | 187 | |
zainulcharbiwala | 0:ee0649a9025a | 188 | /** |
zainulcharbiwala | 0:ee0649a9025a | 189 | * @brief Stop capturing data |
zainulcharbiwala | 0:ee0649a9025a | 190 | */ |
zainulcharbiwala | 0:ee0649a9025a | 191 | void stopCapture(); |
zainulcharbiwala | 0:ee0649a9025a | 192 | |
zainulcharbiwala | 0:ee0649a9025a | 193 | /** |
zainulcharbiwala | 0:ee0649a9025a | 194 | * @brief Read data from the ADS1298 |
zainulcharbiwala | 0:ee0649a9025a | 195 | */ |
zainulcharbiwala | 0:ee0649a9025a | 196 | void readData(uint8_t *buf); |
zainulcharbiwala | 0:ee0649a9025a | 197 | |
zainulcharbiwala | 0:ee0649a9025a | 198 | /** |
zainulcharbiwala | 0:ee0649a9025a | 199 | * @brief Update the lead off status |
zainulcharbiwala | 0:ee0649a9025a | 200 | */ |
zainulcharbiwala | 0:ee0649a9025a | 201 | int updateLeadOff(uint8_t *buf); |
zainulcharbiwala | 0:ee0649a9025a | 202 | |
zainulcharbiwala | 0:ee0649a9025a | 203 | private: |
zainulcharbiwala | 0:ee0649a9025a | 204 | |
zainulcharbiwala | 0:ee0649a9025a | 205 | SPI spi_; // mosi, miso, sclk |
zainulcharbiwala | 0:ee0649a9025a | 206 | DigitalOut cs_; |
zainulcharbiwala | 0:ee0649a9025a | 207 | DigitalOut reset_; |
zainulcharbiwala | 0:ee0649a9025a | 208 | InterruptIn drdy_; |
zainulcharbiwala | 0:ee0649a9025a | 209 | DigitalOut start_; |
zainulcharbiwala | 0:ee0649a9025a | 210 | uint16_t lOff_; |
zainulcharbiwala | 0:ee0649a9025a | 211 | |
zainulcharbiwala | 0:ee0649a9025a | 212 | // Low Level methods |
zainulcharbiwala | 0:ee0649a9025a | 213 | void sendCommand(uint8_t cmd); |
zainulcharbiwala | 0:ee0649a9025a | 214 | void writeRegister(uint8_t reg, uint8_t val); |
zainulcharbiwala | 0:ee0649a9025a | 215 | uint8_t readRegister(uint8_t reg); |
zainulcharbiwala | 0:ee0649a9025a | 216 | |
zainulcharbiwala | 0:ee0649a9025a | 217 | }; |
zainulcharbiwala | 0:ee0649a9025a | 218 | |
zainulcharbiwala | 0:ee0649a9025a | 219 | |
zainulcharbiwala | 0:ee0649a9025a | 220 | |
zainulcharbiwala | 0:ee0649a9025a | 221 | #endif |