zain aftab
/
mbed-src3
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_usart.h@526:c320967f86b9, 2015-04-28 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Apr 28 11:45:12 2015 +0100
- Revision:
- 526:c320967f86b9
Synchronized with git revision 299385b8331142b9dc524da7a986536f60b14553
Full URL: https://github.com/mbedmicro/mbed/commit/299385b8331142b9dc524da7a986536f60b14553/
Add in Silicon Labs targets with asynchronous API support
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 526:c320967f86b9 | 1 | /**************************************************************************//** |
| mbed_official | 526:c320967f86b9 | 2 | * @file efm32hg_usart.h |
| mbed_official | 526:c320967f86b9 | 3 | * @brief EFM32HG_USART register and bit field definitions |
| mbed_official | 526:c320967f86b9 | 4 | * @version 3.20.12 |
| mbed_official | 526:c320967f86b9 | 5 | ****************************************************************************** |
| mbed_official | 526:c320967f86b9 | 6 | * @section License |
| mbed_official | 526:c320967f86b9 | 7 | * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| mbed_official | 526:c320967f86b9 | 8 | ****************************************************************************** |
| mbed_official | 526:c320967f86b9 | 9 | * |
| mbed_official | 526:c320967f86b9 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| mbed_official | 526:c320967f86b9 | 11 | * including commercial applications, and to alter it and redistribute it |
| mbed_official | 526:c320967f86b9 | 12 | * freely, subject to the following restrictions: |
| mbed_official | 526:c320967f86b9 | 13 | * |
| mbed_official | 526:c320967f86b9 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| mbed_official | 526:c320967f86b9 | 15 | * claim that you wrote the original software.@n |
| mbed_official | 526:c320967f86b9 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| mbed_official | 526:c320967f86b9 | 17 | * misrepresented as being the original software.@n |
| mbed_official | 526:c320967f86b9 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| mbed_official | 526:c320967f86b9 | 19 | * |
| mbed_official | 526:c320967f86b9 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| mbed_official | 526:c320967f86b9 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| mbed_official | 526:c320967f86b9 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| mbed_official | 526:c320967f86b9 | 23 | * kind, including, but not limited to, any implied warranties of |
| mbed_official | 526:c320967f86b9 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| mbed_official | 526:c320967f86b9 | 25 | * infringement of any proprietary rights of a third party. |
| mbed_official | 526:c320967f86b9 | 26 | * |
| mbed_official | 526:c320967f86b9 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| mbed_official | 526:c320967f86b9 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| mbed_official | 526:c320967f86b9 | 29 | * any third party, arising from your use of this Software. |
| mbed_official | 526:c320967f86b9 | 30 | * |
| mbed_official | 526:c320967f86b9 | 31 | *****************************************************************************/ |
| mbed_official | 526:c320967f86b9 | 32 | /**************************************************************************//** |
| mbed_official | 526:c320967f86b9 | 33 | * @defgroup EFM32HG_USART |
| mbed_official | 526:c320967f86b9 | 34 | * @{ |
| mbed_official | 526:c320967f86b9 | 35 | * @brief EFM32HG_USART Register Declaration |
| mbed_official | 526:c320967f86b9 | 36 | *****************************************************************************/ |
| mbed_official | 526:c320967f86b9 | 37 | typedef struct |
| mbed_official | 526:c320967f86b9 | 38 | { |
| mbed_official | 526:c320967f86b9 | 39 | __IO uint32_t CTRL; /**< Control Register */ |
| mbed_official | 526:c320967f86b9 | 40 | __IO uint32_t FRAME; /**< USART Frame Format Register */ |
| mbed_official | 526:c320967f86b9 | 41 | __IO uint32_t TRIGCTRL; /**< USART Trigger Control register */ |
| mbed_official | 526:c320967f86b9 | 42 | __IO uint32_t CMD; /**< Command Register */ |
| mbed_official | 526:c320967f86b9 | 43 | __I uint32_t STATUS; /**< USART Status Register */ |
| mbed_official | 526:c320967f86b9 | 44 | __IO uint32_t CLKDIV; /**< Clock Control Register */ |
| mbed_official | 526:c320967f86b9 | 45 | __I uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ |
| mbed_official | 526:c320967f86b9 | 46 | __I uint32_t RXDATA; /**< RX Buffer Data Register */ |
| mbed_official | 526:c320967f86b9 | 47 | __I uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ |
| mbed_official | 526:c320967f86b9 | 48 | __I uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ |
| mbed_official | 526:c320967f86b9 | 49 | __I uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ |
| mbed_official | 526:c320967f86b9 | 50 | __I uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */ |
| mbed_official | 526:c320967f86b9 | 51 | __IO uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ |
| mbed_official | 526:c320967f86b9 | 52 | __IO uint32_t TXDATA; /**< TX Buffer Data Register */ |
| mbed_official | 526:c320967f86b9 | 53 | __IO uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ |
| mbed_official | 526:c320967f86b9 | 54 | __IO uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ |
| mbed_official | 526:c320967f86b9 | 55 | __I uint32_t IF; /**< Interrupt Flag Register */ |
| mbed_official | 526:c320967f86b9 | 56 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
| mbed_official | 526:c320967f86b9 | 57 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| mbed_official | 526:c320967f86b9 | 58 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
| mbed_official | 526:c320967f86b9 | 59 | __IO uint32_t IRCTRL; /**< IrDA Control Register */ |
| mbed_official | 526:c320967f86b9 | 60 | __IO uint32_t ROUTE; /**< I/O Routing Register */ |
| mbed_official | 526:c320967f86b9 | 61 | __IO uint32_t INPUT; /**< USART Input Register */ |
| mbed_official | 526:c320967f86b9 | 62 | __IO uint32_t I2SCTRL; /**< I2S Control Register */ |
| mbed_official | 526:c320967f86b9 | 63 | } USART_TypeDef; /** @} */ |
| mbed_official | 526:c320967f86b9 | 64 | |
| mbed_official | 526:c320967f86b9 | 65 | /**************************************************************************//** |
| mbed_official | 526:c320967f86b9 | 66 | * @defgroup EFM32HG_USART_BitFields |
| mbed_official | 526:c320967f86b9 | 67 | * @{ |
| mbed_official | 526:c320967f86b9 | 68 | *****************************************************************************/ |
| mbed_official | 526:c320967f86b9 | 69 | |
| mbed_official | 526:c320967f86b9 | 70 | /* Bit fields for USART CTRL */ |
| mbed_official | 526:c320967f86b9 | 71 | #define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 72 | #define _USART_CTRL_MASK 0xFFFFFF7FUL /**< Mask for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 73 | #define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ |
| mbed_official | 526:c320967f86b9 | 74 | #define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ |
| mbed_official | 526:c320967f86b9 | 75 | #define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ |
| mbed_official | 526:c320967f86b9 | 76 | #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 77 | #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 78 | #define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ |
| mbed_official | 526:c320967f86b9 | 79 | #define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ |
| mbed_official | 526:c320967f86b9 | 80 | #define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ |
| mbed_official | 526:c320967f86b9 | 81 | #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 82 | #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 83 | #define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ |
| mbed_official | 526:c320967f86b9 | 84 | #define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ |
| mbed_official | 526:c320967f86b9 | 85 | #define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ |
| mbed_official | 526:c320967f86b9 | 86 | #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 87 | #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 88 | #define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ |
| mbed_official | 526:c320967f86b9 | 89 | #define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ |
| mbed_official | 526:c320967f86b9 | 90 | #define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ |
| mbed_official | 526:c320967f86b9 | 91 | #define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 92 | #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 93 | #define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ |
| mbed_official | 526:c320967f86b9 | 94 | #define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ |
| mbed_official | 526:c320967f86b9 | 95 | #define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ |
| mbed_official | 526:c320967f86b9 | 96 | #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 97 | #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 98 | #define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ |
| mbed_official | 526:c320967f86b9 | 99 | #define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ |
| mbed_official | 526:c320967f86b9 | 100 | #define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 101 | #define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 102 | #define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 103 | #define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 104 | #define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 105 | #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 106 | #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 107 | #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 108 | #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 109 | #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 110 | #define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ |
| mbed_official | 526:c320967f86b9 | 111 | #define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ |
| mbed_official | 526:c320967f86b9 | 112 | #define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ |
| mbed_official | 526:c320967f86b9 | 113 | #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 114 | #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 115 | #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 116 | #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 117 | #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 118 | #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 119 | #define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ |
| mbed_official | 526:c320967f86b9 | 120 | #define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ |
| mbed_official | 526:c320967f86b9 | 121 | #define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ |
| mbed_official | 526:c320967f86b9 | 122 | #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 123 | #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 124 | #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 125 | #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 126 | #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 127 | #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 128 | #define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ |
| mbed_official | 526:c320967f86b9 | 129 | #define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ |
| mbed_official | 526:c320967f86b9 | 130 | #define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ |
| mbed_official | 526:c320967f86b9 | 131 | #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 132 | #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 133 | #define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */ |
| mbed_official | 526:c320967f86b9 | 134 | #define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ |
| mbed_official | 526:c320967f86b9 | 135 | #define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ |
| mbed_official | 526:c320967f86b9 | 136 | #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 137 | #define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 138 | #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 139 | #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 140 | #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 141 | #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 142 | #define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ |
| mbed_official | 526:c320967f86b9 | 143 | #define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ |
| mbed_official | 526:c320967f86b9 | 144 | #define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ |
| mbed_official | 526:c320967f86b9 | 145 | #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 146 | #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 147 | #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 148 | #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 149 | #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 150 | #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 151 | #define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ |
| mbed_official | 526:c320967f86b9 | 152 | #define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ |
| mbed_official | 526:c320967f86b9 | 153 | #define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ |
| mbed_official | 526:c320967f86b9 | 154 | #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 155 | #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 156 | #define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ |
| mbed_official | 526:c320967f86b9 | 157 | #define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ |
| mbed_official | 526:c320967f86b9 | 158 | #define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ |
| mbed_official | 526:c320967f86b9 | 159 | #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 160 | #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 161 | #define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ |
| mbed_official | 526:c320967f86b9 | 162 | #define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ |
| mbed_official | 526:c320967f86b9 | 163 | #define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ |
| mbed_official | 526:c320967f86b9 | 164 | #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 165 | #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 166 | #define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ |
| mbed_official | 526:c320967f86b9 | 167 | #define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ |
| mbed_official | 526:c320967f86b9 | 168 | #define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ |
| mbed_official | 526:c320967f86b9 | 169 | #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 170 | #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 171 | #define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ |
| mbed_official | 526:c320967f86b9 | 172 | #define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ |
| mbed_official | 526:c320967f86b9 | 173 | #define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ |
| mbed_official | 526:c320967f86b9 | 174 | #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 175 | #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 176 | #define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ |
| mbed_official | 526:c320967f86b9 | 177 | #define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ |
| mbed_official | 526:c320967f86b9 | 178 | #define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ |
| mbed_official | 526:c320967f86b9 | 179 | #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 180 | #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 181 | #define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ |
| mbed_official | 526:c320967f86b9 | 182 | #define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ |
| mbed_official | 526:c320967f86b9 | 183 | #define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ |
| mbed_official | 526:c320967f86b9 | 184 | #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 185 | #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 186 | #define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ |
| mbed_official | 526:c320967f86b9 | 187 | #define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ |
| mbed_official | 526:c320967f86b9 | 188 | #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ |
| mbed_official | 526:c320967f86b9 | 189 | #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 190 | #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 191 | #define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ |
| mbed_official | 526:c320967f86b9 | 192 | #define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ |
| mbed_official | 526:c320967f86b9 | 193 | #define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ |
| mbed_official | 526:c320967f86b9 | 194 | #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 195 | #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 196 | #define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ |
| mbed_official | 526:c320967f86b9 | 197 | #define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ |
| mbed_official | 526:c320967f86b9 | 198 | #define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ |
| mbed_official | 526:c320967f86b9 | 199 | #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 200 | #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 201 | #define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ |
| mbed_official | 526:c320967f86b9 | 202 | #define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ |
| mbed_official | 526:c320967f86b9 | 203 | #define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ |
| mbed_official | 526:c320967f86b9 | 204 | #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 205 | #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 206 | #define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ |
| mbed_official | 526:c320967f86b9 | 207 | #define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ |
| mbed_official | 526:c320967f86b9 | 208 | #define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ |
| mbed_official | 526:c320967f86b9 | 209 | #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 210 | #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 211 | #define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */ |
| mbed_official | 526:c320967f86b9 | 212 | #define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ |
| mbed_official | 526:c320967f86b9 | 213 | #define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ |
| mbed_official | 526:c320967f86b9 | 214 | #define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 215 | #define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 216 | #define _USART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */ |
| mbed_official | 526:c320967f86b9 | 217 | #define _USART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */ |
| mbed_official | 526:c320967f86b9 | 218 | #define _USART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 219 | #define _USART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 220 | #define _USART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 221 | #define _USART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 222 | #define _USART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 223 | #define USART_CTRL_TXDELAY_DEFAULT (_USART_CTRL_TXDELAY_DEFAULT << 26) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 224 | #define USART_CTRL_TXDELAY_NONE (_USART_CTRL_TXDELAY_NONE << 26) /**< Shifted mode NONE for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 225 | #define USART_CTRL_TXDELAY_SINGLE (_USART_CTRL_TXDELAY_SINGLE << 26) /**< Shifted mode SINGLE for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 226 | #define USART_CTRL_TXDELAY_DOUBLE (_USART_CTRL_TXDELAY_DOUBLE << 26) /**< Shifted mode DOUBLE for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 227 | #define USART_CTRL_TXDELAY_TRIPLE (_USART_CTRL_TXDELAY_TRIPLE << 26) /**< Shifted mode TRIPLE for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 228 | #define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ |
| mbed_official | 526:c320967f86b9 | 229 | #define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ |
| mbed_official | 526:c320967f86b9 | 230 | #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ |
| mbed_official | 526:c320967f86b9 | 231 | #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 232 | #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 233 | #define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ |
| mbed_official | 526:c320967f86b9 | 234 | #define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ |
| mbed_official | 526:c320967f86b9 | 235 | #define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ |
| mbed_official | 526:c320967f86b9 | 236 | #define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 237 | #define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 238 | #define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ |
| mbed_official | 526:c320967f86b9 | 239 | #define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ |
| mbed_official | 526:c320967f86b9 | 240 | #define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ |
| mbed_official | 526:c320967f86b9 | 241 | #define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 242 | #define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 243 | #define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */ |
| mbed_official | 526:c320967f86b9 | 244 | #define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ |
| mbed_official | 526:c320967f86b9 | 245 | #define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ |
| mbed_official | 526:c320967f86b9 | 246 | #define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 247 | #define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ |
| mbed_official | 526:c320967f86b9 | 248 | |
| mbed_official | 526:c320967f86b9 | 249 | /* Bit fields for USART FRAME */ |
| mbed_official | 526:c320967f86b9 | 250 | #define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 251 | #define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 252 | #define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ |
| mbed_official | 526:c320967f86b9 | 253 | #define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ |
| mbed_official | 526:c320967f86b9 | 254 | #define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 255 | #define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 256 | #define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 257 | #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 258 | #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 259 | #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 260 | #define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 261 | #define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 262 | #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 263 | #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 264 | #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 265 | #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 266 | #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 267 | #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 268 | #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 269 | #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 270 | #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 271 | #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 272 | #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 273 | #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 274 | #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 275 | #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 276 | #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 277 | #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 278 | #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 279 | #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 280 | #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 281 | #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 282 | #define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ |
| mbed_official | 526:c320967f86b9 | 283 | #define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ |
| mbed_official | 526:c320967f86b9 | 284 | #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 285 | #define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 286 | #define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 287 | #define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 288 | #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 289 | #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 290 | #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 291 | #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 292 | #define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ |
| mbed_official | 526:c320967f86b9 | 293 | #define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ |
| mbed_official | 526:c320967f86b9 | 294 | #define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 295 | #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 296 | #define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 297 | #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 298 | #define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 299 | #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 300 | #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 301 | #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 302 | #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 303 | #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ |
| mbed_official | 526:c320967f86b9 | 304 | |
| mbed_official | 526:c320967f86b9 | 305 | /* Bit fields for USART TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 306 | #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 307 | #define _USART_TRIGCTRL_MASK 0x00000077UL /**< Mask for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 308 | #define _USART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */ |
| mbed_official | 526:c320967f86b9 | 309 | #define _USART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */ |
| mbed_official | 526:c320967f86b9 | 310 | #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 311 | #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 312 | #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 313 | #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 314 | #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 315 | #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 316 | #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 317 | #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 318 | #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 319 | #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 320 | #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 321 | #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 322 | #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 323 | #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 324 | #define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ |
| mbed_official | 526:c320967f86b9 | 325 | #define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ |
| mbed_official | 526:c320967f86b9 | 326 | #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ |
| mbed_official | 526:c320967f86b9 | 327 | #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 328 | #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 329 | #define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ |
| mbed_official | 526:c320967f86b9 | 330 | #define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ |
| mbed_official | 526:c320967f86b9 | 331 | #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ |
| mbed_official | 526:c320967f86b9 | 332 | #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 333 | #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 334 | #define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ |
| mbed_official | 526:c320967f86b9 | 335 | #define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ |
| mbed_official | 526:c320967f86b9 | 336 | #define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ |
| mbed_official | 526:c320967f86b9 | 337 | #define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 338 | #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ |
| mbed_official | 526:c320967f86b9 | 339 | |
| mbed_official | 526:c320967f86b9 | 340 | /* Bit fields for USART CMD */ |
| mbed_official | 526:c320967f86b9 | 341 | #define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 342 | #define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 343 | #define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ |
| mbed_official | 526:c320967f86b9 | 344 | #define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ |
| mbed_official | 526:c320967f86b9 | 345 | #define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ |
| mbed_official | 526:c320967f86b9 | 346 | #define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 347 | #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 348 | #define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ |
| mbed_official | 526:c320967f86b9 | 349 | #define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ |
| mbed_official | 526:c320967f86b9 | 350 | #define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ |
| mbed_official | 526:c320967f86b9 | 351 | #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 352 | #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 353 | #define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ |
| mbed_official | 526:c320967f86b9 | 354 | #define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ |
| mbed_official | 526:c320967f86b9 | 355 | #define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ |
| mbed_official | 526:c320967f86b9 | 356 | #define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 357 | #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 358 | #define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ |
| mbed_official | 526:c320967f86b9 | 359 | #define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ |
| mbed_official | 526:c320967f86b9 | 360 | #define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ |
| mbed_official | 526:c320967f86b9 | 361 | #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 362 | #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 363 | #define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */ |
| mbed_official | 526:c320967f86b9 | 364 | #define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ |
| mbed_official | 526:c320967f86b9 | 365 | #define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ |
| mbed_official | 526:c320967f86b9 | 366 | #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 367 | #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 368 | #define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */ |
| mbed_official | 526:c320967f86b9 | 369 | #define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ |
| mbed_official | 526:c320967f86b9 | 370 | #define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ |
| mbed_official | 526:c320967f86b9 | 371 | #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 372 | #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 373 | #define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ |
| mbed_official | 526:c320967f86b9 | 374 | #define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ |
| mbed_official | 526:c320967f86b9 | 375 | #define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ |
| mbed_official | 526:c320967f86b9 | 376 | #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 377 | #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 378 | #define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ |
| mbed_official | 526:c320967f86b9 | 379 | #define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ |
| mbed_official | 526:c320967f86b9 | 380 | #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ |
| mbed_official | 526:c320967f86b9 | 381 | #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 382 | #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 383 | #define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ |
| mbed_official | 526:c320967f86b9 | 384 | #define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ |
| mbed_official | 526:c320967f86b9 | 385 | #define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ |
| mbed_official | 526:c320967f86b9 | 386 | #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 387 | #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 388 | #define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ |
| mbed_official | 526:c320967f86b9 | 389 | #define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ |
| mbed_official | 526:c320967f86b9 | 390 | #define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ |
| mbed_official | 526:c320967f86b9 | 391 | #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 392 | #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 393 | #define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ |
| mbed_official | 526:c320967f86b9 | 394 | #define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ |
| mbed_official | 526:c320967f86b9 | 395 | #define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ |
| mbed_official | 526:c320967f86b9 | 396 | #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 397 | #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 398 | #define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ |
| mbed_official | 526:c320967f86b9 | 399 | #define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ |
| mbed_official | 526:c320967f86b9 | 400 | #define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ |
| mbed_official | 526:c320967f86b9 | 401 | #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 402 | #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ |
| mbed_official | 526:c320967f86b9 | 403 | |
| mbed_official | 526:c320967f86b9 | 404 | /* Bit fields for USART STATUS */ |
| mbed_official | 526:c320967f86b9 | 405 | #define _USART_STATUS_RESETVALUE 0x00000040UL /**< Default value for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 406 | #define _USART_STATUS_MASK 0x00001FFFUL /**< Mask for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 407 | #define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ |
| mbed_official | 526:c320967f86b9 | 408 | #define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ |
| mbed_official | 526:c320967f86b9 | 409 | #define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ |
| mbed_official | 526:c320967f86b9 | 410 | #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 411 | #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 412 | #define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ |
| mbed_official | 526:c320967f86b9 | 413 | #define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ |
| mbed_official | 526:c320967f86b9 | 414 | #define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ |
| mbed_official | 526:c320967f86b9 | 415 | #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 416 | #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 417 | #define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */ |
| mbed_official | 526:c320967f86b9 | 418 | #define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ |
| mbed_official | 526:c320967f86b9 | 419 | #define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ |
| mbed_official | 526:c320967f86b9 | 420 | #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 421 | #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 422 | #define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ |
| mbed_official | 526:c320967f86b9 | 423 | #define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ |
| mbed_official | 526:c320967f86b9 | 424 | #define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ |
| mbed_official | 526:c320967f86b9 | 425 | #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 426 | #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 427 | #define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ |
| mbed_official | 526:c320967f86b9 | 428 | #define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ |
| mbed_official | 526:c320967f86b9 | 429 | #define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ |
| mbed_official | 526:c320967f86b9 | 430 | #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 431 | #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 432 | #define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ |
| mbed_official | 526:c320967f86b9 | 433 | #define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ |
| mbed_official | 526:c320967f86b9 | 434 | #define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ |
| mbed_official | 526:c320967f86b9 | 435 | #define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 436 | #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 437 | #define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ |
| mbed_official | 526:c320967f86b9 | 438 | #define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ |
| mbed_official | 526:c320967f86b9 | 439 | #define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ |
| mbed_official | 526:c320967f86b9 | 440 | #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 441 | #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 442 | #define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ |
| mbed_official | 526:c320967f86b9 | 443 | #define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ |
| mbed_official | 526:c320967f86b9 | 444 | #define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ |
| mbed_official | 526:c320967f86b9 | 445 | #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 446 | #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 447 | #define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ |
| mbed_official | 526:c320967f86b9 | 448 | #define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ |
| mbed_official | 526:c320967f86b9 | 449 | #define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ |
| mbed_official | 526:c320967f86b9 | 450 | #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 451 | #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 452 | #define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ |
| mbed_official | 526:c320967f86b9 | 453 | #define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ |
| mbed_official | 526:c320967f86b9 | 454 | #define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ |
| mbed_official | 526:c320967f86b9 | 455 | #define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 456 | #define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 457 | #define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ |
| mbed_official | 526:c320967f86b9 | 458 | #define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ |
| mbed_official | 526:c320967f86b9 | 459 | #define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ |
| mbed_official | 526:c320967f86b9 | 460 | #define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 461 | #define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 462 | #define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ |
| mbed_official | 526:c320967f86b9 | 463 | #define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ |
| mbed_official | 526:c320967f86b9 | 464 | #define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ |
| mbed_official | 526:c320967f86b9 | 465 | #define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 466 | #define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 467 | #define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ |
| mbed_official | 526:c320967f86b9 | 468 | #define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ |
| mbed_official | 526:c320967f86b9 | 469 | #define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ |
| mbed_official | 526:c320967f86b9 | 470 | #define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 471 | #define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ |
| mbed_official | 526:c320967f86b9 | 472 | |
| mbed_official | 526:c320967f86b9 | 473 | /* Bit fields for USART CLKDIV */ |
| mbed_official | 526:c320967f86b9 | 474 | #define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ |
| mbed_official | 526:c320967f86b9 | 475 | #define _USART_CLKDIV_MASK 0x001FFFF8UL /**< Mask for USART_CLKDIV */ |
| mbed_official | 526:c320967f86b9 | 476 | #define _USART_CLKDIV_DIVEXT_SHIFT 3 /**< Shift value for USART_DIVEXT */ |
| mbed_official | 526:c320967f86b9 | 477 | #define _USART_CLKDIV_DIVEXT_MASK 0x38UL /**< Bit mask for USART_DIVEXT */ |
| mbed_official | 526:c320967f86b9 | 478 | #define _USART_CLKDIV_DIVEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ |
| mbed_official | 526:c320967f86b9 | 479 | #define USART_CLKDIV_DIVEXT_DEFAULT (_USART_CLKDIV_DIVEXT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ |
| mbed_official | 526:c320967f86b9 | 480 | #define _USART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */ |
| mbed_official | 526:c320967f86b9 | 481 | #define _USART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */ |
| mbed_official | 526:c320967f86b9 | 482 | #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ |
| mbed_official | 526:c320967f86b9 | 483 | #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CLKDIV */ |
| mbed_official | 526:c320967f86b9 | 484 | |
| mbed_official | 526:c320967f86b9 | 485 | /* Bit fields for USART RXDATAX */ |
| mbed_official | 526:c320967f86b9 | 486 | #define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ |
| mbed_official | 526:c320967f86b9 | 487 | #define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ |
| mbed_official | 526:c320967f86b9 | 488 | #define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ |
| mbed_official | 526:c320967f86b9 | 489 | #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ |
| mbed_official | 526:c320967f86b9 | 490 | #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ |
| mbed_official | 526:c320967f86b9 | 491 | #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ |
| mbed_official | 526:c320967f86b9 | 492 | #define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ |
| mbed_official | 526:c320967f86b9 | 493 | #define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ |
| mbed_official | 526:c320967f86b9 | 494 | #define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ |
| mbed_official | 526:c320967f86b9 | 495 | #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ |
| mbed_official | 526:c320967f86b9 | 496 | #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ |
| mbed_official | 526:c320967f86b9 | 497 | #define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ |
| mbed_official | 526:c320967f86b9 | 498 | #define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ |
| mbed_official | 526:c320967f86b9 | 499 | #define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ |
| mbed_official | 526:c320967f86b9 | 500 | #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ |
| mbed_official | 526:c320967f86b9 | 501 | #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ |
| mbed_official | 526:c320967f86b9 | 502 | |
| mbed_official | 526:c320967f86b9 | 503 | /* Bit fields for USART RXDATA */ |
| mbed_official | 526:c320967f86b9 | 504 | #define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ |
| mbed_official | 526:c320967f86b9 | 505 | #define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ |
| mbed_official | 526:c320967f86b9 | 506 | #define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ |
| mbed_official | 526:c320967f86b9 | 507 | #define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ |
| mbed_official | 526:c320967f86b9 | 508 | #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ |
| mbed_official | 526:c320967f86b9 | 509 | #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ |
| mbed_official | 526:c320967f86b9 | 510 | |
| mbed_official | 526:c320967f86b9 | 511 | /* Bit fields for USART RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 512 | #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 513 | #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 514 | #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ |
| mbed_official | 526:c320967f86b9 | 515 | #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ |
| mbed_official | 526:c320967f86b9 | 516 | #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 517 | #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 518 | #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ |
| mbed_official | 526:c320967f86b9 | 519 | #define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ |
| mbed_official | 526:c320967f86b9 | 520 | #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ |
| mbed_official | 526:c320967f86b9 | 521 | #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 522 | #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 523 | #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ |
| mbed_official | 526:c320967f86b9 | 524 | #define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ |
| mbed_official | 526:c320967f86b9 | 525 | #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ |
| mbed_official | 526:c320967f86b9 | 526 | #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 527 | #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 528 | #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ |
| mbed_official | 526:c320967f86b9 | 529 | #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ |
| mbed_official | 526:c320967f86b9 | 530 | #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 531 | #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 532 | #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ |
| mbed_official | 526:c320967f86b9 | 533 | #define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ |
| mbed_official | 526:c320967f86b9 | 534 | #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ |
| mbed_official | 526:c320967f86b9 | 535 | #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 536 | #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 537 | #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ |
| mbed_official | 526:c320967f86b9 | 538 | #define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ |
| mbed_official | 526:c320967f86b9 | 539 | #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ |
| mbed_official | 526:c320967f86b9 | 540 | #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 541 | #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 542 | |
| mbed_official | 526:c320967f86b9 | 543 | /* Bit fields for USART RXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 544 | #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 545 | #define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 546 | #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ |
| mbed_official | 526:c320967f86b9 | 547 | #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ |
| mbed_official | 526:c320967f86b9 | 548 | #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 549 | #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 550 | #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ |
| mbed_official | 526:c320967f86b9 | 551 | #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ |
| mbed_official | 526:c320967f86b9 | 552 | #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 553 | #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 554 | |
| mbed_official | 526:c320967f86b9 | 555 | /* Bit fields for USART RXDATAXP */ |
| mbed_official | 526:c320967f86b9 | 556 | #define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ |
| mbed_official | 526:c320967f86b9 | 557 | #define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ |
| mbed_official | 526:c320967f86b9 | 558 | #define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ |
| mbed_official | 526:c320967f86b9 | 559 | #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ |
| mbed_official | 526:c320967f86b9 | 560 | #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ |
| mbed_official | 526:c320967f86b9 | 561 | #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ |
| mbed_official | 526:c320967f86b9 | 562 | #define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ |
| mbed_official | 526:c320967f86b9 | 563 | #define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ |
| mbed_official | 526:c320967f86b9 | 564 | #define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ |
| mbed_official | 526:c320967f86b9 | 565 | #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ |
| mbed_official | 526:c320967f86b9 | 566 | #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ |
| mbed_official | 526:c320967f86b9 | 567 | #define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ |
| mbed_official | 526:c320967f86b9 | 568 | #define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ |
| mbed_official | 526:c320967f86b9 | 569 | #define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ |
| mbed_official | 526:c320967f86b9 | 570 | #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ |
| mbed_official | 526:c320967f86b9 | 571 | #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ |
| mbed_official | 526:c320967f86b9 | 572 | |
| mbed_official | 526:c320967f86b9 | 573 | /* Bit fields for USART RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 574 | #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 575 | #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 576 | #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ |
| mbed_official | 526:c320967f86b9 | 577 | #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ |
| mbed_official | 526:c320967f86b9 | 578 | #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 579 | #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 580 | #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ |
| mbed_official | 526:c320967f86b9 | 581 | #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ |
| mbed_official | 526:c320967f86b9 | 582 | #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ |
| mbed_official | 526:c320967f86b9 | 583 | #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 584 | #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 585 | #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ |
| mbed_official | 526:c320967f86b9 | 586 | #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ |
| mbed_official | 526:c320967f86b9 | 587 | #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ |
| mbed_official | 526:c320967f86b9 | 588 | #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 589 | #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 590 | #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ |
| mbed_official | 526:c320967f86b9 | 591 | #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ |
| mbed_official | 526:c320967f86b9 | 592 | #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 593 | #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 594 | #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ |
| mbed_official | 526:c320967f86b9 | 595 | #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ |
| mbed_official | 526:c320967f86b9 | 596 | #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ |
| mbed_official | 526:c320967f86b9 | 597 | #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 598 | #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 599 | #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ |
| mbed_official | 526:c320967f86b9 | 600 | #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ |
| mbed_official | 526:c320967f86b9 | 601 | #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ |
| mbed_official | 526:c320967f86b9 | 602 | #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 603 | #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ |
| mbed_official | 526:c320967f86b9 | 604 | |
| mbed_official | 526:c320967f86b9 | 605 | /* Bit fields for USART TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 606 | #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 607 | #define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 608 | #define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 609 | #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 610 | #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 611 | #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 612 | #define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ |
| mbed_official | 526:c320967f86b9 | 613 | #define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ |
| mbed_official | 526:c320967f86b9 | 614 | #define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ |
| mbed_official | 526:c320967f86b9 | 615 | #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 616 | #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 617 | #define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ |
| mbed_official | 526:c320967f86b9 | 618 | #define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ |
| mbed_official | 526:c320967f86b9 | 619 | #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ |
| mbed_official | 526:c320967f86b9 | 620 | #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 621 | #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 622 | #define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ |
| mbed_official | 526:c320967f86b9 | 623 | #define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ |
| mbed_official | 526:c320967f86b9 | 624 | #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ |
| mbed_official | 526:c320967f86b9 | 625 | #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 626 | #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 627 | #define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ |
| mbed_official | 526:c320967f86b9 | 628 | #define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ |
| mbed_official | 526:c320967f86b9 | 629 | #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ |
| mbed_official | 526:c320967f86b9 | 630 | #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 631 | #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 632 | #define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ |
| mbed_official | 526:c320967f86b9 | 633 | #define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ |
| mbed_official | 526:c320967f86b9 | 634 | #define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ |
| mbed_official | 526:c320967f86b9 | 635 | #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 636 | #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ |
| mbed_official | 526:c320967f86b9 | 637 | |
| mbed_official | 526:c320967f86b9 | 638 | /* Bit fields for USART TXDATA */ |
| mbed_official | 526:c320967f86b9 | 639 | #define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ |
| mbed_official | 526:c320967f86b9 | 640 | #define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ |
| mbed_official | 526:c320967f86b9 | 641 | #define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ |
| mbed_official | 526:c320967f86b9 | 642 | #define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ |
| mbed_official | 526:c320967f86b9 | 643 | #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ |
| mbed_official | 526:c320967f86b9 | 644 | #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ |
| mbed_official | 526:c320967f86b9 | 645 | |
| mbed_official | 526:c320967f86b9 | 646 | /* Bit fields for USART TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 647 | #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 648 | #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 649 | #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ |
| mbed_official | 526:c320967f86b9 | 650 | #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ |
| mbed_official | 526:c320967f86b9 | 651 | #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 652 | #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 653 | #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ |
| mbed_official | 526:c320967f86b9 | 654 | #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ |
| mbed_official | 526:c320967f86b9 | 655 | #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ |
| mbed_official | 526:c320967f86b9 | 656 | #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 657 | #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 658 | #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ |
| mbed_official | 526:c320967f86b9 | 659 | #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ |
| mbed_official | 526:c320967f86b9 | 660 | #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ |
| mbed_official | 526:c320967f86b9 | 661 | #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 662 | #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 663 | #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ |
| mbed_official | 526:c320967f86b9 | 664 | #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ |
| mbed_official | 526:c320967f86b9 | 665 | #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ |
| mbed_official | 526:c320967f86b9 | 666 | #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 667 | #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 668 | #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ |
| mbed_official | 526:c320967f86b9 | 669 | #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ |
| mbed_official | 526:c320967f86b9 | 670 | #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ |
| mbed_official | 526:c320967f86b9 | 671 | #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 672 | #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 673 | #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ |
| mbed_official | 526:c320967f86b9 | 674 | #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ |
| mbed_official | 526:c320967f86b9 | 675 | #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ |
| mbed_official | 526:c320967f86b9 | 676 | #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 677 | #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 678 | #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ |
| mbed_official | 526:c320967f86b9 | 679 | #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ |
| mbed_official | 526:c320967f86b9 | 680 | #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 681 | #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 682 | #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ |
| mbed_official | 526:c320967f86b9 | 683 | #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ |
| mbed_official | 526:c320967f86b9 | 684 | #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ |
| mbed_official | 526:c320967f86b9 | 685 | #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 686 | #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 687 | #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ |
| mbed_official | 526:c320967f86b9 | 688 | #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ |
| mbed_official | 526:c320967f86b9 | 689 | #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ |
| mbed_official | 526:c320967f86b9 | 690 | #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 691 | #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 692 | #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ |
| mbed_official | 526:c320967f86b9 | 693 | #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ |
| mbed_official | 526:c320967f86b9 | 694 | #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ |
| mbed_official | 526:c320967f86b9 | 695 | #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 696 | #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 697 | #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ |
| mbed_official | 526:c320967f86b9 | 698 | #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ |
| mbed_official | 526:c320967f86b9 | 699 | #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ |
| mbed_official | 526:c320967f86b9 | 700 | #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 701 | #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 702 | #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ |
| mbed_official | 526:c320967f86b9 | 703 | #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ |
| mbed_official | 526:c320967f86b9 | 704 | #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ |
| mbed_official | 526:c320967f86b9 | 705 | #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 706 | #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ |
| mbed_official | 526:c320967f86b9 | 707 | |
| mbed_official | 526:c320967f86b9 | 708 | /* Bit fields for USART TXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 709 | #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 710 | #define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 711 | #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ |
| mbed_official | 526:c320967f86b9 | 712 | #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ |
| mbed_official | 526:c320967f86b9 | 713 | #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 714 | #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 715 | #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ |
| mbed_official | 526:c320967f86b9 | 716 | #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ |
| mbed_official | 526:c320967f86b9 | 717 | #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 718 | #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ |
| mbed_official | 526:c320967f86b9 | 719 | |
| mbed_official | 526:c320967f86b9 | 720 | /* Bit fields for USART IF */ |
| mbed_official | 526:c320967f86b9 | 721 | #define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 722 | #define _USART_IF_MASK 0x00001FFFUL /**< Mask for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 723 | #define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 724 | #define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ |
| mbed_official | 526:c320967f86b9 | 725 | #define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ |
| mbed_official | 526:c320967f86b9 | 726 | #define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 727 | #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 728 | #define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 729 | #define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ |
| mbed_official | 526:c320967f86b9 | 730 | #define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ |
| mbed_official | 526:c320967f86b9 | 731 | #define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 732 | #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 733 | #define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 734 | #define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ |
| mbed_official | 526:c320967f86b9 | 735 | #define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ |
| mbed_official | 526:c320967f86b9 | 736 | #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 737 | #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 738 | #define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 739 | #define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ |
| mbed_official | 526:c320967f86b9 | 740 | #define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ |
| mbed_official | 526:c320967f86b9 | 741 | #define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 742 | #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 743 | #define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 744 | #define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ |
| mbed_official | 526:c320967f86b9 | 745 | #define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ |
| mbed_official | 526:c320967f86b9 | 746 | #define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 747 | #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 748 | #define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 749 | #define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ |
| mbed_official | 526:c320967f86b9 | 750 | #define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ |
| mbed_official | 526:c320967f86b9 | 751 | #define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 752 | #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 753 | #define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 754 | #define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ |
| mbed_official | 526:c320967f86b9 | 755 | #define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ |
| mbed_official | 526:c320967f86b9 | 756 | #define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 757 | #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 758 | #define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 759 | #define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ |
| mbed_official | 526:c320967f86b9 | 760 | #define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ |
| mbed_official | 526:c320967f86b9 | 761 | #define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 762 | #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 763 | #define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 764 | #define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ |
| mbed_official | 526:c320967f86b9 | 765 | #define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ |
| mbed_official | 526:c320967f86b9 | 766 | #define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 767 | #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 768 | #define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 769 | #define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ |
| mbed_official | 526:c320967f86b9 | 770 | #define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ |
| mbed_official | 526:c320967f86b9 | 771 | #define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 772 | #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 773 | #define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 774 | #define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ |
| mbed_official | 526:c320967f86b9 | 775 | #define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ |
| mbed_official | 526:c320967f86b9 | 776 | #define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 777 | #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 778 | #define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 779 | #define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ |
| mbed_official | 526:c320967f86b9 | 780 | #define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ |
| mbed_official | 526:c320967f86b9 | 781 | #define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 782 | #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 783 | #define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 784 | #define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ |
| mbed_official | 526:c320967f86b9 | 785 | #define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ |
| mbed_official | 526:c320967f86b9 | 786 | #define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 787 | #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ |
| mbed_official | 526:c320967f86b9 | 788 | |
| mbed_official | 526:c320967f86b9 | 789 | /* Bit fields for USART IFS */ |
| mbed_official | 526:c320967f86b9 | 790 | #define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 791 | #define _USART_IFS_MASK 0x00001FF9UL /**< Mask for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 792 | #define USART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 793 | #define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */ |
| mbed_official | 526:c320967f86b9 | 794 | #define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ |
| mbed_official | 526:c320967f86b9 | 795 | #define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 796 | #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 797 | #define USART_IFS_RXFULL (0x1UL << 3) /**< Set RX Buffer Full Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 798 | #define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ |
| mbed_official | 526:c320967f86b9 | 799 | #define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ |
| mbed_official | 526:c320967f86b9 | 800 | #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 801 | #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 802 | #define USART_IFS_RXOF (0x1UL << 4) /**< Set RX Overflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 803 | #define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ |
| mbed_official | 526:c320967f86b9 | 804 | #define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ |
| mbed_official | 526:c320967f86b9 | 805 | #define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 806 | #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 807 | #define USART_IFS_RXUF (0x1UL << 5) /**< Set RX Underflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 808 | #define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ |
| mbed_official | 526:c320967f86b9 | 809 | #define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ |
| mbed_official | 526:c320967f86b9 | 810 | #define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 811 | #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 812 | #define USART_IFS_TXOF (0x1UL << 6) /**< Set TX Overflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 813 | #define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ |
| mbed_official | 526:c320967f86b9 | 814 | #define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ |
| mbed_official | 526:c320967f86b9 | 815 | #define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 816 | #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 817 | #define USART_IFS_TXUF (0x1UL << 7) /**< Set TX Underflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 818 | #define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ |
| mbed_official | 526:c320967f86b9 | 819 | #define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ |
| mbed_official | 526:c320967f86b9 | 820 | #define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 821 | #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 822 | #define USART_IFS_PERR (0x1UL << 8) /**< Set Parity Error Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 823 | #define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */ |
| mbed_official | 526:c320967f86b9 | 824 | #define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ |
| mbed_official | 526:c320967f86b9 | 825 | #define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 826 | #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 827 | #define USART_IFS_FERR (0x1UL << 9) /**< Set Framing Error Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 828 | #define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */ |
| mbed_official | 526:c320967f86b9 | 829 | #define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ |
| mbed_official | 526:c320967f86b9 | 830 | #define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 831 | #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 832 | #define USART_IFS_MPAF (0x1UL << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 833 | #define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ |
| mbed_official | 526:c320967f86b9 | 834 | #define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ |
| mbed_official | 526:c320967f86b9 | 835 | #define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 836 | #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 837 | #define USART_IFS_SSM (0x1UL << 11) /**< Set Slave-Select in Master mode Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 838 | #define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */ |
| mbed_official | 526:c320967f86b9 | 839 | #define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ |
| mbed_official | 526:c320967f86b9 | 840 | #define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 841 | #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 842 | #define USART_IFS_CCF (0x1UL << 12) /**< Set Collision Check Fail Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 843 | #define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */ |
| mbed_official | 526:c320967f86b9 | 844 | #define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ |
| mbed_official | 526:c320967f86b9 | 845 | #define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 846 | #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */ |
| mbed_official | 526:c320967f86b9 | 847 | |
| mbed_official | 526:c320967f86b9 | 848 | /* Bit fields for USART IFC */ |
| mbed_official | 526:c320967f86b9 | 849 | #define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 850 | #define _USART_IFC_MASK 0x00001FF9UL /**< Mask for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 851 | #define USART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 852 | #define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */ |
| mbed_official | 526:c320967f86b9 | 853 | #define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ |
| mbed_official | 526:c320967f86b9 | 854 | #define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 855 | #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 856 | #define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RX Buffer Full Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 857 | #define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ |
| mbed_official | 526:c320967f86b9 | 858 | #define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ |
| mbed_official | 526:c320967f86b9 | 859 | #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 860 | #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 861 | #define USART_IFC_RXOF (0x1UL << 4) /**< Clear RX Overflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 862 | #define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ |
| mbed_official | 526:c320967f86b9 | 863 | #define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ |
| mbed_official | 526:c320967f86b9 | 864 | #define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 865 | #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 866 | #define USART_IFC_RXUF (0x1UL << 5) /**< Clear RX Underflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 867 | #define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ |
| mbed_official | 526:c320967f86b9 | 868 | #define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ |
| mbed_official | 526:c320967f86b9 | 869 | #define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 870 | #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 871 | #define USART_IFC_TXOF (0x1UL << 6) /**< Clear TX Overflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 872 | #define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ |
| mbed_official | 526:c320967f86b9 | 873 | #define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ |
| mbed_official | 526:c320967f86b9 | 874 | #define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 875 | #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 876 | #define USART_IFC_TXUF (0x1UL << 7) /**< Clear TX Underflow Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 877 | #define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ |
| mbed_official | 526:c320967f86b9 | 878 | #define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ |
| mbed_official | 526:c320967f86b9 | 879 | #define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 880 | #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 881 | #define USART_IFC_PERR (0x1UL << 8) /**< Clear Parity Error Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 882 | #define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */ |
| mbed_official | 526:c320967f86b9 | 883 | #define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ |
| mbed_official | 526:c320967f86b9 | 884 | #define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 885 | #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 886 | #define USART_IFC_FERR (0x1UL << 9) /**< Clear Framing Error Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 887 | #define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */ |
| mbed_official | 526:c320967f86b9 | 888 | #define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ |
| mbed_official | 526:c320967f86b9 | 889 | #define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 890 | #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 891 | #define USART_IFC_MPAF (0x1UL << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 892 | #define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ |
| mbed_official | 526:c320967f86b9 | 893 | #define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ |
| mbed_official | 526:c320967f86b9 | 894 | #define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 895 | #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 896 | #define USART_IFC_SSM (0x1UL << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 897 | #define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */ |
| mbed_official | 526:c320967f86b9 | 898 | #define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ |
| mbed_official | 526:c320967f86b9 | 899 | #define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 900 | #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 901 | #define USART_IFC_CCF (0x1UL << 12) /**< Clear Collision Check Fail Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 902 | #define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */ |
| mbed_official | 526:c320967f86b9 | 903 | #define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ |
| mbed_official | 526:c320967f86b9 | 904 | #define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 905 | #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */ |
| mbed_official | 526:c320967f86b9 | 906 | |
| mbed_official | 526:c320967f86b9 | 907 | /* Bit fields for USART IEN */ |
| mbed_official | 526:c320967f86b9 | 908 | #define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 909 | #define _USART_IEN_MASK 0x00001FFFUL /**< Mask for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 910 | #define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 911 | #define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ |
| mbed_official | 526:c320967f86b9 | 912 | #define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ |
| mbed_official | 526:c320967f86b9 | 913 | #define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 914 | #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 915 | #define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 916 | #define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ |
| mbed_official | 526:c320967f86b9 | 917 | #define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ |
| mbed_official | 526:c320967f86b9 | 918 | #define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 919 | #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 920 | #define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 921 | #define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ |
| mbed_official | 526:c320967f86b9 | 922 | #define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ |
| mbed_official | 526:c320967f86b9 | 923 | #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 924 | #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 925 | #define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 926 | #define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ |
| mbed_official | 526:c320967f86b9 | 927 | #define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ |
| mbed_official | 526:c320967f86b9 | 928 | #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 929 | #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 930 | #define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 931 | #define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ |
| mbed_official | 526:c320967f86b9 | 932 | #define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ |
| mbed_official | 526:c320967f86b9 | 933 | #define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 934 | #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 935 | #define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 936 | #define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ |
| mbed_official | 526:c320967f86b9 | 937 | #define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ |
| mbed_official | 526:c320967f86b9 | 938 | #define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 939 | #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 940 | #define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 941 | #define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ |
| mbed_official | 526:c320967f86b9 | 942 | #define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ |
| mbed_official | 526:c320967f86b9 | 943 | #define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 944 | #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 945 | #define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 946 | #define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ |
| mbed_official | 526:c320967f86b9 | 947 | #define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ |
| mbed_official | 526:c320967f86b9 | 948 | #define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 949 | #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 950 | #define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 951 | #define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ |
| mbed_official | 526:c320967f86b9 | 952 | #define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ |
| mbed_official | 526:c320967f86b9 | 953 | #define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 954 | #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 955 | #define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 956 | #define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ |
| mbed_official | 526:c320967f86b9 | 957 | #define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ |
| mbed_official | 526:c320967f86b9 | 958 | #define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 959 | #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 960 | #define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 961 | #define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ |
| mbed_official | 526:c320967f86b9 | 962 | #define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ |
| mbed_official | 526:c320967f86b9 | 963 | #define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 964 | #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 965 | #define USART_IEN_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 966 | #define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ |
| mbed_official | 526:c320967f86b9 | 967 | #define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ |
| mbed_official | 526:c320967f86b9 | 968 | #define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 969 | #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 970 | #define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 971 | #define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ |
| mbed_official | 526:c320967f86b9 | 972 | #define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ |
| mbed_official | 526:c320967f86b9 | 973 | #define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 974 | #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ |
| mbed_official | 526:c320967f86b9 | 975 | |
| mbed_official | 526:c320967f86b9 | 976 | /* Bit fields for USART IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 977 | #define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 978 | #define _USART_IRCTRL_MASK 0x000000FFUL /**< Mask for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 979 | #define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ |
| mbed_official | 526:c320967f86b9 | 980 | #define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ |
| mbed_official | 526:c320967f86b9 | 981 | #define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ |
| mbed_official | 526:c320967f86b9 | 982 | #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 983 | #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 984 | #define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ |
| mbed_official | 526:c320967f86b9 | 985 | #define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ |
| mbed_official | 526:c320967f86b9 | 986 | #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 987 | #define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 988 | #define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 989 | #define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 990 | #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 991 | #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 992 | #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 993 | #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 994 | #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 995 | #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 996 | #define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ |
| mbed_official | 526:c320967f86b9 | 997 | #define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ |
| mbed_official | 526:c320967f86b9 | 998 | #define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ |
| mbed_official | 526:c320967f86b9 | 999 | #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1000 | #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1001 | #define _USART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */ |
| mbed_official | 526:c320967f86b9 | 1002 | #define _USART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */ |
| mbed_official | 526:c320967f86b9 | 1003 | #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1004 | #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1005 | #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1006 | #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1007 | #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1008 | #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1009 | #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1010 | #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1011 | #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1012 | #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1013 | #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1014 | #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1015 | #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1016 | #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1017 | #define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */ |
| mbed_official | 526:c320967f86b9 | 1018 | #define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */ |
| mbed_official | 526:c320967f86b9 | 1019 | #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */ |
| mbed_official | 526:c320967f86b9 | 1020 | #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1021 | #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */ |
| mbed_official | 526:c320967f86b9 | 1022 | |
| mbed_official | 526:c320967f86b9 | 1023 | /* Bit fields for USART ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1024 | #define _USART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1025 | #define _USART_ROUTE_MASK 0x0000070FUL /**< Mask for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1026 | #define USART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */ |
| mbed_official | 526:c320967f86b9 | 1027 | #define _USART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */ |
| mbed_official | 526:c320967f86b9 | 1028 | #define _USART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */ |
| mbed_official | 526:c320967f86b9 | 1029 | #define _USART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1030 | #define USART_ROUTE_RXPEN_DEFAULT (_USART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1031 | #define USART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */ |
| mbed_official | 526:c320967f86b9 | 1032 | #define _USART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */ |
| mbed_official | 526:c320967f86b9 | 1033 | #define _USART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */ |
| mbed_official | 526:c320967f86b9 | 1034 | #define _USART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1035 | #define USART_ROUTE_TXPEN_DEFAULT (_USART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1036 | #define USART_ROUTE_CSPEN (0x1UL << 2) /**< CS Pin Enable */ |
| mbed_official | 526:c320967f86b9 | 1037 | #define _USART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */ |
| mbed_official | 526:c320967f86b9 | 1038 | #define _USART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */ |
| mbed_official | 526:c320967f86b9 | 1039 | #define _USART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1040 | #define USART_ROUTE_CSPEN_DEFAULT (_USART_ROUTE_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1041 | #define USART_ROUTE_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */ |
| mbed_official | 526:c320967f86b9 | 1042 | #define _USART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */ |
| mbed_official | 526:c320967f86b9 | 1043 | #define _USART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */ |
| mbed_official | 526:c320967f86b9 | 1044 | #define _USART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1045 | #define USART_ROUTE_CLKPEN_DEFAULT (_USART_ROUTE_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1046 | #define _USART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */ |
| mbed_official | 526:c320967f86b9 | 1047 | #define _USART_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for USART_LOCATION */ |
| mbed_official | 526:c320967f86b9 | 1048 | #define _USART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1049 | #define _USART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1050 | #define _USART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1051 | #define _USART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1052 | #define _USART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1053 | #define _USART_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1054 | #define _USART_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1055 | #define _USART_ROUTE_LOCATION_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1056 | #define USART_ROUTE_LOCATION_LOC0 (_USART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1057 | #define USART_ROUTE_LOCATION_DEFAULT (_USART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1058 | #define USART_ROUTE_LOCATION_LOC1 (_USART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1059 | #define USART_ROUTE_LOCATION_LOC2 (_USART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1060 | #define USART_ROUTE_LOCATION_LOC3 (_USART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1061 | #define USART_ROUTE_LOCATION_LOC4 (_USART_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1062 | #define USART_ROUTE_LOCATION_LOC5 (_USART_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1063 | #define USART_ROUTE_LOCATION_LOC6 (_USART_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 1064 | |
| mbed_official | 526:c320967f86b9 | 1065 | /* Bit fields for USART INPUT */ |
| mbed_official | 526:c320967f86b9 | 1066 | #define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1067 | #define _USART_INPUT_MASK 0x00000017UL /**< Mask for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1068 | #define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */ |
| mbed_official | 526:c320967f86b9 | 1069 | #define _USART_INPUT_RXPRSSEL_MASK 0x7UL /**< Bit mask for USART_RXPRSSEL */ |
| mbed_official | 526:c320967f86b9 | 1070 | #define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1071 | #define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1072 | #define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1073 | #define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1074 | #define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1075 | #define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1076 | #define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1077 | #define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1078 | #define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1079 | #define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1080 | #define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1081 | #define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1082 | #define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1083 | #define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1084 | #define USART_INPUT_RXPRS (0x1UL << 4) /**< PRS RX Enable */ |
| mbed_official | 526:c320967f86b9 | 1085 | #define _USART_INPUT_RXPRS_SHIFT 4 /**< Shift value for USART_RXPRS */ |
| mbed_official | 526:c320967f86b9 | 1086 | #define _USART_INPUT_RXPRS_MASK 0x10UL /**< Bit mask for USART_RXPRS */ |
| mbed_official | 526:c320967f86b9 | 1087 | #define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1088 | #define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_INPUT */ |
| mbed_official | 526:c320967f86b9 | 1089 | |
| mbed_official | 526:c320967f86b9 | 1090 | /* Bit fields for USART I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1091 | #define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1092 | #define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1093 | #define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ |
| mbed_official | 526:c320967f86b9 | 1094 | #define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ |
| mbed_official | 526:c320967f86b9 | 1095 | #define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ |
| mbed_official | 526:c320967f86b9 | 1096 | #define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1097 | #define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1098 | #define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ |
| mbed_official | 526:c320967f86b9 | 1099 | #define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ |
| mbed_official | 526:c320967f86b9 | 1100 | #define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ |
| mbed_official | 526:c320967f86b9 | 1101 | #define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1102 | #define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1103 | #define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ |
| mbed_official | 526:c320967f86b9 | 1104 | #define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ |
| mbed_official | 526:c320967f86b9 | 1105 | #define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ |
| mbed_official | 526:c320967f86b9 | 1106 | #define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1107 | #define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1108 | #define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1109 | #define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1110 | #define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1111 | #define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1112 | #define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ |
| mbed_official | 526:c320967f86b9 | 1113 | #define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ |
| mbed_official | 526:c320967f86b9 | 1114 | #define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ |
| mbed_official | 526:c320967f86b9 | 1115 | #define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1116 | #define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1117 | #define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ |
| mbed_official | 526:c320967f86b9 | 1118 | #define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ |
| mbed_official | 526:c320967f86b9 | 1119 | #define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ |
| mbed_official | 526:c320967f86b9 | 1120 | #define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1121 | #define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1122 | #define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ |
| mbed_official | 526:c320967f86b9 | 1123 | #define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ |
| mbed_official | 526:c320967f86b9 | 1124 | #define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1125 | #define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1126 | #define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1127 | #define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1128 | #define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1129 | #define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1130 | #define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1131 | #define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1132 | #define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1133 | #define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1134 | #define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1135 | #define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1136 | #define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1137 | #define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1138 | #define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1139 | #define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1140 | #define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1141 | #define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ |
| mbed_official | 526:c320967f86b9 | 1142 | |
| mbed_official | 526:c320967f86b9 | 1143 | /** @} End of group EFM32HG_USART */ |
| mbed_official | 526:c320967f86b9 | 1144 | |
| mbed_official | 526:c320967f86b9 | 1145 |