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mbed official
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG_STK3700/efm32gg_emu.h@526:c320967f86b9, 2015-04-28 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Apr 28 11:45:12 2015 +0100
- Revision:
- 526:c320967f86b9
Synchronized with git revision 299385b8331142b9dc524da7a986536f60b14553
Full URL: https://github.com/mbedmicro/mbed/commit/299385b8331142b9dc524da7a986536f60b14553/
Add in Silicon Labs targets with asynchronous API support
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 526:c320967f86b9 | 1 | /**************************************************************************//** |
| mbed_official | 526:c320967f86b9 | 2 | * @file efm32gg_emu.h |
| mbed_official | 526:c320967f86b9 | 3 | * @brief EFM32GG_EMU register and bit field definitions |
| mbed_official | 526:c320967f86b9 | 4 | * @version 3.20.6 |
| mbed_official | 526:c320967f86b9 | 5 | ****************************************************************************** |
| mbed_official | 526:c320967f86b9 | 6 | * @section License |
| mbed_official | 526:c320967f86b9 | 7 | * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| mbed_official | 526:c320967f86b9 | 8 | ****************************************************************************** |
| mbed_official | 526:c320967f86b9 | 9 | * |
| mbed_official | 526:c320967f86b9 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| mbed_official | 526:c320967f86b9 | 11 | * including commercial applications, and to alter it and redistribute it |
| mbed_official | 526:c320967f86b9 | 12 | * freely, subject to the following restrictions: |
| mbed_official | 526:c320967f86b9 | 13 | * |
| mbed_official | 526:c320967f86b9 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| mbed_official | 526:c320967f86b9 | 15 | * claim that you wrote the original software.@n |
| mbed_official | 526:c320967f86b9 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| mbed_official | 526:c320967f86b9 | 17 | * misrepresented as being the original software.@n |
| mbed_official | 526:c320967f86b9 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| mbed_official | 526:c320967f86b9 | 19 | * |
| mbed_official | 526:c320967f86b9 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| mbed_official | 526:c320967f86b9 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| mbed_official | 526:c320967f86b9 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| mbed_official | 526:c320967f86b9 | 23 | * kind, including, but not limited to, any implied warranties of |
| mbed_official | 526:c320967f86b9 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| mbed_official | 526:c320967f86b9 | 25 | * infringement of any proprietary rights of a third party. |
| mbed_official | 526:c320967f86b9 | 26 | * |
| mbed_official | 526:c320967f86b9 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| mbed_official | 526:c320967f86b9 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| mbed_official | 526:c320967f86b9 | 29 | * any third party, arising from your use of this Software. |
| mbed_official | 526:c320967f86b9 | 30 | * |
| mbed_official | 526:c320967f86b9 | 31 | *****************************************************************************/ |
| mbed_official | 526:c320967f86b9 | 32 | /**************************************************************************//** |
| mbed_official | 526:c320967f86b9 | 33 | * @defgroup EFM32GG_EMU |
| mbed_official | 526:c320967f86b9 | 34 | * @{ |
| mbed_official | 526:c320967f86b9 | 35 | * @brief EFM32GG_EMU Register Declaration |
| mbed_official | 526:c320967f86b9 | 36 | *****************************************************************************/ |
| mbed_official | 526:c320967f86b9 | 37 | typedef struct |
| mbed_official | 526:c320967f86b9 | 38 | { |
| mbed_official | 526:c320967f86b9 | 39 | __IO uint32_t CTRL; /**< Control Register */ |
| mbed_official | 526:c320967f86b9 | 40 | __IO uint32_t MEMCTRL; /**< Memory Control Register */ |
| mbed_official | 526:c320967f86b9 | 41 | __IO uint32_t LOCK; /**< Configuration Lock Register */ |
| mbed_official | 526:c320967f86b9 | 42 | |
| mbed_official | 526:c320967f86b9 | 43 | uint32_t RESERVED0[6]; /**< Reserved for future use **/ |
| mbed_official | 526:c320967f86b9 | 44 | __IO uint32_t AUXCTRL; /**< Auxiliary Control Register */ |
| mbed_official | 526:c320967f86b9 | 45 | |
| mbed_official | 526:c320967f86b9 | 46 | uint32_t RESERVED1[1]; /**< Reserved for future use **/ |
| mbed_official | 526:c320967f86b9 | 47 | __IO uint32_t EM4CONF; /**< Energy mode 4 configuration register */ |
| mbed_official | 526:c320967f86b9 | 48 | __IO uint32_t BUCTRL; /**< Backup Power configuration register */ |
| mbed_official | 526:c320967f86b9 | 49 | __IO uint32_t PWRCONF; /**< Power connection configuration register */ |
| mbed_official | 526:c320967f86b9 | 50 | __IO uint32_t BUINACT; /**< Backup mode inactive configuration register */ |
| mbed_official | 526:c320967f86b9 | 51 | __IO uint32_t BUACT; /**< Backup mode active configuration register */ |
| mbed_official | 526:c320967f86b9 | 52 | __I uint32_t STATUS; /**< Status register */ |
| mbed_official | 526:c320967f86b9 | 53 | __IO uint32_t ROUTE; /**< I/O Routing Register */ |
| mbed_official | 526:c320967f86b9 | 54 | __I uint32_t IF; /**< Interrupt Flag Register */ |
| mbed_official | 526:c320967f86b9 | 55 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
| mbed_official | 526:c320967f86b9 | 56 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| mbed_official | 526:c320967f86b9 | 57 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
| mbed_official | 526:c320967f86b9 | 58 | __IO uint32_t BUBODBUVINCAL; /**< BU_VIN Backup BOD calibration */ |
| mbed_official | 526:c320967f86b9 | 59 | __IO uint32_t BUBODUNREGCAL; /**< Unregulated power Backup BOD calibration */ |
| mbed_official | 526:c320967f86b9 | 60 | } EMU_TypeDef; /** @} */ |
| mbed_official | 526:c320967f86b9 | 61 | |
| mbed_official | 526:c320967f86b9 | 62 | /**************************************************************************//** |
| mbed_official | 526:c320967f86b9 | 63 | * @defgroup EFM32GG_EMU_BitFields |
| mbed_official | 526:c320967f86b9 | 64 | * @{ |
| mbed_official | 526:c320967f86b9 | 65 | *****************************************************************************/ |
| mbed_official | 526:c320967f86b9 | 66 | |
| mbed_official | 526:c320967f86b9 | 67 | /* Bit fields for EMU CTRL */ |
| mbed_official | 526:c320967f86b9 | 68 | #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 69 | #define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 70 | #define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */ |
| mbed_official | 526:c320967f86b9 | 71 | #define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */ |
| mbed_official | 526:c320967f86b9 | 72 | #define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */ |
| mbed_official | 526:c320967f86b9 | 73 | #define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 74 | #define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL /**< Mode REDUCED for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 75 | #define _EMU_CTRL_EMVREG_FULL 0x00000001UL /**< Mode FULL for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 76 | #define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 77 | #define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0) /**< Shifted mode REDUCED for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 78 | #define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0) /**< Shifted mode FULL for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 79 | #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ |
| mbed_official | 526:c320967f86b9 | 80 | #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ |
| mbed_official | 526:c320967f86b9 | 81 | #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ |
| mbed_official | 526:c320967f86b9 | 82 | #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 83 | #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 84 | #define _EMU_CTRL_EM4CTRL_SHIFT 2 /**< Shift value for EMU_EM4CTRL */ |
| mbed_official | 526:c320967f86b9 | 85 | #define _EMU_CTRL_EM4CTRL_MASK 0xCUL /**< Bit mask for EMU_EM4CTRL */ |
| mbed_official | 526:c320967f86b9 | 86 | #define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 87 | #define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ |
| mbed_official | 526:c320967f86b9 | 88 | |
| mbed_official | 526:c320967f86b9 | 89 | /* Bit fields for EMU MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 90 | #define _EMU_MEMCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 91 | #define _EMU_MEMCTRL_MASK 0x00000007UL /**< Mask for EMU_MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 92 | #define _EMU_MEMCTRL_POWERDOWN_SHIFT 0 /**< Shift value for EMU_POWERDOWN */ |
| mbed_official | 526:c320967f86b9 | 93 | #define _EMU_MEMCTRL_POWERDOWN_MASK 0x7UL /**< Bit mask for EMU_POWERDOWN */ |
| mbed_official | 526:c320967f86b9 | 94 | #define _EMU_MEMCTRL_POWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 95 | #define _EMU_MEMCTRL_POWERDOWN_BLK3 0x00000004UL /**< Mode BLK3 for EMU_MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 96 | #define _EMU_MEMCTRL_POWERDOWN_BLK23 0x00000006UL /**< Mode BLK23 for EMU_MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 97 | #define _EMU_MEMCTRL_POWERDOWN_BLK123 0x00000007UL /**< Mode BLK123 for EMU_MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 98 | #define EMU_MEMCTRL_POWERDOWN_DEFAULT (_EMU_MEMCTRL_POWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 99 | #define EMU_MEMCTRL_POWERDOWN_BLK3 (_EMU_MEMCTRL_POWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 100 | #define EMU_MEMCTRL_POWERDOWN_BLK23 (_EMU_MEMCTRL_POWERDOWN_BLK23 << 0) /**< Shifted mode BLK23 for EMU_MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 101 | #define EMU_MEMCTRL_POWERDOWN_BLK123 (_EMU_MEMCTRL_POWERDOWN_BLK123 << 0) /**< Shifted mode BLK123 for EMU_MEMCTRL */ |
| mbed_official | 526:c320967f86b9 | 102 | |
| mbed_official | 526:c320967f86b9 | 103 | /* Bit fields for EMU LOCK */ |
| mbed_official | 526:c320967f86b9 | 104 | #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 105 | #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 106 | #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ |
| mbed_official | 526:c320967f86b9 | 107 | #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ |
| mbed_official | 526:c320967f86b9 | 108 | #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 109 | #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 110 | #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 111 | #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 112 | #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 113 | #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 114 | #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 115 | #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 116 | #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 117 | #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ |
| mbed_official | 526:c320967f86b9 | 118 | |
| mbed_official | 526:c320967f86b9 | 119 | /* Bit fields for EMU AUXCTRL */ |
| mbed_official | 526:c320967f86b9 | 120 | #define _EMU_AUXCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_AUXCTRL */ |
| mbed_official | 526:c320967f86b9 | 121 | #define _EMU_AUXCTRL_MASK 0x00000101UL /**< Mask for EMU_AUXCTRL */ |
| mbed_official | 526:c320967f86b9 | 122 | #define EMU_AUXCTRL_HRCCLR (0x1UL << 0) /**< Hard Reset Cause Clear */ |
| mbed_official | 526:c320967f86b9 | 123 | #define _EMU_AUXCTRL_HRCCLR_SHIFT 0 /**< Shift value for EMU_HRCCLR */ |
| mbed_official | 526:c320967f86b9 | 124 | #define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL /**< Bit mask for EMU_HRCCLR */ |
| mbed_official | 526:c320967f86b9 | 125 | #define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_AUXCTRL */ |
| mbed_official | 526:c320967f86b9 | 126 | #define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */ |
| mbed_official | 526:c320967f86b9 | 127 | #define EMU_AUXCTRL_REDLFXOBOOST (0x1UL << 8) /**< Reduce LFXO Start-up Boost Current */ |
| mbed_official | 526:c320967f86b9 | 128 | #define _EMU_AUXCTRL_REDLFXOBOOST_SHIFT 8 /**< Shift value for EMU_REDLFXOBOOST */ |
| mbed_official | 526:c320967f86b9 | 129 | #define _EMU_AUXCTRL_REDLFXOBOOST_MASK 0x100UL /**< Bit mask for EMU_REDLFXOBOOST */ |
| mbed_official | 526:c320967f86b9 | 130 | #define _EMU_AUXCTRL_REDLFXOBOOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_AUXCTRL */ |
| mbed_official | 526:c320967f86b9 | 131 | #define EMU_AUXCTRL_REDLFXOBOOST_DEFAULT (_EMU_AUXCTRL_REDLFXOBOOST_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_AUXCTRL */ |
| mbed_official | 526:c320967f86b9 | 132 | |
| mbed_official | 526:c320967f86b9 | 133 | /* Bit fields for EMU EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 134 | #define _EMU_EM4CONF_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 135 | #define _EMU_EM4CONF_MASK 0x0001001FUL /**< Mask for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 136 | #define EMU_EM4CONF_VREGEN (0x1UL << 0) /**< EM4 voltage regulator enable */ |
| mbed_official | 526:c320967f86b9 | 137 | #define _EMU_EM4CONF_VREGEN_SHIFT 0 /**< Shift value for EMU_VREGEN */ |
| mbed_official | 526:c320967f86b9 | 138 | #define _EMU_EM4CONF_VREGEN_MASK 0x1UL /**< Bit mask for EMU_VREGEN */ |
| mbed_official | 526:c320967f86b9 | 139 | #define _EMU_EM4CONF_VREGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 140 | #define EMU_EM4CONF_VREGEN_DEFAULT (_EMU_EM4CONF_VREGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 141 | #define EMU_EM4CONF_BURTCWU (0x1UL << 1) /**< Backup RTC EM4 wakeup enable */ |
| mbed_official | 526:c320967f86b9 | 142 | #define _EMU_EM4CONF_BURTCWU_SHIFT 1 /**< Shift value for EMU_BURTCWU */ |
| mbed_official | 526:c320967f86b9 | 143 | #define _EMU_EM4CONF_BURTCWU_MASK 0x2UL /**< Bit mask for EMU_BURTCWU */ |
| mbed_official | 526:c320967f86b9 | 144 | #define _EMU_EM4CONF_BURTCWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 145 | #define EMU_EM4CONF_BURTCWU_DEFAULT (_EMU_EM4CONF_BURTCWU_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 146 | #define _EMU_EM4CONF_OSC_SHIFT 2 /**< Shift value for EMU_OSC */ |
| mbed_official | 526:c320967f86b9 | 147 | #define _EMU_EM4CONF_OSC_MASK 0xCUL /**< Bit mask for EMU_OSC */ |
| mbed_official | 526:c320967f86b9 | 148 | #define _EMU_EM4CONF_OSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 149 | #define _EMU_EM4CONF_OSC_ULFRCO 0x00000000UL /**< Mode ULFRCO for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 150 | #define _EMU_EM4CONF_OSC_LFRCO 0x00000001UL /**< Mode LFRCO for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 151 | #define _EMU_EM4CONF_OSC_LFXO 0x00000002UL /**< Mode LFXO for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 152 | #define EMU_EM4CONF_OSC_DEFAULT (_EMU_EM4CONF_OSC_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 153 | #define EMU_EM4CONF_OSC_ULFRCO (_EMU_EM4CONF_OSC_ULFRCO << 2) /**< Shifted mode ULFRCO for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 154 | #define EMU_EM4CONF_OSC_LFRCO (_EMU_EM4CONF_OSC_LFRCO << 2) /**< Shifted mode LFRCO for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 155 | #define EMU_EM4CONF_OSC_LFXO (_EMU_EM4CONF_OSC_LFXO << 2) /**< Shifted mode LFXO for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 156 | #define EMU_EM4CONF_BUBODRSTDIS (0x1UL << 4) /**< Disable reset from Backup BOD in EM4 */ |
| mbed_official | 526:c320967f86b9 | 157 | #define _EMU_EM4CONF_BUBODRSTDIS_SHIFT 4 /**< Shift value for EMU_BUBODRSTDIS */ |
| mbed_official | 526:c320967f86b9 | 158 | #define _EMU_EM4CONF_BUBODRSTDIS_MASK 0x10UL /**< Bit mask for EMU_BUBODRSTDIS */ |
| mbed_official | 526:c320967f86b9 | 159 | #define _EMU_EM4CONF_BUBODRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 160 | #define EMU_EM4CONF_BUBODRSTDIS_DEFAULT (_EMU_EM4CONF_BUBODRSTDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 161 | #define EMU_EM4CONF_LOCKCONF (0x1UL << 16) /**< EM4 configuration lock enable */ |
| mbed_official | 526:c320967f86b9 | 162 | #define _EMU_EM4CONF_LOCKCONF_SHIFT 16 /**< Shift value for EMU_LOCKCONF */ |
| mbed_official | 526:c320967f86b9 | 163 | #define _EMU_EM4CONF_LOCKCONF_MASK 0x10000UL /**< Bit mask for EMU_LOCKCONF */ |
| mbed_official | 526:c320967f86b9 | 164 | #define _EMU_EM4CONF_LOCKCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 165 | #define EMU_EM4CONF_LOCKCONF_DEFAULT (_EMU_EM4CONF_LOCKCONF_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CONF */ |
| mbed_official | 526:c320967f86b9 | 166 | |
| mbed_official | 526:c320967f86b9 | 167 | /* Bit fields for EMU BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 168 | #define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 169 | #define _EMU_BUCTRL_MASK 0x00000067UL /**< Mask for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 170 | #define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable backup mode */ |
| mbed_official | 526:c320967f86b9 | 171 | #define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ |
| mbed_official | 526:c320967f86b9 | 172 | #define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ |
| mbed_official | 526:c320967f86b9 | 173 | #define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 174 | #define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 175 | #define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable backup mode status export */ |
| mbed_official | 526:c320967f86b9 | 176 | #define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */ |
| mbed_official | 526:c320967f86b9 | 177 | #define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */ |
| mbed_official | 526:c320967f86b9 | 178 | #define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 179 | #define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 180 | #define EMU_BUCTRL_BODCAL (0x1UL << 2) /**< Enable BOD calibration mode */ |
| mbed_official | 526:c320967f86b9 | 181 | #define _EMU_BUCTRL_BODCAL_SHIFT 2 /**< Shift value for EMU_BODCAL */ |
| mbed_official | 526:c320967f86b9 | 182 | #define _EMU_BUCTRL_BODCAL_MASK 0x4UL /**< Bit mask for EMU_BODCAL */ |
| mbed_official | 526:c320967f86b9 | 183 | #define _EMU_BUCTRL_BODCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 184 | #define EMU_BUCTRL_BODCAL_DEFAULT (_EMU_BUCTRL_BODCAL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 185 | #define _EMU_BUCTRL_PROBE_SHIFT 5 /**< Shift value for EMU_PROBE */ |
| mbed_official | 526:c320967f86b9 | 186 | #define _EMU_BUCTRL_PROBE_MASK 0x60UL /**< Bit mask for EMU_PROBE */ |
| mbed_official | 526:c320967f86b9 | 187 | #define _EMU_BUCTRL_PROBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 188 | #define _EMU_BUCTRL_PROBE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 189 | #define _EMU_BUCTRL_PROBE_VDDDREG 0x00000001UL /**< Mode VDDDREG for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 190 | #define _EMU_BUCTRL_PROBE_BUIN 0x00000002UL /**< Mode BUIN for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 191 | #define _EMU_BUCTRL_PROBE_BUOUT 0x00000003UL /**< Mode BUOUT for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 192 | #define EMU_BUCTRL_PROBE_DEFAULT (_EMU_BUCTRL_PROBE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 193 | #define EMU_BUCTRL_PROBE_DISABLE (_EMU_BUCTRL_PROBE_DISABLE << 5) /**< Shifted mode DISABLE for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 194 | #define EMU_BUCTRL_PROBE_VDDDREG (_EMU_BUCTRL_PROBE_VDDDREG << 5) /**< Shifted mode VDDDREG for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 195 | #define EMU_BUCTRL_PROBE_BUIN (_EMU_BUCTRL_PROBE_BUIN << 5) /**< Shifted mode BUIN for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 196 | #define EMU_BUCTRL_PROBE_BUOUT (_EMU_BUCTRL_PROBE_BUOUT << 5) /**< Shifted mode BUOUT for EMU_BUCTRL */ |
| mbed_official | 526:c320967f86b9 | 197 | |
| mbed_official | 526:c320967f86b9 | 198 | /* Bit fields for EMU PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 199 | #define _EMU_PWRCONF_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 200 | #define _EMU_PWRCONF_MASK 0x0000001FUL /**< Mask for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 201 | #define EMU_PWRCONF_VOUTWEAK (0x1UL << 0) /**< BU_VOUT weak enable */ |
| mbed_official | 526:c320967f86b9 | 202 | #define _EMU_PWRCONF_VOUTWEAK_SHIFT 0 /**< Shift value for EMU_VOUTWEAK */ |
| mbed_official | 526:c320967f86b9 | 203 | #define _EMU_PWRCONF_VOUTWEAK_MASK 0x1UL /**< Bit mask for EMU_VOUTWEAK */ |
| mbed_official | 526:c320967f86b9 | 204 | #define _EMU_PWRCONF_VOUTWEAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 205 | #define EMU_PWRCONF_VOUTWEAK_DEFAULT (_EMU_PWRCONF_VOUTWEAK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 206 | #define EMU_PWRCONF_VOUTMED (0x1UL << 1) /**< BU_VOUT medium enable */ |
| mbed_official | 526:c320967f86b9 | 207 | #define _EMU_PWRCONF_VOUTMED_SHIFT 1 /**< Shift value for EMU_VOUTMED */ |
| mbed_official | 526:c320967f86b9 | 208 | #define _EMU_PWRCONF_VOUTMED_MASK 0x2UL /**< Bit mask for EMU_VOUTMED */ |
| mbed_official | 526:c320967f86b9 | 209 | #define _EMU_PWRCONF_VOUTMED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 210 | #define EMU_PWRCONF_VOUTMED_DEFAULT (_EMU_PWRCONF_VOUTMED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 211 | #define EMU_PWRCONF_VOUTSTRONG (0x1UL << 2) /**< BU_VOUT strong enable */ |
| mbed_official | 526:c320967f86b9 | 212 | #define _EMU_PWRCONF_VOUTSTRONG_SHIFT 2 /**< Shift value for EMU_VOUTSTRONG */ |
| mbed_official | 526:c320967f86b9 | 213 | #define _EMU_PWRCONF_VOUTSTRONG_MASK 0x4UL /**< Bit mask for EMU_VOUTSTRONG */ |
| mbed_official | 526:c320967f86b9 | 214 | #define _EMU_PWRCONF_VOUTSTRONG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 215 | #define EMU_PWRCONF_VOUTSTRONG_DEFAULT (_EMU_PWRCONF_VOUTSTRONG_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 216 | #define _EMU_PWRCONF_PWRRES_SHIFT 3 /**< Shift value for EMU_PWRRES */ |
| mbed_official | 526:c320967f86b9 | 217 | #define _EMU_PWRCONF_PWRRES_MASK 0x18UL /**< Bit mask for EMU_PWRRES */ |
| mbed_official | 526:c320967f86b9 | 218 | #define _EMU_PWRCONF_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 219 | #define _EMU_PWRCONF_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 220 | #define _EMU_PWRCONF_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 221 | #define _EMU_PWRCONF_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 222 | #define _EMU_PWRCONF_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 223 | #define EMU_PWRCONF_PWRRES_DEFAULT (_EMU_PWRCONF_PWRRES_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 224 | #define EMU_PWRCONF_PWRRES_RES0 (_EMU_PWRCONF_PWRRES_RES0 << 3) /**< Shifted mode RES0 for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 225 | #define EMU_PWRCONF_PWRRES_RES1 (_EMU_PWRCONF_PWRRES_RES1 << 3) /**< Shifted mode RES1 for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 226 | #define EMU_PWRCONF_PWRRES_RES2 (_EMU_PWRCONF_PWRRES_RES2 << 3) /**< Shifted mode RES2 for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 227 | #define EMU_PWRCONF_PWRRES_RES3 (_EMU_PWRCONF_PWRRES_RES3 << 3) /**< Shifted mode RES3 for EMU_PWRCONF */ |
| mbed_official | 526:c320967f86b9 | 228 | |
| mbed_official | 526:c320967f86b9 | 229 | /* Bit fields for EMU BUINACT */ |
| mbed_official | 526:c320967f86b9 | 230 | #define _EMU_BUINACT_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 231 | #define _EMU_BUINACT_MASK 0x0000007FUL /**< Mask for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 232 | #define _EMU_BUINACT_BUENTHRES_SHIFT 0 /**< Shift value for EMU_BUENTHRES */ |
| mbed_official | 526:c320967f86b9 | 233 | #define _EMU_BUINACT_BUENTHRES_MASK 0x7UL /**< Bit mask for EMU_BUENTHRES */ |
| mbed_official | 526:c320967f86b9 | 234 | #define _EMU_BUINACT_BUENTHRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 235 | #define EMU_BUINACT_BUENTHRES_DEFAULT (_EMU_BUINACT_BUENTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 236 | #define _EMU_BUINACT_BUENRANGE_SHIFT 3 /**< Shift value for EMU_BUENRANGE */ |
| mbed_official | 526:c320967f86b9 | 237 | #define _EMU_BUINACT_BUENRANGE_MASK 0x18UL /**< Bit mask for EMU_BUENRANGE */ |
| mbed_official | 526:c320967f86b9 | 238 | #define _EMU_BUINACT_BUENRANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 239 | #define EMU_BUINACT_BUENRANGE_DEFAULT (_EMU_BUINACT_BUENRANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 240 | #define _EMU_BUINACT_PWRCON_SHIFT 5 /**< Shift value for EMU_PWRCON */ |
| mbed_official | 526:c320967f86b9 | 241 | #define _EMU_BUINACT_PWRCON_MASK 0x60UL /**< Bit mask for EMU_PWRCON */ |
| mbed_official | 526:c320967f86b9 | 242 | #define _EMU_BUINACT_PWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 243 | #define _EMU_BUINACT_PWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 244 | #define _EMU_BUINACT_PWRCON_BUMAIN 0x00000001UL /**< Mode BUMAIN for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 245 | #define _EMU_BUINACT_PWRCON_MAINBU 0x00000002UL /**< Mode MAINBU for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 246 | #define _EMU_BUINACT_PWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 247 | #define EMU_BUINACT_PWRCON_DEFAULT (_EMU_BUINACT_PWRCON_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 248 | #define EMU_BUINACT_PWRCON_NONE (_EMU_BUINACT_PWRCON_NONE << 5) /**< Shifted mode NONE for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 249 | #define EMU_BUINACT_PWRCON_BUMAIN (_EMU_BUINACT_PWRCON_BUMAIN << 5) /**< Shifted mode BUMAIN for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 250 | #define EMU_BUINACT_PWRCON_MAINBU (_EMU_BUINACT_PWRCON_MAINBU << 5) /**< Shifted mode MAINBU for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 251 | #define EMU_BUINACT_PWRCON_NODIODE (_EMU_BUINACT_PWRCON_NODIODE << 5) /**< Shifted mode NODIODE for EMU_BUINACT */ |
| mbed_official | 526:c320967f86b9 | 252 | |
| mbed_official | 526:c320967f86b9 | 253 | /* Bit fields for EMU BUACT */ |
| mbed_official | 526:c320967f86b9 | 254 | #define _EMU_BUACT_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 255 | #define _EMU_BUACT_MASK 0x0000007FUL /**< Mask for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 256 | #define _EMU_BUACT_BUEXTHRES_SHIFT 0 /**< Shift value for EMU_BUEXTHRES */ |
| mbed_official | 526:c320967f86b9 | 257 | #define _EMU_BUACT_BUEXTHRES_MASK 0x7UL /**< Bit mask for EMU_BUEXTHRES */ |
| mbed_official | 526:c320967f86b9 | 258 | #define _EMU_BUACT_BUEXTHRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 259 | #define EMU_BUACT_BUEXTHRES_DEFAULT (_EMU_BUACT_BUEXTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 260 | #define _EMU_BUACT_BUEXRANGE_SHIFT 3 /**< Shift value for EMU_BUEXRANGE */ |
| mbed_official | 526:c320967f86b9 | 261 | #define _EMU_BUACT_BUEXRANGE_MASK 0x18UL /**< Bit mask for EMU_BUEXRANGE */ |
| mbed_official | 526:c320967f86b9 | 262 | #define _EMU_BUACT_BUEXRANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 263 | #define EMU_BUACT_BUEXRANGE_DEFAULT (_EMU_BUACT_BUEXRANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 264 | #define _EMU_BUACT_PWRCON_SHIFT 5 /**< Shift value for EMU_PWRCON */ |
| mbed_official | 526:c320967f86b9 | 265 | #define _EMU_BUACT_PWRCON_MASK 0x60UL /**< Bit mask for EMU_PWRCON */ |
| mbed_official | 526:c320967f86b9 | 266 | #define _EMU_BUACT_PWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 267 | #define _EMU_BUACT_PWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 268 | #define _EMU_BUACT_PWRCON_BUMAIN 0x00000001UL /**< Mode BUMAIN for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 269 | #define _EMU_BUACT_PWRCON_MAINBU 0x00000002UL /**< Mode MAINBU for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 270 | #define _EMU_BUACT_PWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 271 | #define EMU_BUACT_PWRCON_DEFAULT (_EMU_BUACT_PWRCON_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 272 | #define EMU_BUACT_PWRCON_NONE (_EMU_BUACT_PWRCON_NONE << 5) /**< Shifted mode NONE for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 273 | #define EMU_BUACT_PWRCON_BUMAIN (_EMU_BUACT_PWRCON_BUMAIN << 5) /**< Shifted mode BUMAIN for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 274 | #define EMU_BUACT_PWRCON_MAINBU (_EMU_BUACT_PWRCON_MAINBU << 5) /**< Shifted mode MAINBU for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 275 | #define EMU_BUACT_PWRCON_NODIODE (_EMU_BUACT_PWRCON_NODIODE << 5) /**< Shifted mode NODIODE for EMU_BUACT */ |
| mbed_official | 526:c320967f86b9 | 276 | |
| mbed_official | 526:c320967f86b9 | 277 | /* Bit fields for EMU STATUS */ |
| mbed_official | 526:c320967f86b9 | 278 | #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ |
| mbed_official | 526:c320967f86b9 | 279 | #define _EMU_STATUS_MASK 0x00000001UL /**< Mask for EMU_STATUS */ |
| mbed_official | 526:c320967f86b9 | 280 | #define EMU_STATUS_BURDY (0x1UL << 0) /**< Backup mode ready */ |
| mbed_official | 526:c320967f86b9 | 281 | #define _EMU_STATUS_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */ |
| mbed_official | 526:c320967f86b9 | 282 | #define _EMU_STATUS_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */ |
| mbed_official | 526:c320967f86b9 | 283 | #define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| mbed_official | 526:c320967f86b9 | 284 | #define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| mbed_official | 526:c320967f86b9 | 285 | |
| mbed_official | 526:c320967f86b9 | 286 | /* Bit fields for EMU ROUTE */ |
| mbed_official | 526:c320967f86b9 | 287 | #define _EMU_ROUTE_RESETVALUE 0x00000001UL /**< Default value for EMU_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 288 | #define _EMU_ROUTE_MASK 0x00000001UL /**< Mask for EMU_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 289 | #define EMU_ROUTE_BUVINPEN (0x1UL << 0) /**< BU_VIN Pin Enable */ |
| mbed_official | 526:c320967f86b9 | 290 | #define _EMU_ROUTE_BUVINPEN_SHIFT 0 /**< Shift value for EMU_BUVINPEN */ |
| mbed_official | 526:c320967f86b9 | 291 | #define _EMU_ROUTE_BUVINPEN_MASK 0x1UL /**< Bit mask for EMU_BUVINPEN */ |
| mbed_official | 526:c320967f86b9 | 292 | #define _EMU_ROUTE_BUVINPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 293 | #define EMU_ROUTE_BUVINPEN_DEFAULT (_EMU_ROUTE_BUVINPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_ROUTE */ |
| mbed_official | 526:c320967f86b9 | 294 | |
| mbed_official | 526:c320967f86b9 | 295 | /* Bit fields for EMU IF */ |
| mbed_official | 526:c320967f86b9 | 296 | #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ |
| mbed_official | 526:c320967f86b9 | 297 | #define _EMU_IF_MASK 0x00000001UL /**< Mask for EMU_IF */ |
| mbed_official | 526:c320967f86b9 | 298 | #define EMU_IF_BURDY (0x1UL << 0) /**< Backup functionality ready Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 299 | #define _EMU_IF_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */ |
| mbed_official | 526:c320967f86b9 | 300 | #define _EMU_IF_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */ |
| mbed_official | 526:c320967f86b9 | 301 | #define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| mbed_official | 526:c320967f86b9 | 302 | #define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ |
| mbed_official | 526:c320967f86b9 | 303 | |
| mbed_official | 526:c320967f86b9 | 304 | /* Bit fields for EMU IFS */ |
| mbed_official | 526:c320967f86b9 | 305 | #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ |
| mbed_official | 526:c320967f86b9 | 306 | #define _EMU_IFS_MASK 0x00000001UL /**< Mask for EMU_IFS */ |
| mbed_official | 526:c320967f86b9 | 307 | #define EMU_IFS_BURDY (0x1UL << 0) /**< Set Backup functionality ready Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 308 | #define _EMU_IFS_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */ |
| mbed_official | 526:c320967f86b9 | 309 | #define _EMU_IFS_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */ |
| mbed_official | 526:c320967f86b9 | 310 | #define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| mbed_official | 526:c320967f86b9 | 311 | #define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ |
| mbed_official | 526:c320967f86b9 | 312 | |
| mbed_official | 526:c320967f86b9 | 313 | /* Bit fields for EMU IFC */ |
| mbed_official | 526:c320967f86b9 | 314 | #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ |
| mbed_official | 526:c320967f86b9 | 315 | #define _EMU_IFC_MASK 0x00000001UL /**< Mask for EMU_IFC */ |
| mbed_official | 526:c320967f86b9 | 316 | #define EMU_IFC_BURDY (0x1UL << 0) /**< Clear Backup functionality ready Interrupt Flag */ |
| mbed_official | 526:c320967f86b9 | 317 | #define _EMU_IFC_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */ |
| mbed_official | 526:c320967f86b9 | 318 | #define _EMU_IFC_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */ |
| mbed_official | 526:c320967f86b9 | 319 | #define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| mbed_official | 526:c320967f86b9 | 320 | #define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ |
| mbed_official | 526:c320967f86b9 | 321 | |
| mbed_official | 526:c320967f86b9 | 322 | /* Bit fields for EMU IEN */ |
| mbed_official | 526:c320967f86b9 | 323 | #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ |
| mbed_official | 526:c320967f86b9 | 324 | #define _EMU_IEN_MASK 0x00000001UL /**< Mask for EMU_IEN */ |
| mbed_official | 526:c320967f86b9 | 325 | #define EMU_IEN_BURDY (0x1UL << 0) /**< Backup functionality ready Interrupt Enable */ |
| mbed_official | 526:c320967f86b9 | 326 | #define _EMU_IEN_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */ |
| mbed_official | 526:c320967f86b9 | 327 | #define _EMU_IEN_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */ |
| mbed_official | 526:c320967f86b9 | 328 | #define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| mbed_official | 526:c320967f86b9 | 329 | #define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ |
| mbed_official | 526:c320967f86b9 | 330 | |
| mbed_official | 526:c320967f86b9 | 331 | /* Bit fields for EMU BUBODBUVINCAL */ |
| mbed_official | 526:c320967f86b9 | 332 | #define _EMU_BUBODBUVINCAL_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUBODBUVINCAL */ |
| mbed_official | 526:c320967f86b9 | 333 | #define _EMU_BUBODBUVINCAL_MASK 0x0000001FUL /**< Mask for EMU_BUBODBUVINCAL */ |
| mbed_official | 526:c320967f86b9 | 334 | #define _EMU_BUBODBUVINCAL_THRES_SHIFT 0 /**< Shift value for EMU_THRES */ |
| mbed_official | 526:c320967f86b9 | 335 | #define _EMU_BUBODBUVINCAL_THRES_MASK 0x7UL /**< Bit mask for EMU_THRES */ |
| mbed_official | 526:c320967f86b9 | 336 | #define _EMU_BUBODBUVINCAL_THRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUBODBUVINCAL */ |
| mbed_official | 526:c320967f86b9 | 337 | #define EMU_BUBODBUVINCAL_THRES_DEFAULT (_EMU_BUBODBUVINCAL_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUBODBUVINCAL */ |
| mbed_official | 526:c320967f86b9 | 338 | #define _EMU_BUBODBUVINCAL_RANGE_SHIFT 3 /**< Shift value for EMU_RANGE */ |
| mbed_official | 526:c320967f86b9 | 339 | #define _EMU_BUBODBUVINCAL_RANGE_MASK 0x18UL /**< Bit mask for EMU_RANGE */ |
| mbed_official | 526:c320967f86b9 | 340 | #define _EMU_BUBODBUVINCAL_RANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUBODBUVINCAL */ |
| mbed_official | 526:c320967f86b9 | 341 | #define EMU_BUBODBUVINCAL_RANGE_DEFAULT (_EMU_BUBODBUVINCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODBUVINCAL */ |
| mbed_official | 526:c320967f86b9 | 342 | |
| mbed_official | 526:c320967f86b9 | 343 | /* Bit fields for EMU BUBODUNREGCAL */ |
| mbed_official | 526:c320967f86b9 | 344 | #define _EMU_BUBODUNREGCAL_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUBODUNREGCAL */ |
| mbed_official | 526:c320967f86b9 | 345 | #define _EMU_BUBODUNREGCAL_MASK 0x0000001FUL /**< Mask for EMU_BUBODUNREGCAL */ |
| mbed_official | 526:c320967f86b9 | 346 | #define _EMU_BUBODUNREGCAL_THRES_SHIFT 0 /**< Shift value for EMU_THRES */ |
| mbed_official | 526:c320967f86b9 | 347 | #define _EMU_BUBODUNREGCAL_THRES_MASK 0x7UL /**< Bit mask for EMU_THRES */ |
| mbed_official | 526:c320967f86b9 | 348 | #define _EMU_BUBODUNREGCAL_THRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUBODUNREGCAL */ |
| mbed_official | 526:c320967f86b9 | 349 | #define EMU_BUBODUNREGCAL_THRES_DEFAULT (_EMU_BUBODUNREGCAL_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */ |
| mbed_official | 526:c320967f86b9 | 350 | #define _EMU_BUBODUNREGCAL_RANGE_SHIFT 3 /**< Shift value for EMU_RANGE */ |
| mbed_official | 526:c320967f86b9 | 351 | #define _EMU_BUBODUNREGCAL_RANGE_MASK 0x18UL /**< Bit mask for EMU_RANGE */ |
| mbed_official | 526:c320967f86b9 | 352 | #define _EMU_BUBODUNREGCAL_RANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUBODUNREGCAL */ |
| mbed_official | 526:c320967f86b9 | 353 | #define EMU_BUBODUNREGCAL_RANGE_DEFAULT (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */ |
| mbed_official | 526:c320967f86b9 | 354 | |
| mbed_official | 526:c320967f86b9 | 355 | /** @} End of group EFM32GG_EMU */ |
| mbed_official | 526:c320967f86b9 | 356 | |
| mbed_official | 526:c320967f86b9 | 357 |