zain aftab / mbed-src

mbed library sources

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC13XX/i2c_api.c@636:a11c0372f0ba, 2015-09-30 (annotated)

Committer:
mbed_official
Date:
Wed Sep 30 17:00:09 2015 +0100
Revision:
636:a11c0372f0ba
Parent:
285:31249416b6f9 
Synchronized with git revision d29c98dae61be0946ddf3a3c641c7726056f9452



Full URL: https://github.com/mbedmicro/mbed/commit/d29c98dae61be0946ddf3a3c641c7726056f9452/



Added support for SAMW25

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 13:0645d8841f51 1 /* mbed Microcontroller Library
bogdanm 13:0645d8841f51 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 13:0645d8841f51 3 *
bogdanm 13:0645d8841f51 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 13:0645d8841f51 5 * you may not use this file except in compliance with the License.
bogdanm 13:0645d8841f51 6 * You may obtain a copy of the License at
bogdanm 13:0645d8841f51 7 *
bogdanm 13:0645d8841f51 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 13:0645d8841f51 9 *
bogdanm 13:0645d8841f51 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 13:0645d8841f51 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 13:0645d8841f51 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 13:0645d8841f51 13 * See the License for the specific language governing permissions and
bogdanm 13:0645d8841f51 14 * limitations under the License.
bogdanm 13:0645d8841f51 15 */
mbed_official 227:7bd0639b8911 16 #include "mbed_assert.h"
bogdanm 13:0645d8841f51 17 #include "i2c_api.h"
bogdanm 13:0645d8841f51 18 #include "cmsis.h"
bogdanm 13:0645d8841f51 19 #include "pinmap.h"
mbed_official 285:31249416b6f9 20 #include "mbed_error.h"
bogdanm 13:0645d8841f51 21
bogdanm 13:0645d8841f51 22 static const PinMap PinMap_I2C_SDA[] = {
bogdanm 13:0645d8841f51 23 {P0_5, I2C_0, 1},
bogdanm 13:0645d8841f51 24 {NC , NC , 0}
bogdanm 13:0645d8841f51 25 };
bogdanm 13:0645d8841f51 26
bogdanm 13:0645d8841f51 27 static const PinMap PinMap_I2C_SCL[] = {
bogdanm 13:0645d8841f51 28 {P0_4, I2C_0, 1},
bogdanm 13:0645d8841f51 29 {NC , NC, 0}
bogdanm 13:0645d8841f51 30 };
bogdanm 13:0645d8841f51 31
bogdanm 13:0645d8841f51 32 #define I2C_CONSET(x) (x->i2c->CONSET)
bogdanm 13:0645d8841f51 33 #define I2C_CONCLR(x) (x->i2c->CONCLR)
bogdanm 13:0645d8841f51 34 #define I2C_STAT(x) (x->i2c->STAT)
bogdanm 13:0645d8841f51 35 #define I2C_DAT(x) (x->i2c->DAT)
bogdanm 13:0645d8841f51 36 #define I2C_SCLL(x, val) (x->i2c->SCLL = val)
bogdanm 13:0645d8841f51 37 #define I2C_SCLH(x, val) (x->i2c->SCLH = val)
bogdanm 13:0645d8841f51 38
bogdanm 13:0645d8841f51 39 static const uint32_t I2C_addr_offset[2][4] = {
bogdanm 13:0645d8841f51 40 {0x0C, 0x20, 0x24, 0x28},
bogdanm 13:0645d8841f51 41 {0x30, 0x34, 0x38, 0x3C}
bogdanm 13:0645d8841f51 42 };
bogdanm 13:0645d8841f51 43
bogdanm 13:0645d8841f51 44 static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
bogdanm 13:0645d8841f51 45 I2C_CONCLR(obj) = (start << 5)
bogdanm 13:0645d8841f51 46 | (stop << 4)
bogdanm 13:0645d8841f51 47 | (interrupt << 3)
bogdanm 13:0645d8841f51 48 | (acknowledge << 2);
bogdanm 13:0645d8841f51 49 }
bogdanm 13:0645d8841f51 50
bogdanm 13:0645d8841f51 51 static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
bogdanm 13:0645d8841f51 52 I2C_CONSET(obj) = (start << 5)
bogdanm 13:0645d8841f51 53 | (stop << 4)
bogdanm 13:0645d8841f51 54 | (interrupt << 3)
bogdanm 13:0645d8841f51 55 | (acknowledge << 2);
bogdanm 13:0645d8841f51 56 }
bogdanm 13:0645d8841f51 57
bogdanm 13:0645d8841f51 58 // Clear the Serial Interrupt (SI)
bogdanm 13:0645d8841f51 59 static inline void i2c_clear_SI(i2c_t *obj) {
bogdanm 13:0645d8841f51 60 i2c_conclr(obj, 0, 0, 1, 0);
bogdanm 13:0645d8841f51 61 }
bogdanm 13:0645d8841f51 62
bogdanm 13:0645d8841f51 63 static inline int i2c_status(i2c_t *obj) {
bogdanm 13:0645d8841f51 64 return I2C_STAT(obj);
bogdanm 13:0645d8841f51 65 }
bogdanm 13:0645d8841f51 66
bogdanm 13:0645d8841f51 67 // Wait until the Serial Interrupt (SI) is set
bogdanm 13:0645d8841f51 68 static int i2c_wait_SI(i2c_t *obj) {
bogdanm 13:0645d8841f51 69 int timeout = 0;
bogdanm 13:0645d8841f51 70 while (!(I2C_CONSET(obj) & (1 << 3))) {
bogdanm 13:0645d8841f51 71 timeout++;
bogdanm 13:0645d8841f51 72 if (timeout > 100000) return -1;
bogdanm 13:0645d8841f51 73 }
bogdanm 13:0645d8841f51 74 return 0;
bogdanm 13:0645d8841f51 75 }
bogdanm 13:0645d8841f51 76
bogdanm 13:0645d8841f51 77 static inline void i2c_interface_enable(i2c_t *obj) {
bogdanm 13:0645d8841f51 78 I2C_CONSET(obj) = 0x40;
bogdanm 13:0645d8841f51 79 }
bogdanm 13:0645d8841f51 80
bogdanm 13:0645d8841f51 81 static inline void i2c_power_enable(i2c_t *obj) {
bogdanm 13:0645d8841f51 82 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5);
bogdanm 13:0645d8841f51 83 LPC_SYSCON->PRESETCTRL |= 1 << 1;
bogdanm 13:0645d8841f51 84 }
bogdanm 13:0645d8841f51 85
bogdanm 13:0645d8841f51 86 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
bogdanm 13:0645d8841f51 87 // determine the SPI to use
bogdanm 13:0645d8841f51 88 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
bogdanm 13:0645d8841f51 89 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
bogdanm 13:0645d8841f51 90 obj->i2c = (LPC_I2C_Type *)pinmap_merge(i2c_sda, i2c_scl);
mbed_official 227:7bd0639b8911 91 MBED_ASSERT((int)obj->i2c != NC);
bogdanm 13:0645d8841f51 92
bogdanm 13:0645d8841f51 93 // enable power
bogdanm 13:0645d8841f51 94 i2c_power_enable(obj);
bogdanm 13:0645d8841f51 95
bogdanm 13:0645d8841f51 96 // set default frequency at 100k
bogdanm 13:0645d8841f51 97 i2c_frequency(obj, 100000);
bogdanm 13:0645d8841f51 98 i2c_conclr(obj, 1, 1, 1, 1);
bogdanm 13:0645d8841f51 99 i2c_interface_enable(obj);
bogdanm 13:0645d8841f51 100
bogdanm 13:0645d8841f51 101 pinmap_pinout(sda, PinMap_I2C_SDA);
bogdanm 13:0645d8841f51 102 pinmap_pinout(scl, PinMap_I2C_SCL);
bogdanm 13:0645d8841f51 103 }
bogdanm 13:0645d8841f51 104
bogdanm 13:0645d8841f51 105 inline int i2c_start(i2c_t *obj) {
bogdanm 13:0645d8841f51 106 int status = 0;
bogdanm 13:0645d8841f51 107 // 8.1 Before master mode can be entered, I2CON must be initialised to:
bogdanm 13:0645d8841f51 108 // - I2EN STA STO SI AA - -
bogdanm 13:0645d8841f51 109 // - 1 0 0 0 x - -
bogdanm 13:0645d8841f51 110 // if AA = 0, it can't enter slave mode
bogdanm 13:0645d8841f51 111 i2c_conclr(obj, 1, 1, 1, 1);
bogdanm 13:0645d8841f51 112
bogdanm 13:0645d8841f51 113 // The master mode may now be entered by setting the STA bit
bogdanm 13:0645d8841f51 114 // this will generate a start condition when the bus becomes free
bogdanm 13:0645d8841f51 115 i2c_conset(obj, 1, 0, 0, 1);
bogdanm 13:0645d8841f51 116
bogdanm 13:0645d8841f51 117 i2c_wait_SI(obj);
bogdanm 13:0645d8841f51 118 status = i2c_status(obj);
bogdanm 13:0645d8841f51 119
bogdanm 13:0645d8841f51 120 // Clear start bit now transmitted, and interrupt bit
bogdanm 13:0645d8841f51 121 i2c_conclr(obj, 1, 0, 0, 0);
bogdanm 13:0645d8841f51 122 return status;
bogdanm 13:0645d8841f51 123 }
bogdanm 13:0645d8841f51 124
bogdanm 13:0645d8841f51 125 inline int i2c_stop(i2c_t *obj) {
bogdanm 13:0645d8841f51 126 int timeout = 0;
bogdanm 13:0645d8841f51 127
bogdanm 13:0645d8841f51 128 // write the stop bit
bogdanm 13:0645d8841f51 129 i2c_conset(obj, 0, 1, 0, 0);
bogdanm 13:0645d8841f51 130 i2c_clear_SI(obj);
bogdanm 13:0645d8841f51 131
bogdanm 13:0645d8841f51 132 // wait for STO bit to reset
bogdanm 13:0645d8841f51 133 while(I2C_CONSET(obj) & (1 << 4)) {
bogdanm 13:0645d8841f51 134 timeout ++;
bogdanm 13:0645d8841f51 135 if (timeout > 100000) return 1;
bogdanm 13:0645d8841f51 136 }
bogdanm 13:0645d8841f51 137
bogdanm 13:0645d8841f51 138 return 0;
bogdanm 13:0645d8841f51 139 }
bogdanm 13:0645d8841f51 140
bogdanm 13:0645d8841f51 141
bogdanm 13:0645d8841f51 142 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
bogdanm 13:0645d8841f51 143 // write the data
bogdanm 13:0645d8841f51 144 I2C_DAT(obj) = value;
bogdanm 13:0645d8841f51 145
bogdanm 13:0645d8841f51 146 // clear SI to init a send
bogdanm 13:0645d8841f51 147 i2c_clear_SI(obj);
bogdanm 13:0645d8841f51 148
bogdanm 13:0645d8841f51 149 // wait and return status
bogdanm 13:0645d8841f51 150 i2c_wait_SI(obj);
bogdanm 13:0645d8841f51 151 return i2c_status(obj);
bogdanm 13:0645d8841f51 152 }
bogdanm 13:0645d8841f51 153
bogdanm 13:0645d8841f51 154 static inline int i2c_do_read(i2c_t *obj, int last) {
bogdanm 13:0645d8841f51 155 // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
bogdanm 13:0645d8841f51 156 if (last) {
bogdanm 13:0645d8841f51 157 i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
bogdanm 13:0645d8841f51 158 } else {
bogdanm 13:0645d8841f51 159 i2c_conset(obj, 0, 0, 0, 1); // send a ACK
bogdanm 13:0645d8841f51 160 }
bogdanm 13:0645d8841f51 161
bogdanm 13:0645d8841f51 162 // accept byte
bogdanm 13:0645d8841f51 163 i2c_clear_SI(obj);
bogdanm 13:0645d8841f51 164
bogdanm 13:0645d8841f51 165 // wait for it to arrive
bogdanm 13:0645d8841f51 166 i2c_wait_SI(obj);
bogdanm 13:0645d8841f51 167
bogdanm 13:0645d8841f51 168 // return the data
bogdanm 13:0645d8841f51 169 return (I2C_DAT(obj) & 0xFF);
bogdanm 13:0645d8841f51 170 }
bogdanm 13:0645d8841f51 171
bogdanm 13:0645d8841f51 172 void i2c_frequency(i2c_t *obj, int hz) {
bogdanm 13:0645d8841f51 173 // No peripheral clock divider on the M0
bogdanm 13:0645d8841f51 174 uint32_t PCLK = SystemCoreClock;
bogdanm 13:0645d8841f51 175
bogdanm 13:0645d8841f51 176 uint32_t pulse = PCLK / (hz * 2);
bogdanm 13:0645d8841f51 177
bogdanm 13:0645d8841f51 178 // I2C Rate
bogdanm 13:0645d8841f51 179 I2C_SCLL(obj, pulse);
bogdanm 13:0645d8841f51 180 I2C_SCLH(obj, pulse);
bogdanm 13:0645d8841f51 181 }
bogdanm 13:0645d8841f51 182
bogdanm 13:0645d8841f51 183 // The I2C does a read or a write as a whole operation
bogdanm 13:0645d8841f51 184 // There are two types of error conditions it can encounter
bogdanm 13:0645d8841f51 185 // 1) it can not obtain the bus
bogdanm 13:0645d8841f51 186 // 2) it gets error responses at part of the transmission
bogdanm 13:0645d8841f51 187 //
bogdanm 13:0645d8841f51 188 // We tackle them as follows:
bogdanm 13:0645d8841f51 189 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
bogdanm 13:0645d8841f51 190 // which basically turns it in to a 2)
bogdanm 13:0645d8841f51 191 // 2) on error, we use the standard error mechanisms to report/debug
bogdanm 13:0645d8841f51 192 //
bogdanm 13:0645d8841f51 193 // Therefore an I2C transaction should always complete. If it doesn't it is usually
bogdanm 13:0645d8841f51 194 // because something is setup wrong (e.g. wiring), and we don't need to programatically
bogdanm 13:0645d8841f51 195 // check for that
bogdanm 13:0645d8841f51 196
bogdanm 13:0645d8841f51 197 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
bogdanm 13:0645d8841f51 198 int count, status;
bogdanm 13:0645d8841f51 199
bogdanm 13:0645d8841f51 200 status = i2c_start(obj);
bogdanm 13:0645d8841f51 201
bogdanm 13:0645d8841f51 202 if ((status != 0x10) && (status != 0x08)) {
bogdanm 13:0645d8841f51 203 i2c_stop(obj);
bogdanm 13:0645d8841f51 204 return I2C_ERROR_BUS_BUSY;
bogdanm 13:0645d8841f51 205 }
bogdanm 13:0645d8841f51 206
bogdanm 13:0645d8841f51 207 status = i2c_do_write(obj, (address | 0x01), 1);
bogdanm 13:0645d8841f51 208 if (status != 0x40) {
bogdanm 13:0645d8841f51 209 i2c_stop(obj);
bogdanm 13:0645d8841f51 210 return I2C_ERROR_NO_SLAVE;
bogdanm 13:0645d8841f51 211 }
bogdanm 13:0645d8841f51 212
bogdanm 13:0645d8841f51 213 // Read in all except last byte
bogdanm 13:0645d8841f51 214 for (count = 0; count < (length - 1); count++) {
bogdanm 13:0645d8841f51 215 int value = i2c_do_read(obj, 0);
bogdanm 13:0645d8841f51 216 status = i2c_status(obj);
bogdanm 13:0645d8841f51 217 if (status != 0x50) {
bogdanm 13:0645d8841f51 218 i2c_stop(obj);
bogdanm 13:0645d8841f51 219 return count;
bogdanm 13:0645d8841f51 220 }
bogdanm 13:0645d8841f51 221 data[count] = (char) value;
bogdanm 13:0645d8841f51 222 }
bogdanm 13:0645d8841f51 223
bogdanm 13:0645d8841f51 224 // read in last byte
bogdanm 13:0645d8841f51 225 int value = i2c_do_read(obj, 1);
bogdanm 13:0645d8841f51 226 status = i2c_status(obj);
bogdanm 13:0645d8841f51 227 if (status != 0x58) {
bogdanm 13:0645d8841f51 228 i2c_stop(obj);
bogdanm 13:0645d8841f51 229 return length - 1;
bogdanm 13:0645d8841f51 230 }
bogdanm 13:0645d8841f51 231
bogdanm 13:0645d8841f51 232 data[count] = (char) value;
bogdanm 13:0645d8841f51 233
bogdanm 13:0645d8841f51 234 // If not repeated start, send stop.
bogdanm 13:0645d8841f51 235 if (stop) {
bogdanm 13:0645d8841f51 236 i2c_stop(obj);
bogdanm 13:0645d8841f51 237 }
bogdanm 13:0645d8841f51 238
bogdanm 13:0645d8841f51 239 return length;
bogdanm 13:0645d8841f51 240 }
bogdanm 13:0645d8841f51 241
bogdanm 13:0645d8841f51 242 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
bogdanm 13:0645d8841f51 243 int i, status;
bogdanm 13:0645d8841f51 244
bogdanm 13:0645d8841f51 245 status = i2c_start(obj);
bogdanm 13:0645d8841f51 246
bogdanm 13:0645d8841f51 247 if ((status != 0x10) && (status != 0x08)) {
bogdanm 13:0645d8841f51 248 i2c_stop(obj);
bogdanm 13:0645d8841f51 249 return I2C_ERROR_BUS_BUSY;
bogdanm 13:0645d8841f51 250 }
bogdanm 13:0645d8841f51 251
bogdanm 13:0645d8841f51 252 status = i2c_do_write(obj, (address & 0xFE), 1);
bogdanm 13:0645d8841f51 253 if (status != 0x18) {
bogdanm 13:0645d8841f51 254 i2c_stop(obj);
bogdanm 13:0645d8841f51 255 return I2C_ERROR_NO_SLAVE;
bogdanm 13:0645d8841f51 256 }
bogdanm 13:0645d8841f51 257
bogdanm 13:0645d8841f51 258 for (i=0; i<length; i++) {
bogdanm 13:0645d8841f51 259 status = i2c_do_write(obj, data[i], 0);
bogdanm 13:0645d8841f51 260 if(status != 0x28) {
bogdanm 13:0645d8841f51 261 i2c_stop(obj);
bogdanm 13:0645d8841f51 262 return i;
bogdanm 13:0645d8841f51 263 }
bogdanm 13:0645d8841f51 264 }
bogdanm 13:0645d8841f51 265
bogdanm 13:0645d8841f51 266 // clearing the serial interrupt here might cause an unintended rewrite of the last byte
bogdanm 13:0645d8841f51 267 // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
bogdanm 13:0645d8841f51 268 // i2c_clear_SI(obj);
bogdanm 13:0645d8841f51 269
bogdanm 13:0645d8841f51 270 // If not repeated start, send stop.
bogdanm 13:0645d8841f51 271 if (stop) {
bogdanm 13:0645d8841f51 272 i2c_stop(obj);
bogdanm 13:0645d8841f51 273 }
bogdanm 13:0645d8841f51 274
bogdanm 13:0645d8841f51 275 return length;
bogdanm 13:0645d8841f51 276 }
bogdanm 13:0645d8841f51 277
bogdanm 13:0645d8841f51 278 void i2c_reset(i2c_t *obj) {
bogdanm 13:0645d8841f51 279 i2c_stop(obj);
bogdanm 13:0645d8841f51 280 }
bogdanm 13:0645d8841f51 281
bogdanm 13:0645d8841f51 282 int i2c_byte_read(i2c_t *obj, int last) {
bogdanm 13:0645d8841f51 283 return (i2c_do_read(obj, last) & 0xFF);
bogdanm 13:0645d8841f51 284 }
bogdanm 13:0645d8841f51 285
bogdanm 13:0645d8841f51 286 int i2c_byte_write(i2c_t *obj, int data) {
bogdanm 13:0645d8841f51 287 int ack;
bogdanm 13:0645d8841f51 288 int status = i2c_do_write(obj, (data & 0xFF), 0);
bogdanm 13:0645d8841f51 289
bogdanm 13:0645d8841f51 290 switch(status) {
bogdanm 13:0645d8841f51 291 case 0x18: case 0x28: // Master transmit ACKs
bogdanm 13:0645d8841f51 292 ack = 1;
bogdanm 13:0645d8841f51 293 break;
bogdanm 13:0645d8841f51 294 case 0x40: // Master receive address transmitted ACK
bogdanm 13:0645d8841f51 295 ack = 1;
bogdanm 13:0645d8841f51 296 break;
bogdanm 13:0645d8841f51 297 case 0xB8: // Slave transmit ACK
bogdanm 13:0645d8841f51 298 ack = 1;
bogdanm 13:0645d8841f51 299 break;
bogdanm 13:0645d8841f51 300 default:
bogdanm 13:0645d8841f51 301 ack = 0;
bogdanm 13:0645d8841f51 302 break;
bogdanm 13:0645d8841f51 303 }
bogdanm 13:0645d8841f51 304
bogdanm 13:0645d8841f51 305 return ack;
bogdanm 13:0645d8841f51 306 }
bogdanm 13:0645d8841f51 307
bogdanm 13:0645d8841f51 308 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
bogdanm 13:0645d8841f51 309 if (enable_slave != 0) {
bogdanm 13:0645d8841f51 310 i2c_conclr(obj, 1, 1, 1, 0);
bogdanm 13:0645d8841f51 311 i2c_conset(obj, 0, 0, 0, 1);
bogdanm 13:0645d8841f51 312 } else {
bogdanm 13:0645d8841f51 313 i2c_conclr(obj, 1, 1, 1, 1);
bogdanm 13:0645d8841f51 314 }
bogdanm 13:0645d8841f51 315 }
bogdanm 13:0645d8841f51 316
bogdanm 13:0645d8841f51 317 int i2c_slave_receive(i2c_t *obj) {
bogdanm 13:0645d8841f51 318 int status;
bogdanm 13:0645d8841f51 319 int retval;
bogdanm 13:0645d8841f51 320
bogdanm 13:0645d8841f51 321 status = i2c_status(obj);
bogdanm 13:0645d8841f51 322 switch(status) {
bogdanm 13:0645d8841f51 323 case 0x60: retval = 3; break;
bogdanm 13:0645d8841f51 324 case 0x70: retval = 2; break;
bogdanm 13:0645d8841f51 325 case 0xA8: retval = 1; break;
bogdanm 13:0645d8841f51 326 default : retval = 0; break;
bogdanm 13:0645d8841f51 327 }
bogdanm 13:0645d8841f51 328
bogdanm 13:0645d8841f51 329 return(retval);
bogdanm 13:0645d8841f51 330 }
bogdanm 13:0645d8841f51 331
bogdanm 13:0645d8841f51 332 int i2c_slave_read(i2c_t *obj, char *data, int length) {
bogdanm 13:0645d8841f51 333 int count = 0;
bogdanm 13:0645d8841f51 334 int status;
bogdanm 13:0645d8841f51 335
bogdanm 13:0645d8841f51 336 do {
bogdanm 13:0645d8841f51 337 i2c_clear_SI(obj);
bogdanm 13:0645d8841f51 338 i2c_wait_SI(obj);
bogdanm 13:0645d8841f51 339 status = i2c_status(obj);
bogdanm 13:0645d8841f51 340 if((status == 0x80) || (status == 0x90)) {
bogdanm 13:0645d8841f51 341 data[count] = I2C_DAT(obj) & 0xFF;
bogdanm 13:0645d8841f51 342 }
bogdanm 13:0645d8841f51 343 count++;
bogdanm 13:0645d8841f51 344 } while (((status == 0x80) || (status == 0x90) ||
bogdanm 13:0645d8841f51 345 (status == 0x060) || (status == 0x70)) && (count < length));
bogdanm 13:0645d8841f51 346
bogdanm 13:0645d8841f51 347 if(status != 0xA0) {
bogdanm 13:0645d8841f51 348 i2c_stop(obj);
bogdanm 13:0645d8841f51 349 }
bogdanm 13:0645d8841f51 350
bogdanm 13:0645d8841f51 351 i2c_clear_SI(obj);
bogdanm 13:0645d8841f51 352
bogdanm 13:0645d8841f51 353 return count;
bogdanm 13:0645d8841f51 354 }
bogdanm 13:0645d8841f51 355
bogdanm 13:0645d8841f51 356 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
bogdanm 13:0645d8841f51 357 int count = 0;
bogdanm 13:0645d8841f51 358 int status;
bogdanm 13:0645d8841f51 359
bogdanm 13:0645d8841f51 360 if(length <= 0) {
bogdanm 13:0645d8841f51 361 return(0);
bogdanm 13:0645d8841f51 362 }
bogdanm 13:0645d8841f51 363
bogdanm 13:0645d8841f51 364 do {
bogdanm 13:0645d8841f51 365 status = i2c_do_write(obj, data[count], 0);
bogdanm 13:0645d8841f51 366 count++;
bogdanm 13:0645d8841f51 367 } while ((count < length) && (status == 0xB8));
bogdanm 13:0645d8841f51 368
bogdanm 13:0645d8841f51 369 if((status != 0xC0) && (status != 0xC8)) {
bogdanm 13:0645d8841f51 370 i2c_stop(obj);
bogdanm 13:0645d8841f51 371 }
bogdanm 13:0645d8841f51 372
bogdanm 13:0645d8841f51 373 i2c_clear_SI(obj);
bogdanm 13:0645d8841f51 374
bogdanm 13:0645d8841f51 375 return(count);
bogdanm 13:0645d8841f51 376 }
bogdanm 13:0645d8841f51 377
bogdanm 13:0645d8841f51 378 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
bogdanm 13:0645d8841f51 379 uint32_t addr;
bogdanm 13:0645d8841f51 380
bogdanm 13:0645d8841f51 381 if ((idx >= 0) && (idx <= 3)) {
bogdanm 13:0645d8841f51 382 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
bogdanm 13:0645d8841f51 383 *((uint32_t *) addr) = address & 0xFF;
bogdanm 13:0645d8841f51 384 }
bogdanm 13:0645d8841f51 385 }