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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.c@636:a11c0372f0ba, 2015-09-30 (annotated)

Committer:
mbed_official
Date:
Wed Sep 30 17:00:09 2015 +0100
Revision:
636:a11c0372f0ba
Parent:
490:119543c9f674 
Synchronized with git revision d29c98dae61be0946ddf3a3c641c7726056f9452



Full URL: https://github.com/mbedmicro/mbed/commit/d29c98dae61be0946ddf3a3c641c7726056f9452/



Added support for SAMW25

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 376:cb4d9db17537 1 /**
mbed_official 376:cb4d9db17537 2 ******************************************************************************
mbed_official 376:cb4d9db17537 3 * @file stm32l0xx_hal_tim.c
mbed_official 376:cb4d9db17537 4 * @author MCD Application Team
mbed_official 490:119543c9f674 5 * @version V1.2.0
mbed_official 490:119543c9f674 6 * @date 06-February-2015
mbed_official 376:cb4d9db17537 7 * @brief TIM HAL module driver.
mbed_official 376:cb4d9db17537 8 * @brief This file provides firmware functions to manage the following
mbed_official 376:cb4d9db17537 9 * functionalities of the Timer (TIM) peripheral:
mbed_official 490:119543c9f674 10 * + Timer Base Initialization
mbed_official 490:119543c9f674 11 * + Timer Base Start
mbed_official 490:119543c9f674 12 * + Timer Base Start Interruption
mbed_official 490:119543c9f674 13 * + Timer Base Start DMA
mbed_official 490:119543c9f674 14 * + Timer Output Compare/PWM Initialization
mbed_official 490:119543c9f674 15 * + Timer Output Compare/PWM Channel Configuration
mbed_official 490:119543c9f674 16 * + Timer Output Compare/PWM Start
mbed_official 490:119543c9f674 17 * + Timer Output Compare/PWM Start Interruption
mbed_official 490:119543c9f674 18 * + Timer Output Compare/PWM Start DMA
mbed_official 490:119543c9f674 19 * + Timer Input Capture Initialization
mbed_official 490:119543c9f674 20 * + Timer Input Capture Channel Configuration
mbed_official 490:119543c9f674 21 * + Timer Input Capture Start
mbed_official 490:119543c9f674 22 * + Timer Input Capture Start Interruption
mbed_official 490:119543c9f674 23 * + Timer Input Capture Start DMA
mbed_official 490:119543c9f674 24 * + Timer One Pulse Initialization
mbed_official 490:119543c9f674 25 * + Timer One Pulse Channel Configuration
mbed_official 490:119543c9f674 26 * + Timer One Pulse Start
mbed_official 490:119543c9f674 27 * + Timer Encoder Interface Initialization
mbed_official 490:119543c9f674 28 * + Timer Encoder Interface Start
mbed_official 490:119543c9f674 29 * + Timer Encoder Interface Start Interruption
mbed_official 490:119543c9f674 30 * + Timer Encoder Interface Start DMA
mbed_official 490:119543c9f674 31 * + Timer OCRef clear configuration
mbed_official 490:119543c9f674 32 * + Timer External Clock configuration
mbed_official 490:119543c9f674 33 * + Timer Complementary signal bread and dead time configuration
mbed_official 490:119543c9f674 34 * + Timer Master and Slave synchronization configuration
mbed_official 376:cb4d9db17537 35 @verbatim
mbed_official 376:cb4d9db17537 36 ==============================================================================
mbed_official 376:cb4d9db17537 37 ##### TIMER Generic features #####
mbed_official 376:cb4d9db17537 38 ==============================================================================
mbed_official 376:cb4d9db17537 39 [..] The Timer features include:
mbed_official 376:cb4d9db17537 40 (#) 16-bit up, down, up/down auto-reload counter.
mbed_official 376:cb4d9db17537 41 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the counter clock
mbed_official 376:cb4d9db17537 42 frequency either by any factor between 1 and 65536.
mbed_official 376:cb4d9db17537 43 (#) Up to 4 independent channels for:
mbed_official 376:cb4d9db17537 44 (++) Input Capture
mbed_official 376:cb4d9db17537 45 (++) Output Compare
mbed_official 376:cb4d9db17537 46 (++) PWM generation (Edge and Center-aligned Mode)
mbed_official 376:cb4d9db17537 47 (++) One-pulse mode output
mbed_official 376:cb4d9db17537 48 (#) Synchronization circuit to control the timer with external signals and to interconnect
mbed_official 376:cb4d9db17537 49 several timers together.
mbed_official 376:cb4d9db17537 50 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
mbed_official 376:cb4d9db17537 51 purposes
mbed_official 376:cb4d9db17537 52
mbed_official 376:cb4d9db17537 53 ##### How to use this driver #####
mbed_official 376:cb4d9db17537 54 ================================================================================
mbed_official 376:cb4d9db17537 55 [..]
mbed_official 490:119543c9f674 56 (#) Initialize the TIM low level resources by implementing the following functions
mbed_official 490:119543c9f674 57 depending from feature used :
mbed_official 490:119543c9f674 58 (++) Time Base : HAL_TIM_Base_MspInit()
mbed_official 490:119543c9f674 59 (++) Input Capture : HAL_TIM_IC_MspInit()
mbed_official 490:119543c9f674 60 (++) Output Compare : HAL_TIM_OC_MspInit()
mbed_official 490:119543c9f674 61 (++) PWM generation : HAL_TIM_PWM_MspInit()
mbed_official 490:119543c9f674 62 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
mbed_official 490:119543c9f674 63 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
mbed_official 490:119543c9f674 64
mbed_official 490:119543c9f674 65 (#) Initialize the TIM low level resources :
mbed_official 490:119543c9f674 66 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
mbed_official 490:119543c9f674 67 (##) TIM pins configuration
mbed_official 490:119543c9f674 68 (+++) Enable the clock for the TIM GPIOs using the following function:
mbed_official 490:119543c9f674 69 __HAL_RCC_GPIOx_CLK_ENABLE();
mbed_official 490:119543c9f674 70 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
mbed_official 376:cb4d9db17537 71
mbed_official 376:cb4d9db17537 72 (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx),
mbed_official 376:cb4d9db17537 73 using the following function:
mbed_official 376:cb4d9db17537 74 HAL_TIM_ConfigClockSource, the clock configuration should be done before any start function.
mbed_official 376:cb4d9db17537 75
mbed_official 376:cb4d9db17537 76 (#) Configure the TIM in the desired functioning mode using one of the
mbed_official 376:cb4d9db17537 77 initialization function of this driver:
mbed_official 376:cb4d9db17537 78 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
mbed_official 376:cb4d9db17537 79 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
mbed_official 376:cb4d9db17537 80 Output Compare signal.
mbed_official 376:cb4d9db17537 81 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
mbed_official 376:cb4d9db17537 82 PWM signal.
mbed_official 376:cb4d9db17537 83 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
mbed_official 376:cb4d9db17537 84 external signal.
mbed_official 376:cb4d9db17537 85 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer in One Pulse Mode.
mbed_official 376:cb4d9db17537 86 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
mbed_official 376:cb4d9db17537 87
mbed_official 376:cb4d9db17537 88 (#) Activate the TIM peripheral using one of the start functions:
mbed_official 376:cb4d9db17537 89 HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT(),
mbed_official 376:cb4d9db17537 90 HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT(),
mbed_official 376:cb4d9db17537 91 HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT(),
mbed_official 376:cb4d9db17537 92 HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT(),
mbed_official 376:cb4d9db17537 93 HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT(),
mbed_official 376:cb4d9db17537 94 HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA() or HAL_TIM_Encoder_Start_IT()
mbed_official 376:cb4d9db17537 95
mbed_official 376:cb4d9db17537 96 (#) The DMA Burst is managed with the two following functions:
mbed_official 376:cb4d9db17537 97 HAL_TIM_DMABurst_WriteStart
mbed_official 376:cb4d9db17537 98 HAL_TIM_DMABurst_ReadStart
mbed_official 376:cb4d9db17537 99
mbed_official 376:cb4d9db17537 100 @endverbatim
mbed_official 376:cb4d9db17537 101 ******************************************************************************
mbed_official 376:cb4d9db17537 102 * @attention
mbed_official 376:cb4d9db17537 103 *
mbed_official 490:119543c9f674 104 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 376:cb4d9db17537 105 *
mbed_official 376:cb4d9db17537 106 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 376:cb4d9db17537 107 * are permitted provided that the following conditions are met:
mbed_official 376:cb4d9db17537 108 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 376:cb4d9db17537 109 * this list of conditions and the following disclaimer.
mbed_official 376:cb4d9db17537 110 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 376:cb4d9db17537 111 * this list of conditions and the following disclaimer in the documentation
mbed_official 376:cb4d9db17537 112 * and/or other materials provided with the distribution.
mbed_official 376:cb4d9db17537 113 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 376:cb4d9db17537 114 * may be used to endorse or promote products derived from this software
mbed_official 376:cb4d9db17537 115 * without specific prior written permission.
mbed_official 376:cb4d9db17537 116 *
mbed_official 376:cb4d9db17537 117 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 376:cb4d9db17537 118 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 376:cb4d9db17537 119 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 376:cb4d9db17537 120 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 376:cb4d9db17537 121 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 376:cb4d9db17537 122 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 376:cb4d9db17537 123 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 376:cb4d9db17537 124 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 376:cb4d9db17537 125 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 376:cb4d9db17537 126 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 376:cb4d9db17537 127 *
mbed_official 376:cb4d9db17537 128 ******************************************************************************
mbed_official 376:cb4d9db17537 129 */
mbed_official 376:cb4d9db17537 130
mbed_official 376:cb4d9db17537 131 /* Includes ------------------------------------------------------------------*/
mbed_official 376:cb4d9db17537 132 #include "stm32l0xx_hal.h"
mbed_official 376:cb4d9db17537 133
mbed_official 376:cb4d9db17537 134 /** @addtogroup STM32L0xx_HAL_Driver
mbed_official 376:cb4d9db17537 135 * @{
mbed_official 376:cb4d9db17537 136 */
mbed_official 376:cb4d9db17537 137
mbed_official 490:119543c9f674 138 /** @addtogroup TIM
mbed_official 376:cb4d9db17537 139 * @brief TIM HAL module driver
mbed_official 376:cb4d9db17537 140 * @{
mbed_official 376:cb4d9db17537 141 */
mbed_official 376:cb4d9db17537 142
mbed_official 376:cb4d9db17537 143 #ifdef HAL_TIM_MODULE_ENABLED
mbed_official 376:cb4d9db17537 144
mbed_official 376:cb4d9db17537 145 /* Private typedef -----------------------------------------------------------*/
mbed_official 376:cb4d9db17537 146 /* Private define ------------------------------------------------------------*/
mbed_official 376:cb4d9db17537 147 /* Private macro -------------------------------------------------------------*/
mbed_official 376:cb4d9db17537 148 /* Private variables ---------------------------------------------------------*/
mbed_official 376:cb4d9db17537 149 /* Private function prototypes -----------------------------------------------*/
mbed_official 376:cb4d9db17537 150 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
mbed_official 376:cb4d9db17537 151 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 376:cb4d9db17537 152 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 376:cb4d9db17537 153 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 376:cb4d9db17537 154 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 376:cb4d9db17537 155 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official 376:cb4d9db17537 156 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 376:cb4d9db17537 157 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official 376:cb4d9db17537 158 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 376:cb4d9db17537 159 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official 376:cb4d9db17537 160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official 376:cb4d9db17537 161 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
mbed_official 490:119543c9f674 162 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
mbed_official 376:cb4d9db17537 163 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
mbed_official 376:cb4d9db17537 164 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
mbed_official 376:cb4d9db17537 165 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
mbed_official 490:119543c9f674 166 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,TIM_SlaveConfigTypeDef * sSlaveConfig);
mbed_official 490:119543c9f674 167
mbed_official 490:119543c9f674 168 /*******************************************************************************/
mbed_official 490:119543c9f674 169 /* Exported functions ---------------------------------------------------------*/
mbed_official 490:119543c9f674 170 /*******************************************************************************/
mbed_official 490:119543c9f674 171
mbed_official 490:119543c9f674 172 /** @addtogroup TIM_Exported_Functions
mbed_official 376:cb4d9db17537 173 * @{
mbed_official 376:cb4d9db17537 174 */
mbed_official 376:cb4d9db17537 175
mbed_official 490:119543c9f674 176 /** @addtogroup TIM_Exported_Functions_Group1
mbed_official 490:119543c9f674 177 * @brief Time Base functions
mbed_official 376:cb4d9db17537 178 *
mbed_official 376:cb4d9db17537 179 @verbatim
mbed_official 490:119543c9f674 180 ==============================================================================
mbed_official 490:119543c9f674 181 ##### Timer Base functions #####
mbed_official 490:119543c9f674 182 ==============================================================================
mbed_official 490:119543c9f674 183 [..]
mbed_official 490:119543c9f674 184 This section provides functions allowing to:
mbed_official 490:119543c9f674 185 (+) Initialize and configure the TIM base.
mbed_official 490:119543c9f674 186 (+) De-initialize the TIM base.
mbed_official 490:119543c9f674 187 (+) Start the Timer Base.
mbed_official 490:119543c9f674 188 (+) Stop the Timer Base.
mbed_official 490:119543c9f674 189 (+) Start the Timer Base and enable interrupt.
mbed_official 490:119543c9f674 190 (+) Stop the Timer Base and disable interrupt.
mbed_official 490:119543c9f674 191 (+) Start the Timer Base and enable DMA transfer.
mbed_official 490:119543c9f674 192 (+) Stop the Timer Base and disable DMA transfer.
mbed_official 376:cb4d9db17537 193
mbed_official 376:cb4d9db17537 194 @endverbatim
mbed_official 376:cb4d9db17537 195 * @{
mbed_official 376:cb4d9db17537 196 */
mbed_official 376:cb4d9db17537 197 /**
mbed_official 376:cb4d9db17537 198 * @brief Initializes the TIM Time base Unit according to the specified
mbed_official 376:cb4d9db17537 199 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 490:119543c9f674 200 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 201 * @retval HAL status
mbed_official 376:cb4d9db17537 202 */
mbed_official 376:cb4d9db17537 203 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 204 {
mbed_official 376:cb4d9db17537 205 /* Check the TIM handle allocation */
mbed_official 490:119543c9f674 206 if(htim == NULL)
mbed_official 376:cb4d9db17537 207 {
mbed_official 376:cb4d9db17537 208 return HAL_ERROR;
mbed_official 376:cb4d9db17537 209 }
mbed_official 376:cb4d9db17537 210
mbed_official 376:cb4d9db17537 211 /* Check the parameters */
mbed_official 376:cb4d9db17537 212 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 213 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 376:cb4d9db17537 214 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 490:119543c9f674 215 assert_param(IS_TIM_PERIOD(htim->Init.Period));
mbed_official 490:119543c9f674 216 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
mbed_official 376:cb4d9db17537 217
mbed_official 376:cb4d9db17537 218 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 376:cb4d9db17537 219 {
mbed_official 376:cb4d9db17537 220 /* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official 376:cb4d9db17537 221 HAL_TIM_Base_MspInit(htim);
mbed_official 376:cb4d9db17537 222 }
mbed_official 376:cb4d9db17537 223
mbed_official 376:cb4d9db17537 224 /* Set the TIM state */
mbed_official 376:cb4d9db17537 225 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 226
mbed_official 376:cb4d9db17537 227 /* Set the Time Base configuration */
mbed_official 376:cb4d9db17537 228 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 376:cb4d9db17537 229
mbed_official 376:cb4d9db17537 230 /* Initialize the TIM state*/
mbed_official 376:cb4d9db17537 231 htim->State= HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 232
mbed_official 376:cb4d9db17537 233 return HAL_OK;
mbed_official 376:cb4d9db17537 234 }
mbed_official 376:cb4d9db17537 235
mbed_official 376:cb4d9db17537 236 /**
mbed_official 490:119543c9f674 237 * @brief DeInitializes the TIM Base peripheral
mbed_official 490:119543c9f674 238 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 239 * @retval HAL status
mbed_official 376:cb4d9db17537 240 */
mbed_official 376:cb4d9db17537 241 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 242 {
mbed_official 376:cb4d9db17537 243 /* Check the parameters */
mbed_official 376:cb4d9db17537 244 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 245
mbed_official 376:cb4d9db17537 246 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 247
mbed_official 376:cb4d9db17537 248 /* Disable the TIM Peripheral Clock */
mbed_official 376:cb4d9db17537 249 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 250
mbed_official 490:119543c9f674 251 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 490:119543c9f674 252 HAL_TIM_Base_MspDeInit(htim);
mbed_official 490:119543c9f674 253
mbed_official 490:119543c9f674 254 /* Change TIM state */
mbed_official 376:cb4d9db17537 255 htim->State = HAL_TIM_STATE_RESET;
mbed_official 376:cb4d9db17537 256
mbed_official 376:cb4d9db17537 257 /* Release Lock */
mbed_official 376:cb4d9db17537 258 __HAL_UNLOCK(htim);
mbed_official 490:119543c9f674 259
mbed_official 376:cb4d9db17537 260 return HAL_OK;
mbed_official 376:cb4d9db17537 261 }
mbed_official 376:cb4d9db17537 262
mbed_official 376:cb4d9db17537 263 /**
mbed_official 376:cb4d9db17537 264 * @brief Initializes the TIM Base MSP.
mbed_official 490:119543c9f674 265 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 266 * @retval None
mbed_official 376:cb4d9db17537 267 */
mbed_official 376:cb4d9db17537 268 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 269 {
mbed_official 376:cb4d9db17537 270 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 376:cb4d9db17537 271 the HAL_TIM_Base_MspInit could be implemented in the user file
mbed_official 376:cb4d9db17537 272 */
mbed_official 376:cb4d9db17537 273 }
mbed_official 376:cb4d9db17537 274
mbed_official 376:cb4d9db17537 275 /**
mbed_official 376:cb4d9db17537 276 * @brief DeInitializes TIM Base MSP.
mbed_official 490:119543c9f674 277 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 278 * @retval None
mbed_official 376:cb4d9db17537 279 */
mbed_official 376:cb4d9db17537 280 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 281 {
mbed_official 376:cb4d9db17537 282 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 376:cb4d9db17537 283 the HAL_TIM_Base_MspDeInit could be implemented in the user file
mbed_official 376:cb4d9db17537 284 */
mbed_official 376:cb4d9db17537 285 }
mbed_official 376:cb4d9db17537 286
mbed_official 376:cb4d9db17537 287 /**
mbed_official 376:cb4d9db17537 288 * @brief Starts the TIM Base generation.
mbed_official 490:119543c9f674 289 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 290 * @retval HAL status
mbed_official 376:cb4d9db17537 291 */
mbed_official 376:cb4d9db17537 292 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 293 {
mbed_official 376:cb4d9db17537 294 /* Check the parameters */
mbed_official 376:cb4d9db17537 295 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 296
mbed_official 376:cb4d9db17537 297 /* Set the TIM state */
mbed_official 376:cb4d9db17537 298 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 299
mbed_official 376:cb4d9db17537 300 /* Enable the Peripheral */
mbed_official 376:cb4d9db17537 301 __HAL_TIM_ENABLE(htim);
mbed_official 490:119543c9f674 302
mbed_official 376:cb4d9db17537 303 /* Change the TIM state*/
mbed_official 376:cb4d9db17537 304 htim->State= HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 305
mbed_official 376:cb4d9db17537 306 /* Return function status */
mbed_official 376:cb4d9db17537 307 return HAL_OK;
mbed_official 376:cb4d9db17537 308 }
mbed_official 376:cb4d9db17537 309
mbed_official 376:cb4d9db17537 310 /**
mbed_official 376:cb4d9db17537 311 * @brief Stops the TIM Base generation.
mbed_official 490:119543c9f674 312 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 313 * @retval HAL status
mbed_official 376:cb4d9db17537 314 */
mbed_official 376:cb4d9db17537 315 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 316 {
mbed_official 376:cb4d9db17537 317 /* Check the parameters */
mbed_official 376:cb4d9db17537 318 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 319
mbed_official 376:cb4d9db17537 320 /* Set the TIM state */
mbed_official 376:cb4d9db17537 321 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 322
mbed_official 376:cb4d9db17537 323 /* Disable the Peripheral */
mbed_official 376:cb4d9db17537 324 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 325
mbed_official 376:cb4d9db17537 326 /* Change the TIM state*/
mbed_official 376:cb4d9db17537 327 htim->State= HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 328
mbed_official 376:cb4d9db17537 329 /* Return function status */
mbed_official 376:cb4d9db17537 330 return HAL_OK;
mbed_official 376:cb4d9db17537 331 }
mbed_official 376:cb4d9db17537 332
mbed_official 376:cb4d9db17537 333 /**
mbed_official 376:cb4d9db17537 334 * @brief Starts the TIM Base generation in interrupt mode.
mbed_official 490:119543c9f674 335 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 336 * @retval HAL status
mbed_official 376:cb4d9db17537 337 */
mbed_official 376:cb4d9db17537 338 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 339 {
mbed_official 376:cb4d9db17537 340 /* Check the parameters */
mbed_official 376:cb4d9db17537 341 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 342
mbed_official 376:cb4d9db17537 343 /* Enable the TIM Update interrupt */
mbed_official 376:cb4d9db17537 344 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 490:119543c9f674 345
mbed_official 376:cb4d9db17537 346 /* Enable the Peripheral */
mbed_official 376:cb4d9db17537 347 __HAL_TIM_ENABLE(htim);
mbed_official 490:119543c9f674 348
mbed_official 376:cb4d9db17537 349 /* Return function status */
mbed_official 376:cb4d9db17537 350 return HAL_OK;
mbed_official 376:cb4d9db17537 351 }
mbed_official 376:cb4d9db17537 352
mbed_official 376:cb4d9db17537 353 /**
mbed_official 376:cb4d9db17537 354 * @brief Stops the TIM Base generation in interrupt mode.
mbed_official 490:119543c9f674 355 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 356 * @retval HAL status
mbed_official 376:cb4d9db17537 357 */
mbed_official 376:cb4d9db17537 358 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 359 {
mbed_official 376:cb4d9db17537 360 /* Check the parameters */
mbed_official 376:cb4d9db17537 361 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 362 /* Disable the TIM Update interrupt */
mbed_official 376:cb4d9db17537 363 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 490:119543c9f674 364
mbed_official 376:cb4d9db17537 365 /* Disable the Peripheral */
mbed_official 376:cb4d9db17537 366 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 367
mbed_official 376:cb4d9db17537 368 /* Return function status */
mbed_official 376:cb4d9db17537 369 return HAL_OK;
mbed_official 376:cb4d9db17537 370 }
mbed_official 376:cb4d9db17537 371
mbed_official 376:cb4d9db17537 372 /**
mbed_official 376:cb4d9db17537 373 * @brief Starts the TIM Base generation in DMA mode.
mbed_official 490:119543c9f674 374 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 375 * @param pData: The source Buffer address.
mbed_official 376:cb4d9db17537 376 * @param Length: The length of data to be transferred from memory to peripheral.
mbed_official 376:cb4d9db17537 377 * @retval HAL status
mbed_official 376:cb4d9db17537 378 */
mbed_official 376:cb4d9db17537 379 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
mbed_official 376:cb4d9db17537 380 {
mbed_official 376:cb4d9db17537 381 /* Check the parameters */
mbed_official 490:119543c9f674 382 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 383
mbed_official 376:cb4d9db17537 384 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 376:cb4d9db17537 385 {
mbed_official 376:cb4d9db17537 386 return HAL_BUSY;
mbed_official 376:cb4d9db17537 387 }
mbed_official 376:cb4d9db17537 388 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 376:cb4d9db17537 389 {
mbed_official 490:119543c9f674 390 if((pData == 0 ) && (Length > 0))
mbed_official 376:cb4d9db17537 391 {
mbed_official 490:119543c9f674 392 return HAL_ERROR;
mbed_official 376:cb4d9db17537 393 }
mbed_official 376:cb4d9db17537 394 else
mbed_official 376:cb4d9db17537 395 {
mbed_official 376:cb4d9db17537 396 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 397 }
mbed_official 490:119543c9f674 398 }
mbed_official 376:cb4d9db17537 399 /* Set the DMA Period elapsed callback */
mbed_official 376:cb4d9db17537 400 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 490:119543c9f674 401
mbed_official 376:cb4d9db17537 402 /* Set the DMA error callback */
mbed_official 490:119543c9f674 403 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 404
mbed_official 376:cb4d9db17537 405 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 406 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
mbed_official 376:cb4d9db17537 407
mbed_official 376:cb4d9db17537 408 /* Enable the TIM Update DMA request */
mbed_official 376:cb4d9db17537 409 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 376:cb4d9db17537 410
mbed_official 376:cb4d9db17537 411 /* Enable the Peripheral */
mbed_official 490:119543c9f674 412 __HAL_TIM_ENABLE(htim);
mbed_official 376:cb4d9db17537 413
mbed_official 376:cb4d9db17537 414 /* Return function status */
mbed_official 376:cb4d9db17537 415 return HAL_OK;
mbed_official 376:cb4d9db17537 416 }
mbed_official 376:cb4d9db17537 417
mbed_official 376:cb4d9db17537 418 /**
mbed_official 376:cb4d9db17537 419 * @brief Stops the TIM Base generation in DMA mode.
mbed_official 490:119543c9f674 420 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 421 * @retval HAL status
mbed_official 376:cb4d9db17537 422 */
mbed_official 376:cb4d9db17537 423 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 424 {
mbed_official 376:cb4d9db17537 425 /* Check the parameters */
mbed_official 376:cb4d9db17537 426 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 427
mbed_official 376:cb4d9db17537 428 /* Disable the TIM Update DMA request */
mbed_official 376:cb4d9db17537 429 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 490:119543c9f674 430
mbed_official 376:cb4d9db17537 431 /* Disable the Peripheral */
mbed_official 376:cb4d9db17537 432 __HAL_TIM_DISABLE(htim);
mbed_official 376:cb4d9db17537 433
mbed_official 376:cb4d9db17537 434 /* Change the htim state */
mbed_official 376:cb4d9db17537 435 htim->State = HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 436
mbed_official 376:cb4d9db17537 437 /* Return function status */
mbed_official 376:cb4d9db17537 438 return HAL_OK;
mbed_official 376:cb4d9db17537 439 }
mbed_official 376:cb4d9db17537 440
mbed_official 376:cb4d9db17537 441 /**
mbed_official 490:119543c9f674 442 * @}
mbed_official 490:119543c9f674 443 */
mbed_official 490:119543c9f674 444
mbed_official 490:119543c9f674 445
mbed_official 490:119543c9f674 446 /** @addtogroup TIM_Exported_Functions_Group2
mbed_official 490:119543c9f674 447 * @brief Time Output Compare functions
mbed_official 490:119543c9f674 448 *
mbed_official 490:119543c9f674 449 @verbatim
mbed_official 490:119543c9f674 450 ==============================================================================
mbed_official 490:119543c9f674 451 ##### Timer Output Compare functions #####
mbed_official 490:119543c9f674 452 ==============================================================================
mbed_official 490:119543c9f674 453 [..]
mbed_official 490:119543c9f674 454 This section provides functions allowing to:
mbed_official 490:119543c9f674 455 (+) Initialize and configure the TIM Output Compare.
mbed_official 490:119543c9f674 456 (+) De-initialize the TIM Output Compare.
mbed_official 490:119543c9f674 457 (+) Start the Timer Output Compare.
mbed_official 490:119543c9f674 458 (+) Stop the Timer Output Compare.
mbed_official 490:119543c9f674 459 (+) Start the Timer Output Compare and enable interrupt.
mbed_official 490:119543c9f674 460 (+) Stop the Timer Output Compare and disable interrupt.
mbed_official 490:119543c9f674 461 (+) Start the Timer Output Compare and enable DMA transfer.
mbed_official 490:119543c9f674 462 (+) Stop the Timer Output Compare and disable DMA transfer.
mbed_official 490:119543c9f674 463
mbed_official 490:119543c9f674 464 @endverbatim
mbed_official 490:119543c9f674 465 * @{
mbed_official 490:119543c9f674 466 */
mbed_official 490:119543c9f674 467 /**
mbed_official 490:119543c9f674 468 * @brief Initializes the TIM Output Compare according to the specified
mbed_official 490:119543c9f674 469 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 490:119543c9f674 470 * @param htim: TIM Output Compare handle
mbed_official 490:119543c9f674 471 * @retval HAL status
mbed_official 490:119543c9f674 472 */
mbed_official 490:119543c9f674 473 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
mbed_official 490:119543c9f674 474 {
mbed_official 490:119543c9f674 475 /* Check the TIM handle allocation */
mbed_official 490:119543c9f674 476 if(htim == NULL)
mbed_official 490:119543c9f674 477 {
mbed_official 490:119543c9f674 478 return HAL_ERROR;
mbed_official 490:119543c9f674 479 }
mbed_official 490:119543c9f674 480
mbed_official 490:119543c9f674 481 /* Check the parameters */
mbed_official 490:119543c9f674 482 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 483 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 490:119543c9f674 484 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 490:119543c9f674 485 assert_param(IS_TIM_PERIOD(htim->Init.Period));
mbed_official 490:119543c9f674 486 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
mbed_official 490:119543c9f674 487
mbed_official 490:119543c9f674 488 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 490:119543c9f674 489 {
mbed_official 490:119543c9f674 490 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA*/
mbed_official 490:119543c9f674 491 HAL_TIM_OC_MspInit(htim);
mbed_official 490:119543c9f674 492 }
mbed_official 490:119543c9f674 493 /* Set the TIM state */
mbed_official 490:119543c9f674 494 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 495
mbed_official 490:119543c9f674 496 /* Init the base time for the Output Compare */
mbed_official 490:119543c9f674 497 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 490:119543c9f674 498
mbed_official 490:119543c9f674 499 /* Initialize the TIM state*/
mbed_official 490:119543c9f674 500 htim->State= HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 501
mbed_official 490:119543c9f674 502 return HAL_OK;
mbed_official 490:119543c9f674 503 }
mbed_official 490:119543c9f674 504
mbed_official 490:119543c9f674 505 /**
mbed_official 490:119543c9f674 506 * @brief DeInitializes the TIM peripheral
mbed_official 490:119543c9f674 507 * @param htim: TIM Output Compare handle
mbed_official 490:119543c9f674 508 * @retval HAL status
mbed_official 490:119543c9f674 509 */
mbed_official 490:119543c9f674 510 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 511 {
mbed_official 490:119543c9f674 512 /* Check the parameters */
mbed_official 490:119543c9f674 513 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 514
mbed_official 490:119543c9f674 515 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 516
mbed_official 490:119543c9f674 517 /* Disable the TIM Peripheral Clock */
mbed_official 490:119543c9f674 518 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 519
mbed_official 490:119543c9f674 520 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 490:119543c9f674 521 HAL_TIM_OC_MspDeInit(htim);
mbed_official 490:119543c9f674 522
mbed_official 490:119543c9f674 523 /* Change TIM state */
mbed_official 490:119543c9f674 524 htim->State = HAL_TIM_STATE_RESET;
mbed_official 490:119543c9f674 525
mbed_official 490:119543c9f674 526 /* Release Lock */
mbed_official 490:119543c9f674 527 __HAL_UNLOCK(htim);
mbed_official 490:119543c9f674 528
mbed_official 490:119543c9f674 529 return HAL_OK;
mbed_official 490:119543c9f674 530 }
mbed_official 490:119543c9f674 531
mbed_official 490:119543c9f674 532 /**
mbed_official 490:119543c9f674 533 * @brief Initializes the TIM Output Compare MSP.
mbed_official 490:119543c9f674 534 * @param htim : TIM handle
mbed_official 490:119543c9f674 535 * @retval None
mbed_official 490:119543c9f674 536 */
mbed_official 490:119543c9f674 537 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 538 {
mbed_official 490:119543c9f674 539 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 490:119543c9f674 540 the HAL_TIM_OC_MspInit could be implemented in the user file
mbed_official 490:119543c9f674 541 */
mbed_official 490:119543c9f674 542 }
mbed_official 490:119543c9f674 543
mbed_official 490:119543c9f674 544 /**
mbed_official 490:119543c9f674 545 * @brief DeInitializes TIM Output Compare MSP.
mbed_official 490:119543c9f674 546 * @param htim : TIM handle
mbed_official 490:119543c9f674 547 * @retval None
mbed_official 490:119543c9f674 548 */
mbed_official 490:119543c9f674 549 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 550 {
mbed_official 490:119543c9f674 551 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 490:119543c9f674 552 the HAL_TIM_OC_MspDeInit could be implemented in the user file
mbed_official 490:119543c9f674 553 */
mbed_official 490:119543c9f674 554 }
mbed_official 490:119543c9f674 555
mbed_official 490:119543c9f674 556 /**
mbed_official 376:cb4d9db17537 557 * @brief Starts the TIM Output Compare signal generation.
mbed_official 490:119543c9f674 558 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 559 * @param Channel: TIM Channel to be enabled.
mbed_official 376:cb4d9db17537 560 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 561 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 562 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 563 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 490:119543c9f674 564 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 565 * @retval HAL status
mbed_official 376:cb4d9db17537 566 */
mbed_official 376:cb4d9db17537 567 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 568 {
mbed_official 376:cb4d9db17537 569 /* Check the parameters */
mbed_official 376:cb4d9db17537 570 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 571
mbed_official 376:cb4d9db17537 572 /* Enable the Output compare channel */
mbed_official 376:cb4d9db17537 573 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 574
mbed_official 376:cb4d9db17537 575 /* Enable the Peripheral */
mbed_official 490:119543c9f674 576 __HAL_TIM_ENABLE(htim);
mbed_official 376:cb4d9db17537 577
mbed_official 376:cb4d9db17537 578 /* Return function status */
mbed_official 376:cb4d9db17537 579 return HAL_OK;
mbed_official 376:cb4d9db17537 580 }
mbed_official 376:cb4d9db17537 581
mbed_official 376:cb4d9db17537 582 /**
mbed_official 376:cb4d9db17537 583 * @brief Stops the TIM Output Compare signal generation.
mbed_official 490:119543c9f674 584 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 585 * @param Channel: TIM Channel to be disabled.
mbed_official 376:cb4d9db17537 586 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 587 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 588 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 589 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 590 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 591 * @retval HAL status
mbed_official 376:cb4d9db17537 592 */
mbed_official 376:cb4d9db17537 593 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 594 {
mbed_official 376:cb4d9db17537 595 /* Check the parameters */
mbed_official 376:cb4d9db17537 596 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 376:cb4d9db17537 597
mbed_official 376:cb4d9db17537 598 /* Disable the Output compare channel */
mbed_official 376:cb4d9db17537 599 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 600
mbed_official 376:cb4d9db17537 601 /* Disable the Peripheral */
mbed_official 490:119543c9f674 602 __HAL_TIM_DISABLE(htim);
mbed_official 376:cb4d9db17537 603
mbed_official 376:cb4d9db17537 604 /* Return function status */
mbed_official 376:cb4d9db17537 605 return HAL_OK;
mbed_official 490:119543c9f674 606 }
mbed_official 376:cb4d9db17537 607
mbed_official 376:cb4d9db17537 608 /**
mbed_official 376:cb4d9db17537 609 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
mbed_official 490:119543c9f674 610 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 611 * @param Channel: TIM Channel to be enabled.
mbed_official 376:cb4d9db17537 612 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 613 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 614 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 615 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 616 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 617 * @retval HAL status
mbed_official 376:cb4d9db17537 618 */
mbed_official 376:cb4d9db17537 619 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 620 {
mbed_official 376:cb4d9db17537 621 /* Check the parameters */
mbed_official 376:cb4d9db17537 622 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 623
mbed_official 376:cb4d9db17537 624 switch (Channel)
mbed_official 376:cb4d9db17537 625 {
mbed_official 376:cb4d9db17537 626 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 627 {
mbed_official 376:cb4d9db17537 628 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 376:cb4d9db17537 629 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 376:cb4d9db17537 630 }
mbed_official 376:cb4d9db17537 631 break;
mbed_official 490:119543c9f674 632
mbed_official 376:cb4d9db17537 633 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 634 {
mbed_official 376:cb4d9db17537 635 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 376:cb4d9db17537 636 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 376:cb4d9db17537 637 }
mbed_official 376:cb4d9db17537 638 break;
mbed_official 490:119543c9f674 639
mbed_official 376:cb4d9db17537 640 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 641 {
mbed_official 376:cb4d9db17537 642 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 376:cb4d9db17537 643 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 376:cb4d9db17537 644 }
mbed_official 376:cb4d9db17537 645 break;
mbed_official 490:119543c9f674 646
mbed_official 376:cb4d9db17537 647 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 648 {
mbed_official 376:cb4d9db17537 649 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 376:cb4d9db17537 650 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 376:cb4d9db17537 651 }
mbed_official 376:cb4d9db17537 652 break;
mbed_official 490:119543c9f674 653
mbed_official 376:cb4d9db17537 654 default:
mbed_official 376:cb4d9db17537 655 break;
mbed_official 490:119543c9f674 656 }
mbed_official 376:cb4d9db17537 657
mbed_official 376:cb4d9db17537 658 /* Enable the Output compare channel */
mbed_official 376:cb4d9db17537 659 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 660
mbed_official 376:cb4d9db17537 661 /* Enable the Peripheral */
mbed_official 376:cb4d9db17537 662 __HAL_TIM_ENABLE(htim);
mbed_official 376:cb4d9db17537 663
mbed_official 376:cb4d9db17537 664 /* Return function status */
mbed_official 376:cb4d9db17537 665 return HAL_OK;
mbed_official 376:cb4d9db17537 666 }
mbed_official 376:cb4d9db17537 667
mbed_official 376:cb4d9db17537 668 /**
mbed_official 376:cb4d9db17537 669 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
mbed_official 490:119543c9f674 670 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 671 * @param Channel: TIM Channel to be disabled.
mbed_official 376:cb4d9db17537 672 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 673 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 674 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 675 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 676 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 677 * @retval HAL status
mbed_official 376:cb4d9db17537 678 */
mbed_official 376:cb4d9db17537 679 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 680 {
mbed_official 376:cb4d9db17537 681 /* Check the parameters */
mbed_official 376:cb4d9db17537 682 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 683
mbed_official 376:cb4d9db17537 684 switch (Channel)
mbed_official 376:cb4d9db17537 685 {
mbed_official 376:cb4d9db17537 686 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 687 {
mbed_official 376:cb4d9db17537 688 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 376:cb4d9db17537 689 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 376:cb4d9db17537 690 }
mbed_official 376:cb4d9db17537 691 break;
mbed_official 490:119543c9f674 692
mbed_official 376:cb4d9db17537 693 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 694 {
mbed_official 376:cb4d9db17537 695 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 376:cb4d9db17537 696 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 376:cb4d9db17537 697 }
mbed_official 376:cb4d9db17537 698 break;
mbed_official 490:119543c9f674 699
mbed_official 376:cb4d9db17537 700 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 701 {
mbed_official 376:cb4d9db17537 702 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 376:cb4d9db17537 703 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 376:cb4d9db17537 704 }
mbed_official 376:cb4d9db17537 705 break;
mbed_official 490:119543c9f674 706
mbed_official 376:cb4d9db17537 707 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 708 {
mbed_official 376:cb4d9db17537 709 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 376:cb4d9db17537 710 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 376:cb4d9db17537 711 }
mbed_official 376:cb4d9db17537 712 break;
mbed_official 490:119543c9f674 713
mbed_official 376:cb4d9db17537 714 default:
mbed_official 490:119543c9f674 715 break;
mbed_official 490:119543c9f674 716 }
mbed_official 490:119543c9f674 717
mbed_official 376:cb4d9db17537 718 /* Disable the Output compare channel */
mbed_official 376:cb4d9db17537 719 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 490:119543c9f674 720
mbed_official 376:cb4d9db17537 721 /* Disable the Peripheral */
mbed_official 490:119543c9f674 722 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 723
mbed_official 376:cb4d9db17537 724 /* Return function status */
mbed_official 376:cb4d9db17537 725 return HAL_OK;
mbed_official 376:cb4d9db17537 726 }
mbed_official 376:cb4d9db17537 727
mbed_official 376:cb4d9db17537 728 /**
mbed_official 376:cb4d9db17537 729 * @brief Starts the TIM Output Compare signal generation in DMA mode.
mbed_official 490:119543c9f674 730 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 731 * @param Channel: TIM Channel to be enabled.
mbed_official 376:cb4d9db17537 732 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 733 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 734 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 735 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 736 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 737 * @param pData: The source Buffer address.
mbed_official 376:cb4d9db17537 738 * @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official 376:cb4d9db17537 739 * @retval HAL status
mbed_official 376:cb4d9db17537 740 */
mbed_official 376:cb4d9db17537 741 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 376:cb4d9db17537 742 {
mbed_official 376:cb4d9db17537 743 /* Check the parameters */
mbed_official 376:cb4d9db17537 744 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 745
mbed_official 376:cb4d9db17537 746 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 376:cb4d9db17537 747 {
mbed_official 376:cb4d9db17537 748 return HAL_BUSY;
mbed_official 376:cb4d9db17537 749 }
mbed_official 376:cb4d9db17537 750 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 376:cb4d9db17537 751 {
mbed_official 490:119543c9f674 752 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 376:cb4d9db17537 753 {
mbed_official 490:119543c9f674 754 return HAL_ERROR;
mbed_official 376:cb4d9db17537 755 }
mbed_official 376:cb4d9db17537 756 else
mbed_official 376:cb4d9db17537 757 {
mbed_official 376:cb4d9db17537 758 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 759 }
mbed_official 490:119543c9f674 760 }
mbed_official 376:cb4d9db17537 761 switch (Channel)
mbed_official 376:cb4d9db17537 762 {
mbed_official 376:cb4d9db17537 763 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 764 {
mbed_official 376:cb4d9db17537 765 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 766 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 490:119543c9f674 767
mbed_official 376:cb4d9db17537 768 /* Set the DMA error callback */
mbed_official 490:119543c9f674 769 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 770
mbed_official 376:cb4d9db17537 771 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 772 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 490:119543c9f674 773
mbed_official 376:cb4d9db17537 774 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 376:cb4d9db17537 775 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 376:cb4d9db17537 776 }
mbed_official 376:cb4d9db17537 777 break;
mbed_official 490:119543c9f674 778
mbed_official 376:cb4d9db17537 779 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 780 {
mbed_official 376:cb4d9db17537 781 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 782 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 490:119543c9f674 783
mbed_official 376:cb4d9db17537 784 /* Set the DMA error callback */
mbed_official 490:119543c9f674 785 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 786
mbed_official 376:cb4d9db17537 787 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 788 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 490:119543c9f674 789
mbed_official 376:cb4d9db17537 790 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 376:cb4d9db17537 791 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 376:cb4d9db17537 792 }
mbed_official 376:cb4d9db17537 793 break;
mbed_official 490:119543c9f674 794
mbed_official 376:cb4d9db17537 795 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 796 {
mbed_official 376:cb4d9db17537 797 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 798 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 490:119543c9f674 799
mbed_official 376:cb4d9db17537 800 /* Set the DMA error callback */
mbed_official 490:119543c9f674 801 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 802
mbed_official 376:cb4d9db17537 803 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 804 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 490:119543c9f674 805
mbed_official 376:cb4d9db17537 806 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 376:cb4d9db17537 807 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 376:cb4d9db17537 808 }
mbed_official 376:cb4d9db17537 809 break;
mbed_official 490:119543c9f674 810
mbed_official 376:cb4d9db17537 811 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 812 {
mbed_official 376:cb4d9db17537 813 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 814 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 490:119543c9f674 815
mbed_official 376:cb4d9db17537 816 /* Set the DMA error callback */
mbed_official 490:119543c9f674 817 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 818
mbed_official 376:cb4d9db17537 819 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 820 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 490:119543c9f674 821
mbed_official 376:cb4d9db17537 822 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 376:cb4d9db17537 823 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 376:cb4d9db17537 824 }
mbed_official 376:cb4d9db17537 825 break;
mbed_official 490:119543c9f674 826
mbed_official 376:cb4d9db17537 827 default:
mbed_official 376:cb4d9db17537 828 break;
mbed_official 376:cb4d9db17537 829 }
mbed_official 376:cb4d9db17537 830
mbed_official 376:cb4d9db17537 831 /* Enable the Output compare channel */
mbed_official 490:119543c9f674 832 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 490:119543c9f674 833
mbed_official 376:cb4d9db17537 834 /* Enable the Peripheral */
mbed_official 490:119543c9f674 835 __HAL_TIM_ENABLE(htim);
mbed_official 490:119543c9f674 836
mbed_official 376:cb4d9db17537 837 /* Return function status */
mbed_official 376:cb4d9db17537 838 return HAL_OK;
mbed_official 376:cb4d9db17537 839 }
mbed_official 376:cb4d9db17537 840
mbed_official 376:cb4d9db17537 841 /**
mbed_official 376:cb4d9db17537 842 * @brief Stops the TIM Output Compare signal generation in DMA mode.
mbed_official 490:119543c9f674 843 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 844 * @param Channel: TIM Channel to be disabled.
mbed_official 376:cb4d9db17537 845 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 846 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 847 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 848 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 849 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 850 * @retval HAL status
mbed_official 376:cb4d9db17537 851 */
mbed_official 376:cb4d9db17537 852 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 853 {
mbed_official 376:cb4d9db17537 854 /* Check the parameters */
mbed_official 376:cb4d9db17537 855 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 856
mbed_official 376:cb4d9db17537 857 switch (Channel)
mbed_official 376:cb4d9db17537 858 {
mbed_official 376:cb4d9db17537 859 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 860 {
mbed_official 376:cb4d9db17537 861 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 376:cb4d9db17537 862 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 376:cb4d9db17537 863 }
mbed_official 376:cb4d9db17537 864 break;
mbed_official 490:119543c9f674 865
mbed_official 376:cb4d9db17537 866 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 867 {
mbed_official 376:cb4d9db17537 868 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 376:cb4d9db17537 869 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 376:cb4d9db17537 870 }
mbed_official 376:cb4d9db17537 871 break;
mbed_official 490:119543c9f674 872
mbed_official 376:cb4d9db17537 873 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 874 {
mbed_official 376:cb4d9db17537 875 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 376:cb4d9db17537 876 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 376:cb4d9db17537 877 }
mbed_official 376:cb4d9db17537 878 break;
mbed_official 490:119543c9f674 879
mbed_official 376:cb4d9db17537 880 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 881 {
mbed_official 376:cb4d9db17537 882 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 376:cb4d9db17537 883 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 376:cb4d9db17537 884 }
mbed_official 376:cb4d9db17537 885 break;
mbed_official 490:119543c9f674 886
mbed_official 376:cb4d9db17537 887 default:
mbed_official 376:cb4d9db17537 888 break;
mbed_official 490:119543c9f674 889 }
mbed_official 490:119543c9f674 890
mbed_official 376:cb4d9db17537 891 /* Disable the Output compare channel */
mbed_official 376:cb4d9db17537 892 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 490:119543c9f674 893
mbed_official 376:cb4d9db17537 894 /* Disable the Peripheral */
mbed_official 376:cb4d9db17537 895 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 896
mbed_official 376:cb4d9db17537 897 /* Change the htim state */
mbed_official 376:cb4d9db17537 898 htim->State = HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 899
mbed_official 376:cb4d9db17537 900 /* Return function status */
mbed_official 376:cb4d9db17537 901 return HAL_OK;
mbed_official 376:cb4d9db17537 902 }
mbed_official 376:cb4d9db17537 903
mbed_official 376:cb4d9db17537 904 /**
mbed_official 490:119543c9f674 905 * @}
mbed_official 490:119543c9f674 906 */
mbed_official 490:119543c9f674 907
mbed_official 490:119543c9f674 908 /** @addtogroup TIM_Exported_Functions_Group3
mbed_official 490:119543c9f674 909 * @brief Time PWM functions
mbed_official 490:119543c9f674 910 *
mbed_official 490:119543c9f674 911 @verbatim
mbed_official 490:119543c9f674 912 ==============================================================================
mbed_official 490:119543c9f674 913 ##### Timer PWM functions #####
mbed_official 490:119543c9f674 914 ==============================================================================
mbed_official 490:119543c9f674 915 [..]
mbed_official 490:119543c9f674 916 This section provides functions allowing to:
mbed_official 490:119543c9f674 917 (+) Initialize and configure the TIM OPWM.
mbed_official 490:119543c9f674 918 (+) De-initialize the TIM PWM.
mbed_official 490:119543c9f674 919 (+) Start the Timer PWM.
mbed_official 490:119543c9f674 920 (+) Stop the Timer PWM.
mbed_official 490:119543c9f674 921 (+) Start the Timer PWM and enable interrupt.
mbed_official 490:119543c9f674 922 (+) Stop the Timer PWM and disable interrupt.
mbed_official 490:119543c9f674 923 (+) Start the Timer PWM and enable DMA transfer.
mbed_official 490:119543c9f674 924 (+) Stop the Timer PWM and disable DMA transfer.
mbed_official 490:119543c9f674 925
mbed_official 490:119543c9f674 926 @endverbatim
mbed_official 490:119543c9f674 927 * @{
mbed_official 490:119543c9f674 928 */
mbed_official 490:119543c9f674 929 /**
mbed_official 490:119543c9f674 930 * @brief Initializes the TIM PWM Time Base according to the specified
mbed_official 490:119543c9f674 931 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 490:119543c9f674 932 * @param htim : TIM handle
mbed_official 490:119543c9f674 933 * @retval HAL status
mbed_official 490:119543c9f674 934 */
mbed_official 490:119543c9f674 935
mbed_official 490:119543c9f674 936
mbed_official 490:119543c9f674 937 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 938 {
mbed_official 490:119543c9f674 939 /* Check the TIM handle allocation */
mbed_official 490:119543c9f674 940 if(htim == NULL)
mbed_official 490:119543c9f674 941 {
mbed_official 490:119543c9f674 942 return HAL_ERROR;
mbed_official 490:119543c9f674 943 }
mbed_official 490:119543c9f674 944
mbed_official 490:119543c9f674 945 /* Check the parameters */
mbed_official 490:119543c9f674 946 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 947 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 490:119543c9f674 948 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 490:119543c9f674 949 assert_param(IS_TIM_PERIOD(htim->Init.Period));
mbed_official 490:119543c9f674 950 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
mbed_official 490:119543c9f674 951
mbed_official 490:119543c9f674 952 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 490:119543c9f674 953 {
mbed_official 490:119543c9f674 954 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 490:119543c9f674 955 HAL_TIM_PWM_MspInit(htim);
mbed_official 490:119543c9f674 956 }
mbed_official 490:119543c9f674 957
mbed_official 490:119543c9f674 958 /* Set the TIM state */
mbed_official 490:119543c9f674 959 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 960
mbed_official 490:119543c9f674 961 /* Init the base time for the PWM */
mbed_official 490:119543c9f674 962 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 490:119543c9f674 963
mbed_official 490:119543c9f674 964 /* Initialize the TIM state*/
mbed_official 490:119543c9f674 965 htim->State= HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 966
mbed_official 490:119543c9f674 967 return HAL_OK;
mbed_official 490:119543c9f674 968 }
mbed_official 490:119543c9f674 969
mbed_official 490:119543c9f674 970 /**
mbed_official 490:119543c9f674 971 * @brief DeInitializes the TIM peripheral
mbed_official 490:119543c9f674 972 * @param htim : TIM handle
mbed_official 490:119543c9f674 973 * @retval HAL status
mbed_official 490:119543c9f674 974 */
mbed_official 490:119543c9f674 975 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 976 {
mbed_official 490:119543c9f674 977 /* Check the parameters */
mbed_official 490:119543c9f674 978 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 979
mbed_official 490:119543c9f674 980 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 981
mbed_official 490:119543c9f674 982 /* Disable the TIM Peripheral Clock */
mbed_official 490:119543c9f674 983 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 984
mbed_official 490:119543c9f674 985 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 490:119543c9f674 986 HAL_TIM_PWM_MspDeInit(htim);
mbed_official 490:119543c9f674 987
mbed_official 490:119543c9f674 988 /* Change TIM state */
mbed_official 490:119543c9f674 989 htim->State = HAL_TIM_STATE_RESET;
mbed_official 490:119543c9f674 990
mbed_official 490:119543c9f674 991 /* Release Lock */
mbed_official 490:119543c9f674 992 __HAL_UNLOCK(htim);
mbed_official 490:119543c9f674 993
mbed_official 490:119543c9f674 994 return HAL_OK;
mbed_official 490:119543c9f674 995 }
mbed_official 490:119543c9f674 996
mbed_official 490:119543c9f674 997 /**
mbed_official 490:119543c9f674 998 * @brief Initializes the TIM PWM MSP.
mbed_official 490:119543c9f674 999 * @param htim : TIM handle
mbed_official 490:119543c9f674 1000 * @retval None
mbed_official 490:119543c9f674 1001 */
mbed_official 490:119543c9f674 1002 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 1003 {
mbed_official 490:119543c9f674 1004 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 490:119543c9f674 1005 the HAL_TIM_PWM_MspInit could be implemented in the user file
mbed_official 490:119543c9f674 1006 */
mbed_official 490:119543c9f674 1007 }
mbed_official 490:119543c9f674 1008
mbed_official 490:119543c9f674 1009 /**
mbed_official 490:119543c9f674 1010 * @brief DeInitializes TIM PWM MSP.
mbed_official 490:119543c9f674 1011 * @param htim : TIM handle
mbed_official 490:119543c9f674 1012 * @retval None
mbed_official 490:119543c9f674 1013 */
mbed_official 490:119543c9f674 1014 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 1015 {
mbed_official 490:119543c9f674 1016 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 490:119543c9f674 1017 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
mbed_official 490:119543c9f674 1018 */
mbed_official 490:119543c9f674 1019 }
mbed_official 490:119543c9f674 1020
mbed_official 490:119543c9f674 1021 /**
mbed_official 376:cb4d9db17537 1022 * @brief Starts the PWM signal generation.
mbed_official 490:119543c9f674 1023 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1024 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 1025 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1026 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1027 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1028 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1029 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1030 * @retval HAL status
mbed_official 376:cb4d9db17537 1031 */
mbed_official 376:cb4d9db17537 1032 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 1033 {
mbed_official 376:cb4d9db17537 1034 /* Check the parameters */
mbed_official 376:cb4d9db17537 1035 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 376:cb4d9db17537 1036
mbed_official 376:cb4d9db17537 1037 /* Enable the Capture compare channel */
mbed_official 376:cb4d9db17537 1038 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 490:119543c9f674 1039
mbed_official 376:cb4d9db17537 1040 /* Enable the Peripheral */
mbed_official 376:cb4d9db17537 1041 __HAL_TIM_ENABLE(htim);
mbed_official 490:119543c9f674 1042
mbed_official 376:cb4d9db17537 1043 /* Return function status */
mbed_official 376:cb4d9db17537 1044 return HAL_OK;
mbed_official 490:119543c9f674 1045 }
mbed_official 376:cb4d9db17537 1046
mbed_official 376:cb4d9db17537 1047 /**
mbed_official 376:cb4d9db17537 1048 * @brief Stops the PWM signal generation.
mbed_official 490:119543c9f674 1049 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1050 * @param Channel: TIM Channels to be disabled.
mbed_official 376:cb4d9db17537 1051 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1052 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1053 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1054 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1055 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1056 * @retval HAL status
mbed_official 376:cb4d9db17537 1057 */
mbed_official 376:cb4d9db17537 1058 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 490:119543c9f674 1059 {
mbed_official 376:cb4d9db17537 1060 /* Check the parameters */
mbed_official 376:cb4d9db17537 1061 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 1062
mbed_official 376:cb4d9db17537 1063 /* Disable the Capture compare channel */
mbed_official 376:cb4d9db17537 1064 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 490:119543c9f674 1065
mbed_official 376:cb4d9db17537 1066 /* Disable the Peripheral */
mbed_official 376:cb4d9db17537 1067 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 1068
mbed_official 376:cb4d9db17537 1069 /* Change the htim state */
mbed_official 376:cb4d9db17537 1070 htim->State = HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 1071
mbed_official 376:cb4d9db17537 1072 /* Return function status */
mbed_official 376:cb4d9db17537 1073 return HAL_OK;
mbed_official 490:119543c9f674 1074 }
mbed_official 376:cb4d9db17537 1075
mbed_official 376:cb4d9db17537 1076 /**
mbed_official 376:cb4d9db17537 1077 * @brief Starts the PWM signal generation in interrupt mode.
mbed_official 490:119543c9f674 1078 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1079 * @param Channel: TIM Channel to be disabled.
mbed_official 376:cb4d9db17537 1080 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1081 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1082 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1083 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1084 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1085 * @retval HAL status
mbed_official 376:cb4d9db17537 1086 */
mbed_official 376:cb4d9db17537 1087 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 1088 {
mbed_official 376:cb4d9db17537 1089 /* Check the parameters */
mbed_official 376:cb4d9db17537 1090 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 1091
mbed_official 376:cb4d9db17537 1092 switch (Channel)
mbed_official 376:cb4d9db17537 1093 {
mbed_official 376:cb4d9db17537 1094 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 1095 {
mbed_official 376:cb4d9db17537 1096 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 376:cb4d9db17537 1097 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 376:cb4d9db17537 1098 }
mbed_official 376:cb4d9db17537 1099 break;
mbed_official 490:119543c9f674 1100
mbed_official 376:cb4d9db17537 1101 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 1102 {
mbed_official 376:cb4d9db17537 1103 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 376:cb4d9db17537 1104 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 376:cb4d9db17537 1105 }
mbed_official 376:cb4d9db17537 1106 break;
mbed_official 490:119543c9f674 1107
mbed_official 376:cb4d9db17537 1108 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 1109 {
mbed_official 376:cb4d9db17537 1110 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 376:cb4d9db17537 1111 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 376:cb4d9db17537 1112 }
mbed_official 376:cb4d9db17537 1113 break;
mbed_official 490:119543c9f674 1114
mbed_official 376:cb4d9db17537 1115 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 1116 {
mbed_official 376:cb4d9db17537 1117 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 376:cb4d9db17537 1118 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 376:cb4d9db17537 1119 }
mbed_official 376:cb4d9db17537 1120 break;
mbed_official 490:119543c9f674 1121
mbed_official 376:cb4d9db17537 1122 default:
mbed_official 376:cb4d9db17537 1123 break;
mbed_official 490:119543c9f674 1124 }
mbed_official 490:119543c9f674 1125
mbed_official 376:cb4d9db17537 1126 /* Enable the Capture compare channel */
mbed_official 376:cb4d9db17537 1127 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 1128
mbed_official 376:cb4d9db17537 1129 /* Enable the Peripheral */
mbed_official 376:cb4d9db17537 1130 __HAL_TIM_ENABLE(htim);
mbed_official 490:119543c9f674 1131
mbed_official 376:cb4d9db17537 1132 /* Return function status */
mbed_official 376:cb4d9db17537 1133 return HAL_OK;
mbed_official 490:119543c9f674 1134 }
mbed_official 376:cb4d9db17537 1135
mbed_official 376:cb4d9db17537 1136 /**
mbed_official 376:cb4d9db17537 1137 * @brief Stops the PWM signal generation in interrupt mode.
mbed_official 490:119543c9f674 1138 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1139 * @param Channel: TIM Channels to be disabled.
mbed_official 376:cb4d9db17537 1140 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1141 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1142 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1143 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1144 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1145 * @retval HAL status
mbed_official 376:cb4d9db17537 1146 */
mbed_official 376:cb4d9db17537 1147 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 1148 {
mbed_official 376:cb4d9db17537 1149 /* Check the parameters */
mbed_official 376:cb4d9db17537 1150 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 1151
mbed_official 376:cb4d9db17537 1152 switch (Channel)
mbed_official 376:cb4d9db17537 1153 {
mbed_official 376:cb4d9db17537 1154 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 1155 {
mbed_official 376:cb4d9db17537 1156 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 376:cb4d9db17537 1157 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 376:cb4d9db17537 1158 }
mbed_official 376:cb4d9db17537 1159 break;
mbed_official 490:119543c9f674 1160
mbed_official 376:cb4d9db17537 1161 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 1162 {
mbed_official 376:cb4d9db17537 1163 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 376:cb4d9db17537 1164 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 376:cb4d9db17537 1165 }
mbed_official 376:cb4d9db17537 1166 break;
mbed_official 490:119543c9f674 1167
mbed_official 376:cb4d9db17537 1168 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 1169 {
mbed_official 376:cb4d9db17537 1170 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 376:cb4d9db17537 1171 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 376:cb4d9db17537 1172 }
mbed_official 376:cb4d9db17537 1173 break;
mbed_official 490:119543c9f674 1174
mbed_official 376:cb4d9db17537 1175 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 1176 {
mbed_official 376:cb4d9db17537 1177 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 376:cb4d9db17537 1178 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 376:cb4d9db17537 1179 }
mbed_official 376:cb4d9db17537 1180 break;
mbed_official 490:119543c9f674 1181
mbed_official 376:cb4d9db17537 1182 default:
mbed_official 490:119543c9f674 1183 break;
mbed_official 376:cb4d9db17537 1184 }
mbed_official 490:119543c9f674 1185
mbed_official 376:cb4d9db17537 1186 /* Disable the Capture compare channel */
mbed_official 376:cb4d9db17537 1187 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 490:119543c9f674 1188
mbed_official 376:cb4d9db17537 1189 /* Disable the Peripheral */
mbed_official 376:cb4d9db17537 1190 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 1191
mbed_official 376:cb4d9db17537 1192 /* Return function status */
mbed_official 376:cb4d9db17537 1193 return HAL_OK;
mbed_official 490:119543c9f674 1194 }
mbed_official 376:cb4d9db17537 1195
mbed_official 376:cb4d9db17537 1196 /**
mbed_official 376:cb4d9db17537 1197 * @brief Starts the TIM PWM signal generation in DMA mode.
mbed_official 490:119543c9f674 1198 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1199 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 1200 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1201 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1202 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1203 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1204 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 490:119543c9f674 1205 * @param pData: The source Buffer address. This buffer contains the values
mbed_official 490:119543c9f674 1206 * which will be loaded inside the capture/compare registers.
mbed_official 376:cb4d9db17537 1207 * @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official 376:cb4d9db17537 1208 * @retval HAL status
mbed_official 376:cb4d9db17537 1209 */
mbed_official 376:cb4d9db17537 1210 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 376:cb4d9db17537 1211 {
mbed_official 376:cb4d9db17537 1212 /* Check the parameters */
mbed_official 376:cb4d9db17537 1213 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 1214
mbed_official 376:cb4d9db17537 1215 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 376:cb4d9db17537 1216 {
mbed_official 376:cb4d9db17537 1217 return HAL_BUSY;
mbed_official 376:cb4d9db17537 1218 }
mbed_official 376:cb4d9db17537 1219 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 376:cb4d9db17537 1220 {
mbed_official 490:119543c9f674 1221 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 376:cb4d9db17537 1222 {
mbed_official 490:119543c9f674 1223 return HAL_ERROR;
mbed_official 376:cb4d9db17537 1224 }
mbed_official 376:cb4d9db17537 1225 else
mbed_official 376:cb4d9db17537 1226 {
mbed_official 376:cb4d9db17537 1227 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 1228 }
mbed_official 490:119543c9f674 1229 }
mbed_official 376:cb4d9db17537 1230 switch (Channel)
mbed_official 376:cb4d9db17537 1231 {
mbed_official 376:cb4d9db17537 1232 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 1233 {
mbed_official 376:cb4d9db17537 1234 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 1235 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 490:119543c9f674 1236
mbed_official 376:cb4d9db17537 1237 /* Set the DMA error callback */
mbed_official 490:119543c9f674 1238 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 1239
mbed_official 376:cb4d9db17537 1240 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 1241 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 490:119543c9f674 1242
mbed_official 376:cb4d9db17537 1243 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 376:cb4d9db17537 1244 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 376:cb4d9db17537 1245 }
mbed_official 376:cb4d9db17537 1246 break;
mbed_official 490:119543c9f674 1247
mbed_official 376:cb4d9db17537 1248 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 1249 {
mbed_official 376:cb4d9db17537 1250 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 1251 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 490:119543c9f674 1252
mbed_official 376:cb4d9db17537 1253 /* Set the DMA error callback */
mbed_official 490:119543c9f674 1254 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 1255
mbed_official 376:cb4d9db17537 1256 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 1257 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 490:119543c9f674 1258
mbed_official 376:cb4d9db17537 1259 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 376:cb4d9db17537 1260 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 376:cb4d9db17537 1261 }
mbed_official 376:cb4d9db17537 1262 break;
mbed_official 490:119543c9f674 1263
mbed_official 376:cb4d9db17537 1264 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 1265 {
mbed_official 376:cb4d9db17537 1266 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 1267 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 490:119543c9f674 1268
mbed_official 376:cb4d9db17537 1269 /* Set the DMA error callback */
mbed_official 490:119543c9f674 1270 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 1271
mbed_official 376:cb4d9db17537 1272 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 1273 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 490:119543c9f674 1274
mbed_official 376:cb4d9db17537 1275 /* Enable the TIM Output Capture/Compare 3 request */
mbed_official 376:cb4d9db17537 1276 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 376:cb4d9db17537 1277 }
mbed_official 376:cb4d9db17537 1278 break;
mbed_official 490:119543c9f674 1279
mbed_official 376:cb4d9db17537 1280 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 1281 {
mbed_official 376:cb4d9db17537 1282 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 1283 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 490:119543c9f674 1284
mbed_official 376:cb4d9db17537 1285 /* Set the DMA error callback */
mbed_official 490:119543c9f674 1286 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 1287
mbed_official 376:cb4d9db17537 1288 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 1289 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 490:119543c9f674 1290
mbed_official 376:cb4d9db17537 1291 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 376:cb4d9db17537 1292 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 376:cb4d9db17537 1293 }
mbed_official 376:cb4d9db17537 1294 break;
mbed_official 490:119543c9f674 1295
mbed_official 376:cb4d9db17537 1296 default:
mbed_official 376:cb4d9db17537 1297 break;
mbed_official 376:cb4d9db17537 1298 }
mbed_official 376:cb4d9db17537 1299
mbed_official 376:cb4d9db17537 1300 /* Enable the Capture compare channel */
mbed_official 376:cb4d9db17537 1301 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 490:119543c9f674 1302
mbed_official 376:cb4d9db17537 1303 /* Enable the Peripheral */
mbed_official 490:119543c9f674 1304 __HAL_TIM_ENABLE(htim);
mbed_official 490:119543c9f674 1305
mbed_official 376:cb4d9db17537 1306 /* Return function status */
mbed_official 376:cb4d9db17537 1307 return HAL_OK;
mbed_official 376:cb4d9db17537 1308 }
mbed_official 376:cb4d9db17537 1309
mbed_official 376:cb4d9db17537 1310 /**
mbed_official 376:cb4d9db17537 1311 * @brief Stops the TIM PWM signal generation in DMA mode.
mbed_official 490:119543c9f674 1312 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1313 * @param Channel: TIM Channels to be disabled.
mbed_official 376:cb4d9db17537 1314 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1315 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1316 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1317 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1318 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1319 * @retval HAL status
mbed_official 376:cb4d9db17537 1320 */
mbed_official 376:cb4d9db17537 1321 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 1322 {
mbed_official 376:cb4d9db17537 1323 /* Check the parameters */
mbed_official 376:cb4d9db17537 1324 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 1325
mbed_official 376:cb4d9db17537 1326 switch (Channel)
mbed_official 376:cb4d9db17537 1327 {
mbed_official 376:cb4d9db17537 1328 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 1329 {
mbed_official 376:cb4d9db17537 1330 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 376:cb4d9db17537 1331 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 376:cb4d9db17537 1332 }
mbed_official 376:cb4d9db17537 1333 break;
mbed_official 490:119543c9f674 1334
mbed_official 376:cb4d9db17537 1335 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 1336 {
mbed_official 376:cb4d9db17537 1337 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 376:cb4d9db17537 1338 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 376:cb4d9db17537 1339 }
mbed_official 376:cb4d9db17537 1340 break;
mbed_official 490:119543c9f674 1341
mbed_official 376:cb4d9db17537 1342 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 1343 {
mbed_official 376:cb4d9db17537 1344 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 376:cb4d9db17537 1345 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 376:cb4d9db17537 1346 }
mbed_official 376:cb4d9db17537 1347 break;
mbed_official 490:119543c9f674 1348
mbed_official 376:cb4d9db17537 1349 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 1350 {
mbed_official 376:cb4d9db17537 1351 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 376:cb4d9db17537 1352 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 376:cb4d9db17537 1353 }
mbed_official 376:cb4d9db17537 1354 break;
mbed_official 490:119543c9f674 1355
mbed_official 376:cb4d9db17537 1356 default:
mbed_official 376:cb4d9db17537 1357 break;
mbed_official 490:119543c9f674 1358 }
mbed_official 490:119543c9f674 1359
mbed_official 376:cb4d9db17537 1360 /* Disable the Capture compare channel */
mbed_official 376:cb4d9db17537 1361 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 490:119543c9f674 1362
mbed_official 376:cb4d9db17537 1363 /* Disable the Peripheral */
mbed_official 376:cb4d9db17537 1364 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 1365
mbed_official 376:cb4d9db17537 1366 /* Change the htim state */
mbed_official 376:cb4d9db17537 1367 htim->State = HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 1368
mbed_official 376:cb4d9db17537 1369 /* Return function status */
mbed_official 376:cb4d9db17537 1370 return HAL_OK;
mbed_official 376:cb4d9db17537 1371 }
mbed_official 376:cb4d9db17537 1372
mbed_official 376:cb4d9db17537 1373 /**
mbed_official 490:119543c9f674 1374 * @}
mbed_official 490:119543c9f674 1375 */
mbed_official 490:119543c9f674 1376
mbed_official 490:119543c9f674 1377 /** @addtogroup TIM_Exported_Functions_Group4
mbed_official 490:119543c9f674 1378 * @brief Time Input Capture functions
mbed_official 490:119543c9f674 1379 *
mbed_official 490:119543c9f674 1380 @verbatim
mbed_official 490:119543c9f674 1381 ==============================================================================
mbed_official 490:119543c9f674 1382 ##### Timer Input Capture functions #####
mbed_official 490:119543c9f674 1383 ==============================================================================
mbed_official 490:119543c9f674 1384 [..]
mbed_official 490:119543c9f674 1385 This section provides functions allowing to:
mbed_official 490:119543c9f674 1386 (+) Initialize and configure the TIM Input Capture.
mbed_official 490:119543c9f674 1387 (+) De-initialize the TIM Input Capture.
mbed_official 490:119543c9f674 1388 (+) Start the Timer Input Capture.
mbed_official 490:119543c9f674 1389 (+) Stop the Timer Input Capture.
mbed_official 490:119543c9f674 1390 (+) Start the Timer Input Capture and enable interrupt.
mbed_official 490:119543c9f674 1391 (+) Stop the Timer Input Capture and disable interrupt.
mbed_official 490:119543c9f674 1392 (+) Start the Timer Input Capture and enable DMA transfer.
mbed_official 490:119543c9f674 1393 (+) Stop the Timer Input Capture and disable DMA transfer.
mbed_official 490:119543c9f674 1394
mbed_official 490:119543c9f674 1395 @endverbatim
mbed_official 490:119543c9f674 1396 * @{
mbed_official 490:119543c9f674 1397 */
mbed_official 490:119543c9f674 1398 /**
mbed_official 490:119543c9f674 1399 * @brief Initializes the TIM Input Capture Time base according to the specified
mbed_official 490:119543c9f674 1400 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 490:119543c9f674 1401 * @param htim: TIM Input Capture handle
mbed_official 490:119543c9f674 1402 * @retval HAL status
mbed_official 490:119543c9f674 1403 */
mbed_official 490:119543c9f674 1404 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 1405 {
mbed_official 490:119543c9f674 1406 /* Check the TIM handle allocation */
mbed_official 490:119543c9f674 1407 if(htim == NULL)
mbed_official 490:119543c9f674 1408 {
mbed_official 490:119543c9f674 1409 return HAL_ERROR;
mbed_official 490:119543c9f674 1410 }
mbed_official 490:119543c9f674 1411
mbed_official 490:119543c9f674 1412 /* Check the parameters */
mbed_official 490:119543c9f674 1413 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 1414 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 490:119543c9f674 1415 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 490:119543c9f674 1416 assert_param(IS_TIM_PERIOD(htim->Init.Period));
mbed_official 490:119543c9f674 1417 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
mbed_official 490:119543c9f674 1418
mbed_official 490:119543c9f674 1419 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 490:119543c9f674 1420 {
mbed_official 490:119543c9f674 1421 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 490:119543c9f674 1422 HAL_TIM_IC_MspInit(htim);
mbed_official 490:119543c9f674 1423 }
mbed_official 490:119543c9f674 1424
mbed_official 490:119543c9f674 1425 /* Set the TIM state */
mbed_official 490:119543c9f674 1426 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 1427
mbed_official 490:119543c9f674 1428 /* Init the base time for the input capture */
mbed_official 490:119543c9f674 1429 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 490:119543c9f674 1430
mbed_official 490:119543c9f674 1431 /* Initialize the TIM state*/
mbed_official 490:119543c9f674 1432 htim->State= HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 1433
mbed_official 490:119543c9f674 1434 return HAL_OK;
mbed_official 490:119543c9f674 1435 }
mbed_official 490:119543c9f674 1436
mbed_official 490:119543c9f674 1437 /**
mbed_official 490:119543c9f674 1438 * @brief DeInitializes the TIM peripheral
mbed_official 490:119543c9f674 1439 * @param htim: TIM Input Capture handle
mbed_official 490:119543c9f674 1440 * @retval HAL status
mbed_official 490:119543c9f674 1441 */
mbed_official 490:119543c9f674 1442 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 1443 {
mbed_official 490:119543c9f674 1444 /* Check the parameters */
mbed_official 490:119543c9f674 1445 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 1446
mbed_official 490:119543c9f674 1447 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 1448
mbed_official 490:119543c9f674 1449 /* Disable the TIM Peripheral Clock */
mbed_official 490:119543c9f674 1450 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 1451
mbed_official 490:119543c9f674 1452 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 490:119543c9f674 1453 HAL_TIM_IC_MspDeInit(htim);
mbed_official 490:119543c9f674 1454
mbed_official 490:119543c9f674 1455 /* Change TIM state */
mbed_official 490:119543c9f674 1456 htim->State = HAL_TIM_STATE_RESET;
mbed_official 490:119543c9f674 1457
mbed_official 490:119543c9f674 1458 /* Release Lock */
mbed_official 490:119543c9f674 1459 __HAL_UNLOCK(htim);
mbed_official 490:119543c9f674 1460
mbed_official 490:119543c9f674 1461 return HAL_OK;
mbed_official 490:119543c9f674 1462 }
mbed_official 490:119543c9f674 1463
mbed_official 490:119543c9f674 1464 /**
mbed_official 490:119543c9f674 1465 * @brief Initializes the TIM INput Capture MSP.
mbed_official 490:119543c9f674 1466 * @param htim : TIM handle
mbed_official 490:119543c9f674 1467 * @retval None
mbed_official 490:119543c9f674 1468 */
mbed_official 490:119543c9f674 1469 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 1470 {
mbed_official 490:119543c9f674 1471 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 490:119543c9f674 1472 the HAL_TIM_IC_MspInit could be implemented in the user file
mbed_official 490:119543c9f674 1473 */
mbed_official 490:119543c9f674 1474 }
mbed_official 490:119543c9f674 1475
mbed_official 490:119543c9f674 1476 /**
mbed_official 490:119543c9f674 1477 * @brief DeInitializes TIM Input Capture MSP.
mbed_official 490:119543c9f674 1478 * @param htim : TIM handle
mbed_official 490:119543c9f674 1479 * @retval None
mbed_official 490:119543c9f674 1480 */
mbed_official 490:119543c9f674 1481 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 1482 {
mbed_official 490:119543c9f674 1483 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 490:119543c9f674 1484 the HAL_TIM_IC_MspDeInit could be implemented in the user file
mbed_official 490:119543c9f674 1485 */
mbed_official 490:119543c9f674 1486 }
mbed_official 490:119543c9f674 1487 /**
mbed_official 376:cb4d9db17537 1488 * @brief Starts the TIM Input Capture measurement.
mbed_official 490:119543c9f674 1489 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1490 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 1491 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1492 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1493 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1494 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1495 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1496 * @retval HAL status
mbed_official 376:cb4d9db17537 1497 */
mbed_official 376:cb4d9db17537 1498 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 1499 {
mbed_official 376:cb4d9db17537 1500 /* Check the parameters */
mbed_official 376:cb4d9db17537 1501 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 1502
mbed_official 376:cb4d9db17537 1503 /* Enable the Input Capture channel */
mbed_official 376:cb4d9db17537 1504 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 490:119543c9f674 1505
mbed_official 376:cb4d9db17537 1506 /* Enable the Peripheral */
mbed_official 490:119543c9f674 1507 __HAL_TIM_ENABLE(htim);
mbed_official 376:cb4d9db17537 1508
mbed_official 376:cb4d9db17537 1509 /* Return function status */
mbed_official 490:119543c9f674 1510 return HAL_OK;
mbed_official 490:119543c9f674 1511 }
mbed_official 376:cb4d9db17537 1512
mbed_official 376:cb4d9db17537 1513 /**
mbed_official 376:cb4d9db17537 1514 * @brief Stops the TIM Input Capture measurement.
mbed_official 490:119543c9f674 1515 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1516 * @param Channel: TIM Channels to be disabled.
mbed_official 376:cb4d9db17537 1517 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1518 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1519 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1520 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1521 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1522 * @retval HAL status
mbed_official 376:cb4d9db17537 1523 */
mbed_official 376:cb4d9db17537 1524 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 490:119543c9f674 1525 {
mbed_official 376:cb4d9db17537 1526 /* Check the parameters */
mbed_official 376:cb4d9db17537 1527 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 1528
mbed_official 376:cb4d9db17537 1529 /* Disable the Input Capture channel */
mbed_official 376:cb4d9db17537 1530 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 490:119543c9f674 1531
mbed_official 376:cb4d9db17537 1532 /* Disable the Peripheral */
mbed_official 490:119543c9f674 1533 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 1534
mbed_official 376:cb4d9db17537 1535 /* Return function status */
mbed_official 376:cb4d9db17537 1536 return HAL_OK;
mbed_official 376:cb4d9db17537 1537 }
mbed_official 376:cb4d9db17537 1538
mbed_official 376:cb4d9db17537 1539 /**
mbed_official 376:cb4d9db17537 1540 * @brief Starts the TIM Input Capture measurement in interrupt mode.
mbed_official 490:119543c9f674 1541 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1542 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 1543 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1544 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1545 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1546 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1547 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1548 * @retval HAL status
mbed_official 376:cb4d9db17537 1549 */
mbed_official 376:cb4d9db17537 1550 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 1551 {
mbed_official 376:cb4d9db17537 1552 /* Check the parameters */
mbed_official 376:cb4d9db17537 1553 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 1554
mbed_official 376:cb4d9db17537 1555 switch (Channel)
mbed_official 376:cb4d9db17537 1556 {
mbed_official 376:cb4d9db17537 1557 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 1558 {
mbed_official 376:cb4d9db17537 1559 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 376:cb4d9db17537 1560 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 376:cb4d9db17537 1561 }
mbed_official 376:cb4d9db17537 1562 break;
mbed_official 490:119543c9f674 1563
mbed_official 376:cb4d9db17537 1564 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 1565 {
mbed_official 376:cb4d9db17537 1566 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 376:cb4d9db17537 1567 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 376:cb4d9db17537 1568 }
mbed_official 376:cb4d9db17537 1569 break;
mbed_official 490:119543c9f674 1570
mbed_official 376:cb4d9db17537 1571 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 1572 {
mbed_official 376:cb4d9db17537 1573 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 376:cb4d9db17537 1574 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 376:cb4d9db17537 1575 }
mbed_official 376:cb4d9db17537 1576 break;
mbed_official 490:119543c9f674 1577
mbed_official 376:cb4d9db17537 1578 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 1579 {
mbed_official 376:cb4d9db17537 1580 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 376:cb4d9db17537 1581 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 376:cb4d9db17537 1582 }
mbed_official 376:cb4d9db17537 1583 break;
mbed_official 490:119543c9f674 1584
mbed_official 376:cb4d9db17537 1585 default:
mbed_official 376:cb4d9db17537 1586 break;
mbed_official 490:119543c9f674 1587 }
mbed_official 376:cb4d9db17537 1588 /* Enable the Input Capture channel */
mbed_official 376:cb4d9db17537 1589 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 490:119543c9f674 1590
mbed_official 376:cb4d9db17537 1591 /* Enable the Peripheral */
mbed_official 490:119543c9f674 1592 __HAL_TIM_ENABLE(htim);
mbed_official 376:cb4d9db17537 1593
mbed_official 376:cb4d9db17537 1594 /* Return function status */
mbed_official 490:119543c9f674 1595 return HAL_OK;
mbed_official 490:119543c9f674 1596 }
mbed_official 376:cb4d9db17537 1597
mbed_official 376:cb4d9db17537 1598 /**
mbed_official 376:cb4d9db17537 1599 * @brief Stops the TIM Input Capture measurement in interrupt mode.
mbed_official 490:119543c9f674 1600 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1601 * @param Channel : TIM Channels to be disabled
mbed_official 376:cb4d9db17537 1602 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1603 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1604 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1605 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1606 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1607 * @retval HAL status
mbed_official 376:cb4d9db17537 1608 */
mbed_official 376:cb4d9db17537 1609 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 1610 {
mbed_official 376:cb4d9db17537 1611 /* Check the parameters */
mbed_official 376:cb4d9db17537 1612 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 490:119543c9f674 1613
mbed_official 376:cb4d9db17537 1614 switch (Channel)
mbed_official 376:cb4d9db17537 1615 {
mbed_official 376:cb4d9db17537 1616 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 1617 {
mbed_official 376:cb4d9db17537 1618 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 376:cb4d9db17537 1619 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 376:cb4d9db17537 1620 }
mbed_official 376:cb4d9db17537 1621 break;
mbed_official 490:119543c9f674 1622
mbed_official 376:cb4d9db17537 1623 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 1624 {
mbed_official 376:cb4d9db17537 1625 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 376:cb4d9db17537 1626 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 376:cb4d9db17537 1627 }
mbed_official 376:cb4d9db17537 1628 break;
mbed_official 490:119543c9f674 1629
mbed_official 376:cb4d9db17537 1630 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 1631 {
mbed_official 376:cb4d9db17537 1632 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 376:cb4d9db17537 1633 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 376:cb4d9db17537 1634 }
mbed_official 376:cb4d9db17537 1635 break;
mbed_official 490:119543c9f674 1636
mbed_official 376:cb4d9db17537 1637 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 1638 {
mbed_official 376:cb4d9db17537 1639 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 376:cb4d9db17537 1640 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 376:cb4d9db17537 1641 }
mbed_official 376:cb4d9db17537 1642 break;
mbed_official 490:119543c9f674 1643
mbed_official 376:cb4d9db17537 1644 default:
mbed_official 490:119543c9f674 1645 break;
mbed_official 490:119543c9f674 1646 }
mbed_official 490:119543c9f674 1647
mbed_official 376:cb4d9db17537 1648 /* Disable the Input Capture channel */
mbed_official 490:119543c9f674 1649 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 490:119543c9f674 1650
mbed_official 376:cb4d9db17537 1651 /* Disable the Peripheral */
mbed_official 490:119543c9f674 1652 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 1653
mbed_official 376:cb4d9db17537 1654 /* Return function status */
mbed_official 376:cb4d9db17537 1655 return HAL_OK;
mbed_official 376:cb4d9db17537 1656 }
mbed_official 376:cb4d9db17537 1657
mbed_official 376:cb4d9db17537 1658 /**
mbed_official 376:cb4d9db17537 1659 * @brief Starts the TIM Input Capture measurement on in DMA mode.
mbed_official 490:119543c9f674 1660 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1661 * @param Channel : TIM Channels to be enabled
mbed_official 376:cb4d9db17537 1662 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1663 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1664 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1665 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1666 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1667 * @param pData: The destination Buffer address.
mbed_official 376:cb4d9db17537 1668 * @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official 376:cb4d9db17537 1669 * @retval HAL status
mbed_official 376:cb4d9db17537 1670 */
mbed_official 376:cb4d9db17537 1671 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 376:cb4d9db17537 1672 {
mbed_official 376:cb4d9db17537 1673 /* Check the parameters */
mbed_official 376:cb4d9db17537 1674 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 376:cb4d9db17537 1675 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 1676
mbed_official 376:cb4d9db17537 1677 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 376:cb4d9db17537 1678 {
mbed_official 376:cb4d9db17537 1679 return HAL_BUSY;
mbed_official 376:cb4d9db17537 1680 }
mbed_official 376:cb4d9db17537 1681 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 376:cb4d9db17537 1682 {
mbed_official 490:119543c9f674 1683 if((pData == 0 ) && (Length > 0))
mbed_official 376:cb4d9db17537 1684 {
mbed_official 490:119543c9f674 1685 return HAL_ERROR;
mbed_official 376:cb4d9db17537 1686 }
mbed_official 376:cb4d9db17537 1687 else
mbed_official 376:cb4d9db17537 1688 {
mbed_official 376:cb4d9db17537 1689 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 1690 }
mbed_official 490:119543c9f674 1691 }
mbed_official 490:119543c9f674 1692
mbed_official 376:cb4d9db17537 1693 switch (Channel)
mbed_official 376:cb4d9db17537 1694 {
mbed_official 376:cb4d9db17537 1695 case TIM_CHANNEL_1:
mbed_official 376:cb4d9db17537 1696 {
mbed_official 376:cb4d9db17537 1697 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 1698 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 490:119543c9f674 1699
mbed_official 376:cb4d9db17537 1700 /* Set the DMA error callback */
mbed_official 490:119543c9f674 1701 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 1702
mbed_official 376:cb4d9db17537 1703 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 1704 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
mbed_official 490:119543c9f674 1705
mbed_official 490:119543c9f674 1706 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 376:cb4d9db17537 1707 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 376:cb4d9db17537 1708 }
mbed_official 376:cb4d9db17537 1709 break;
mbed_official 490:119543c9f674 1710
mbed_official 376:cb4d9db17537 1711 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 1712 {
mbed_official 376:cb4d9db17537 1713 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 1714 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 490:119543c9f674 1715
mbed_official 376:cb4d9db17537 1716 /* Set the DMA error callback */
mbed_official 490:119543c9f674 1717 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 1718
mbed_official 376:cb4d9db17537 1719 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 1720 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
mbed_official 490:119543c9f674 1721
mbed_official 376:cb4d9db17537 1722 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 376:cb4d9db17537 1723 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 376:cb4d9db17537 1724 }
mbed_official 376:cb4d9db17537 1725 break;
mbed_official 490:119543c9f674 1726
mbed_official 376:cb4d9db17537 1727 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 1728 {
mbed_official 376:cb4d9db17537 1729 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 1730 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 490:119543c9f674 1731
mbed_official 376:cb4d9db17537 1732 /* Set the DMA error callback */
mbed_official 490:119543c9f674 1733 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 1734
mbed_official 376:cb4d9db17537 1735 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 1736 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
mbed_official 490:119543c9f674 1737
mbed_official 376:cb4d9db17537 1738 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 376:cb4d9db17537 1739 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 376:cb4d9db17537 1740 }
mbed_official 376:cb4d9db17537 1741 break;
mbed_official 490:119543c9f674 1742
mbed_official 376:cb4d9db17537 1743 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 1744 {
mbed_official 376:cb4d9db17537 1745 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 1746 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 490:119543c9f674 1747
mbed_official 376:cb4d9db17537 1748 /* Set the DMA error callback */
mbed_official 490:119543c9f674 1749 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 1750
mbed_official 376:cb4d9db17537 1751 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 1752 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
mbed_official 490:119543c9f674 1753
mbed_official 376:cb4d9db17537 1754 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 376:cb4d9db17537 1755 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 376:cb4d9db17537 1756 }
mbed_official 376:cb4d9db17537 1757 break;
mbed_official 490:119543c9f674 1758
mbed_official 376:cb4d9db17537 1759 default:
mbed_official 376:cb4d9db17537 1760 break;
mbed_official 376:cb4d9db17537 1761 }
mbed_official 376:cb4d9db17537 1762
mbed_official 376:cb4d9db17537 1763 /* Enable the Input Capture channel */
mbed_official 376:cb4d9db17537 1764 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 490:119543c9f674 1765
mbed_official 376:cb4d9db17537 1766 /* Enable the Peripheral */
mbed_official 490:119543c9f674 1767 __HAL_TIM_ENABLE(htim);
mbed_official 490:119543c9f674 1768
mbed_official 376:cb4d9db17537 1769 /* Return function status */
mbed_official 376:cb4d9db17537 1770 return HAL_OK;
mbed_official 376:cb4d9db17537 1771 }
mbed_official 376:cb4d9db17537 1772
mbed_official 376:cb4d9db17537 1773 /**
mbed_official 376:cb4d9db17537 1774 * @brief Stops the TIM Input Capture measurement on in DMA mode.
mbed_official 490:119543c9f674 1775 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1776 * @param Channel : TIM Channels to be disabled
mbed_official 376:cb4d9db17537 1777 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1778 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1779 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1780 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 1781 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 1782 * @retval HAL status
mbed_official 376:cb4d9db17537 1783 */
mbed_official 376:cb4d9db17537 1784 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 1785 {
mbed_official 376:cb4d9db17537 1786 /* Check the parameters */
mbed_official 376:cb4d9db17537 1787 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 376:cb4d9db17537 1788 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 1789
mbed_official 376:cb4d9db17537 1790 switch (Channel)
mbed_official 376:cb4d9db17537 1791 {
mbed_official 376:cb4d9db17537 1792 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 1793 {
mbed_official 376:cb4d9db17537 1794 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 376:cb4d9db17537 1795 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 376:cb4d9db17537 1796 }
mbed_official 376:cb4d9db17537 1797 break;
mbed_official 490:119543c9f674 1798
mbed_official 376:cb4d9db17537 1799 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 1800 {
mbed_official 376:cb4d9db17537 1801 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 376:cb4d9db17537 1802 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 376:cb4d9db17537 1803 }
mbed_official 376:cb4d9db17537 1804 break;
mbed_official 490:119543c9f674 1805
mbed_official 376:cb4d9db17537 1806 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 1807 {
mbed_official 376:cb4d9db17537 1808 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 376:cb4d9db17537 1809 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 376:cb4d9db17537 1810 }
mbed_official 376:cb4d9db17537 1811 break;
mbed_official 490:119543c9f674 1812
mbed_official 376:cb4d9db17537 1813 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 1814 {
mbed_official 376:cb4d9db17537 1815 /* Disable the TIM Capture/Compare 4 DMA request */
mbed_official 376:cb4d9db17537 1816 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 376:cb4d9db17537 1817 }
mbed_official 376:cb4d9db17537 1818 break;
mbed_official 490:119543c9f674 1819
mbed_official 376:cb4d9db17537 1820 default:
mbed_official 376:cb4d9db17537 1821 break;
mbed_official 376:cb4d9db17537 1822 }
mbed_official 376:cb4d9db17537 1823
mbed_official 376:cb4d9db17537 1824 /* Disable the Input Capture channel */
mbed_official 376:cb4d9db17537 1825 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 490:119543c9f674 1826
mbed_official 376:cb4d9db17537 1827 /* Disable the Peripheral */
mbed_official 490:119543c9f674 1828 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 1829
mbed_official 376:cb4d9db17537 1830 /* Change the htim state */
mbed_official 376:cb4d9db17537 1831 htim->State = HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 1832
mbed_official 376:cb4d9db17537 1833 /* Return function status */
mbed_official 376:cb4d9db17537 1834 return HAL_OK;
mbed_official 376:cb4d9db17537 1835 }
mbed_official 376:cb4d9db17537 1836
mbed_official 376:cb4d9db17537 1837 /**
mbed_official 490:119543c9f674 1838 * @}
mbed_official 490:119543c9f674 1839 */
mbed_official 490:119543c9f674 1840
mbed_official 490:119543c9f674 1841 /** @addtogroup TIM_Exported_Functions_Group5
mbed_official 490:119543c9f674 1842 * @brief Time One Pulse functions
mbed_official 490:119543c9f674 1843 *
mbed_official 490:119543c9f674 1844 @verbatim
mbed_official 490:119543c9f674 1845 ==============================================================================
mbed_official 490:119543c9f674 1846 ##### Timer One Pulse functions #####
mbed_official 490:119543c9f674 1847 ==============================================================================
mbed_official 490:119543c9f674 1848 [..]
mbed_official 490:119543c9f674 1849 This section provides functions allowing to:
mbed_official 490:119543c9f674 1850 (+) Initialize and configure the TIM One Pulse.
mbed_official 490:119543c9f674 1851 (+) De-initialize the TIM One Pulse.
mbed_official 490:119543c9f674 1852 (+) Start the Timer One Pulse.
mbed_official 490:119543c9f674 1853 (+) Stop the Timer One Pulse.
mbed_official 490:119543c9f674 1854 (+) Start the Timer One Pulse and enable interrupt.
mbed_official 490:119543c9f674 1855 (+) Stop the Timer One Pulse and disable interrupt.
mbed_official 490:119543c9f674 1856 (+) Start the Timer One Pulse and enable DMA transfer.
mbed_official 490:119543c9f674 1857 (+) Stop the Timer One Pulse and disable DMA transfer.
mbed_official 490:119543c9f674 1858
mbed_official 490:119543c9f674 1859 @endverbatim
mbed_official 490:119543c9f674 1860 * @{
mbed_official 490:119543c9f674 1861 */
mbed_official 490:119543c9f674 1862 /**
mbed_official 490:119543c9f674 1863 * @brief Initializes the TIM One Pulse Time Base according to the specified
mbed_official 490:119543c9f674 1864 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 490:119543c9f674 1865 * @param htim: TIM OnePulse handle
mbed_official 490:119543c9f674 1866 * @param OnePulseMode: Select the One pulse mode.
mbed_official 490:119543c9f674 1867 * This parameter can be one of the following values:
mbed_official 490:119543c9f674 1868 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
mbed_official 490:119543c9f674 1869 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
mbed_official 490:119543c9f674 1870 * @retval HAL status
mbed_official 490:119543c9f674 1871 */
mbed_official 490:119543c9f674 1872 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
mbed_official 490:119543c9f674 1873 {
mbed_official 490:119543c9f674 1874 /* Check the TIM handle allocation */
mbed_official 490:119543c9f674 1875 if(htim == NULL)
mbed_official 490:119543c9f674 1876 {
mbed_official 490:119543c9f674 1877 return HAL_ERROR;
mbed_official 490:119543c9f674 1878 }
mbed_official 490:119543c9f674 1879
mbed_official 490:119543c9f674 1880 /* Check the parameters */
mbed_official 490:119543c9f674 1881 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 1882 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 490:119543c9f674 1883 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 490:119543c9f674 1884 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
mbed_official 490:119543c9f674 1885 assert_param(IS_TIM_PERIOD(htim->Init.Period));
mbed_official 490:119543c9f674 1886 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
mbed_official 490:119543c9f674 1887
mbed_official 490:119543c9f674 1888 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 490:119543c9f674 1889 {
mbed_official 490:119543c9f674 1890 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 490:119543c9f674 1891 HAL_TIM_OnePulse_MspInit(htim);
mbed_official 490:119543c9f674 1892 }
mbed_official 490:119543c9f674 1893
mbed_official 490:119543c9f674 1894 /* Set the TIM state */
mbed_official 490:119543c9f674 1895 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 1896
mbed_official 490:119543c9f674 1897 /* Configure the Time base in the One Pulse Mode */
mbed_official 490:119543c9f674 1898 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 490:119543c9f674 1899
mbed_official 490:119543c9f674 1900 /* Reset the OPM Bit */
mbed_official 490:119543c9f674 1901 htim->Instance->CR1 &= ~TIM_CR1_OPM;
mbed_official 490:119543c9f674 1902
mbed_official 490:119543c9f674 1903 /* Configure the OPM Mode */
mbed_official 490:119543c9f674 1904 htim->Instance->CR1 |= OnePulseMode;
mbed_official 490:119543c9f674 1905
mbed_official 490:119543c9f674 1906 /* Initialize the TIM state*/
mbed_official 490:119543c9f674 1907 htim->State= HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 1908
mbed_official 490:119543c9f674 1909 return HAL_OK;
mbed_official 490:119543c9f674 1910 }
mbed_official 490:119543c9f674 1911
mbed_official 490:119543c9f674 1912 /**
mbed_official 490:119543c9f674 1913 * @brief DeInitializes the TIM One Pulse
mbed_official 490:119543c9f674 1914 * @param htim: TIM One Pulse handle
mbed_official 490:119543c9f674 1915 * @retval HAL status
mbed_official 490:119543c9f674 1916 */
mbed_official 490:119543c9f674 1917 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 1918 {
mbed_official 490:119543c9f674 1919 /* Check the parameters */
mbed_official 490:119543c9f674 1920 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 1921
mbed_official 490:119543c9f674 1922 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 1923
mbed_official 490:119543c9f674 1924 /* Disable the TIM Peripheral Clock */
mbed_official 490:119543c9f674 1925 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 1926
mbed_official 490:119543c9f674 1927 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 490:119543c9f674 1928 HAL_TIM_OnePulse_MspDeInit(htim);
mbed_official 490:119543c9f674 1929
mbed_official 490:119543c9f674 1930 /* Change TIM state */
mbed_official 490:119543c9f674 1931 htim->State = HAL_TIM_STATE_RESET;
mbed_official 490:119543c9f674 1932
mbed_official 490:119543c9f674 1933 /* Release Lock */
mbed_official 490:119543c9f674 1934 __HAL_UNLOCK(htim);
mbed_official 490:119543c9f674 1935
mbed_official 490:119543c9f674 1936 return HAL_OK;
mbed_official 490:119543c9f674 1937 }
mbed_official 490:119543c9f674 1938
mbed_official 490:119543c9f674 1939 /**
mbed_official 490:119543c9f674 1940 * @brief Initializes the TIM One Pulse MSP.
mbed_official 490:119543c9f674 1941 * @param htim : TIM handle
mbed_official 490:119543c9f674 1942 * @retval None
mbed_official 490:119543c9f674 1943 */
mbed_official 490:119543c9f674 1944 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 1945 {
mbed_official 490:119543c9f674 1946 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 490:119543c9f674 1947 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
mbed_official 490:119543c9f674 1948 */
mbed_official 490:119543c9f674 1949 }
mbed_official 490:119543c9f674 1950
mbed_official 490:119543c9f674 1951 /**
mbed_official 490:119543c9f674 1952 * @brief DeInitializes TIM One Pulse MSP.
mbed_official 490:119543c9f674 1953 * @param htim : TIM handle
mbed_official 490:119543c9f674 1954 * @retval None
mbed_official 490:119543c9f674 1955 */
mbed_official 490:119543c9f674 1956 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 1957 {
mbed_official 490:119543c9f674 1958 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 490:119543c9f674 1959 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
mbed_official 490:119543c9f674 1960 */
mbed_official 490:119543c9f674 1961 }
mbed_official 490:119543c9f674 1962
mbed_official 490:119543c9f674 1963 /**
mbed_official 376:cb4d9db17537 1964 * @brief Starts the TIM One Pulse signal generation.
mbed_official 490:119543c9f674 1965 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1966 * @param OutputChannel : TIM Channels to be enabled.
mbed_official 490:119543c9f674 1967 * This parameter is not used since both channels TIM_CHANNEL_1 and
mbed_official 490:119543c9f674 1968 * TIM_CHANNEL_2 are automatically selected.
mbed_official 376:cb4d9db17537 1969 * @retval HAL status
mbed_official 376:cb4d9db17537 1970 */
mbed_official 376:cb4d9db17537 1971 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 376:cb4d9db17537 1972 {
mbed_official 490:119543c9f674 1973 /* Enable the Capture compare and the Input Capture channels
mbed_official 376:cb4d9db17537 1974 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 376:cb4d9db17537 1975 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 490:119543c9f674 1976 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 490:119543c9f674 1977 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 490:119543c9f674 1978
mbed_official 490:119543c9f674 1979 No need to enable the counter, it's enabled automatically by hardware
mbed_official 376:cb4d9db17537 1980 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 490:119543c9f674 1981
mbed_official 490:119543c9f674 1982 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 1983 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 490:119543c9f674 1984
mbed_official 376:cb4d9db17537 1985 /* Return function status */
mbed_official 376:cb4d9db17537 1986 return HAL_OK;
mbed_official 376:cb4d9db17537 1987 }
mbed_official 376:cb4d9db17537 1988
mbed_official 376:cb4d9db17537 1989 /**
mbed_official 376:cb4d9db17537 1990 * @brief Stops the TIM One Pulse signal generation.
mbed_official 490:119543c9f674 1991 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 1992 * @param OutputChannel : TIM Channels to be disable.
mbed_official 376:cb4d9db17537 1993 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 1994 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 1995 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 1996 * @retval HAL status
mbed_official 376:cb4d9db17537 1997 */
mbed_official 376:cb4d9db17537 1998 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 376:cb4d9db17537 1999 {
mbed_official 490:119543c9f674 2000 /* Disable the Capture compare and the Input Capture channels
mbed_official 376:cb4d9db17537 2001 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 376:cb4d9db17537 2002 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 490:119543c9f674 2003 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 376:cb4d9db17537 2004 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 490:119543c9f674 2005
mbed_official 490:119543c9f674 2006 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2007 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 490:119543c9f674 2008
mbed_official 376:cb4d9db17537 2009 /* Disable the Peripheral */
mbed_official 490:119543c9f674 2010 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 2011
mbed_official 376:cb4d9db17537 2012 /* Return function status */
mbed_official 376:cb4d9db17537 2013 return HAL_OK;
mbed_official 376:cb4d9db17537 2014 }
mbed_official 376:cb4d9db17537 2015
mbed_official 376:cb4d9db17537 2016 /**
mbed_official 376:cb4d9db17537 2017 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
mbed_official 490:119543c9f674 2018 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2019 * @param OutputChannel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 2020 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2021 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2022 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 2023 * @retval HAL status
mbed_official 376:cb4d9db17537 2024 */
mbed_official 376:cb4d9db17537 2025 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 376:cb4d9db17537 2026 {
mbed_official 490:119543c9f674 2027 /* Enable the Capture compare and the Input Capture channels
mbed_official 376:cb4d9db17537 2028 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 376:cb4d9db17537 2029 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 490:119543c9f674 2030 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 490:119543c9f674 2031 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 490:119543c9f674 2032
mbed_official 490:119543c9f674 2033 No need to enable the counter, it's enabled automatically by hardware
mbed_official 376:cb4d9db17537 2034 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 490:119543c9f674 2035
mbed_official 376:cb4d9db17537 2036 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 376:cb4d9db17537 2037 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 490:119543c9f674 2038
mbed_official 376:cb4d9db17537 2039 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 376:cb4d9db17537 2040 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 490:119543c9f674 2041
mbed_official 490:119543c9f674 2042 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 490:119543c9f674 2043 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 490:119543c9f674 2044
mbed_official 376:cb4d9db17537 2045 /* Return function status */
mbed_official 376:cb4d9db17537 2046 return HAL_OK;
mbed_official 376:cb4d9db17537 2047 }
mbed_official 376:cb4d9db17537 2048
mbed_official 376:cb4d9db17537 2049 /**
mbed_official 376:cb4d9db17537 2050 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
mbed_official 490:119543c9f674 2051 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2052 * @param OutputChannel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 2053 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2054 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2055 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 2056 * @retval HAL status
mbed_official 376:cb4d9db17537 2057 */
mbed_official 376:cb4d9db17537 2058 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 376:cb4d9db17537 2059 {
mbed_official 376:cb4d9db17537 2060 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 490:119543c9f674 2061 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 490:119543c9f674 2062
mbed_official 376:cb4d9db17537 2063 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 376:cb4d9db17537 2064 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 490:119543c9f674 2065
mbed_official 490:119543c9f674 2066 /* Disable the Capture compare and the Input Capture channels
mbed_official 376:cb4d9db17537 2067 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 376:cb4d9db17537 2068 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 490:119543c9f674 2069 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 490:119543c9f674 2070 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 490:119543c9f674 2071 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2072 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 490:119543c9f674 2073
mbed_official 376:cb4d9db17537 2074 /* Disable the Peripheral */
mbed_official 490:119543c9f674 2075 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 2076
mbed_official 376:cb4d9db17537 2077 /* Return function status */
mbed_official 376:cb4d9db17537 2078 return HAL_OK;
mbed_official 376:cb4d9db17537 2079 }
mbed_official 376:cb4d9db17537 2080
mbed_official 376:cb4d9db17537 2081 /**
mbed_official 490:119543c9f674 2082 * @}
mbed_official 490:119543c9f674 2083 */
mbed_official 490:119543c9f674 2084
mbed_official 490:119543c9f674 2085 /** @addtogroup TIM_Exported_Functions_Group6
mbed_official 490:119543c9f674 2086 * @brief Time Encoder functions
mbed_official 490:119543c9f674 2087 *
mbed_official 490:119543c9f674 2088 @verbatim
mbed_official 490:119543c9f674 2089 ==============================================================================
mbed_official 490:119543c9f674 2090 ##### Timer Encoder functions #####
mbed_official 490:119543c9f674 2091 ==============================================================================
mbed_official 490:119543c9f674 2092 [..]
mbed_official 490:119543c9f674 2093 This section provides functions allowing to:
mbed_official 490:119543c9f674 2094 (+) Initialize and configure the TIM Encoder.
mbed_official 490:119543c9f674 2095 (+) De-initialize the TIM Encoder.
mbed_official 490:119543c9f674 2096 (+) Start the Timer Encoder.
mbed_official 490:119543c9f674 2097 (+) Stop the Timer Encoder.
mbed_official 490:119543c9f674 2098 (+) Start the Timer Encoder and enable interrupt.
mbed_official 490:119543c9f674 2099 (+) Stop the Timer Encoder and disable interrupt.
mbed_official 490:119543c9f674 2100 (+) Start the Timer Encoder and enable DMA transfer.
mbed_official 490:119543c9f674 2101 (+) Stop the Timer Encoder and disable DMA transfer.
mbed_official 490:119543c9f674 2102
mbed_official 490:119543c9f674 2103 @endverbatim
mbed_official 490:119543c9f674 2104 * @{
mbed_official 490:119543c9f674 2105 */
mbed_official 490:119543c9f674 2106 /**
mbed_official 490:119543c9f674 2107 * @brief Initializes the TIM Encoder Interface and create the associated handle.
mbed_official 490:119543c9f674 2108 * @param htim: TIM Encoder Interface handle
mbed_official 490:119543c9f674 2109 * @param sConfig: TIM Encoder Interface configuration structure
mbed_official 490:119543c9f674 2110 * @retval HAL status
mbed_official 490:119543c9f674 2111 */
mbed_official 490:119543c9f674 2112 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
mbed_official 490:119543c9f674 2113 {
mbed_official 490:119543c9f674 2114 uint32_t tmpsmcr = 0;
mbed_official 490:119543c9f674 2115 uint32_t tmpccmr1 = 0;
mbed_official 490:119543c9f674 2116 uint32_t tmpccer = 0;
mbed_official 490:119543c9f674 2117
mbed_official 490:119543c9f674 2118 /* Check the TIM handle allocation */
mbed_official 490:119543c9f674 2119 if(htim == NULL)
mbed_official 490:119543c9f674 2120 {
mbed_official 490:119543c9f674 2121 return HAL_ERROR;
mbed_official 490:119543c9f674 2122 }
mbed_official 490:119543c9f674 2123
mbed_official 490:119543c9f674 2124 /* Check the parameters */
mbed_official 490:119543c9f674 2125 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 2126 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
mbed_official 490:119543c9f674 2127 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
mbed_official 490:119543c9f674 2128 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
mbed_official 490:119543c9f674 2129 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
mbed_official 490:119543c9f674 2130 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
mbed_official 490:119543c9f674 2131 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
mbed_official 490:119543c9f674 2132 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
mbed_official 490:119543c9f674 2133 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
mbed_official 490:119543c9f674 2134 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
mbed_official 490:119543c9f674 2135 assert_param(IS_TIM_PERIOD(htim->Init.Period));
mbed_official 490:119543c9f674 2136 assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
mbed_official 490:119543c9f674 2137
mbed_official 490:119543c9f674 2138 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 490:119543c9f674 2139 {
mbed_official 490:119543c9f674 2140 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 490:119543c9f674 2141 HAL_TIM_Encoder_MspInit(htim);
mbed_official 490:119543c9f674 2142 }
mbed_official 490:119543c9f674 2143
mbed_official 490:119543c9f674 2144 /* Set the TIM state */
mbed_official 490:119543c9f674 2145 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 2146
mbed_official 490:119543c9f674 2147 /* Reset the SMS bits */
mbed_official 490:119543c9f674 2148 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 490:119543c9f674 2149
mbed_official 490:119543c9f674 2150 /* Configure the Time base in the Encoder Mode */
mbed_official 490:119543c9f674 2151 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 490:119543c9f674 2152
mbed_official 490:119543c9f674 2153 /* Get the TIMx SMCR register value */
mbed_official 490:119543c9f674 2154 tmpsmcr = htim->Instance->SMCR;
mbed_official 490:119543c9f674 2155
mbed_official 490:119543c9f674 2156 /* Get the TIMx CCMR1 register value */
mbed_official 490:119543c9f674 2157 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 490:119543c9f674 2158
mbed_official 490:119543c9f674 2159 /* Get the TIMx CCER register value */
mbed_official 490:119543c9f674 2160 tmpccer = htim->Instance->CCER;
mbed_official 490:119543c9f674 2161
mbed_official 490:119543c9f674 2162 /* Set the encoder Mode */
mbed_official 490:119543c9f674 2163 tmpsmcr |= sConfig->EncoderMode;
mbed_official 490:119543c9f674 2164
mbed_official 490:119543c9f674 2165 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official 490:119543c9f674 2166 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
mbed_official 490:119543c9f674 2167 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
mbed_official 490:119543c9f674 2168
mbed_official 490:119543c9f674 2169 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
mbed_official 490:119543c9f674 2170 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
mbed_official 490:119543c9f674 2171 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
mbed_official 490:119543c9f674 2172 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
mbed_official 490:119543c9f674 2173 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
mbed_official 490:119543c9f674 2174
mbed_official 490:119543c9f674 2175 /* Set the TI1 and the TI2 Polarities */
mbed_official 490:119543c9f674 2176 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
mbed_official 490:119543c9f674 2177 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
mbed_official 490:119543c9f674 2178 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
mbed_official 490:119543c9f674 2179
mbed_official 490:119543c9f674 2180 /* Write to TIMx SMCR */
mbed_official 490:119543c9f674 2181 htim->Instance->SMCR = tmpsmcr;
mbed_official 490:119543c9f674 2182
mbed_official 490:119543c9f674 2183 /* Write to TIMx CCMR1 */
mbed_official 490:119543c9f674 2184 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 490:119543c9f674 2185
mbed_official 490:119543c9f674 2186 /* Write to TIMx CCER */
mbed_official 490:119543c9f674 2187 htim->Instance->CCER = tmpccer;
mbed_official 490:119543c9f674 2188
mbed_official 490:119543c9f674 2189 /* Initialize the TIM state*/
mbed_official 490:119543c9f674 2190 htim->State= HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 2191
mbed_official 490:119543c9f674 2192 return HAL_OK;
mbed_official 490:119543c9f674 2193 }
mbed_official 490:119543c9f674 2194
mbed_official 490:119543c9f674 2195 /**
mbed_official 490:119543c9f674 2196 * @brief DeInitializes the TIM Encoder interface
mbed_official 490:119543c9f674 2197 * @param htim: TIM Encoder handle
mbed_official 490:119543c9f674 2198 * @retval HAL status
mbed_official 490:119543c9f674 2199 */
mbed_official 490:119543c9f674 2200 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 2201 {
mbed_official 490:119543c9f674 2202 /* Check the parameters */
mbed_official 490:119543c9f674 2203 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 2204
mbed_official 490:119543c9f674 2205 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 2206
mbed_official 490:119543c9f674 2207 /* Disable the TIM Peripheral Clock */
mbed_official 490:119543c9f674 2208 __HAL_TIM_DISABLE(htim);
mbed_official 490:119543c9f674 2209
mbed_official 490:119543c9f674 2210 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 490:119543c9f674 2211 HAL_TIM_Encoder_MspDeInit(htim);
mbed_official 490:119543c9f674 2212
mbed_official 490:119543c9f674 2213 /* Change TIM state */
mbed_official 490:119543c9f674 2214 htim->State = HAL_TIM_STATE_RESET;
mbed_official 490:119543c9f674 2215
mbed_official 490:119543c9f674 2216 /* Release Lock */
mbed_official 490:119543c9f674 2217 __HAL_UNLOCK(htim);
mbed_official 490:119543c9f674 2218
mbed_official 490:119543c9f674 2219 return HAL_OK;
mbed_official 490:119543c9f674 2220 }
mbed_official 490:119543c9f674 2221
mbed_official 490:119543c9f674 2222
mbed_official 490:119543c9f674 2223 /**
mbed_official 490:119543c9f674 2224 * @brief Initializes the TIM Encoder Interface MSP.
mbed_official 490:119543c9f674 2225 * @param htim : TIM handle
mbed_official 490:119543c9f674 2226 * @retval None
mbed_official 490:119543c9f674 2227 */
mbed_official 490:119543c9f674 2228 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 2229 {
mbed_official 490:119543c9f674 2230 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 490:119543c9f674 2231 the HAL_TIM_Encoder_MspInit could be implemented in the user file
mbed_official 490:119543c9f674 2232 */
mbed_official 490:119543c9f674 2233 }
mbed_official 490:119543c9f674 2234
mbed_official 490:119543c9f674 2235
mbed_official 490:119543c9f674 2236 /**
mbed_official 490:119543c9f674 2237 * @brief DeInitializes TIM Encoder Interface MSP.
mbed_official 490:119543c9f674 2238 * @param htim : TIM handle
mbed_official 490:119543c9f674 2239 * @retval None
mbed_official 490:119543c9f674 2240 */
mbed_official 490:119543c9f674 2241 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 2242 {
mbed_official 490:119543c9f674 2243 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 490:119543c9f674 2244 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
mbed_official 490:119543c9f674 2245 */
mbed_official 490:119543c9f674 2246 }
mbed_official 490:119543c9f674 2247
mbed_official 490:119543c9f674 2248 /**
mbed_official 376:cb4d9db17537 2249 * @brief Starts the TIM Encoder Interface.
mbed_official 490:119543c9f674 2250 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2251 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 2252 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2253 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2254 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 490:119543c9f674 2255 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 376:cb4d9db17537 2256 * @retval HAL status
mbed_official 376:cb4d9db17537 2257 */
mbed_official 376:cb4d9db17537 2258 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 2259 {
mbed_official 376:cb4d9db17537 2260 /* Check the parameters */
mbed_official 376:cb4d9db17537 2261 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2262
mbed_official 376:cb4d9db17537 2263 /* Enable the encoder interface channels */
mbed_official 376:cb4d9db17537 2264 switch (Channel)
mbed_official 376:cb4d9db17537 2265 {
mbed_official 376:cb4d9db17537 2266 case TIM_CHANNEL_1:
mbed_official 376:cb4d9db17537 2267 {
mbed_official 376:cb4d9db17537 2268 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2269 break;
mbed_official 376:cb4d9db17537 2270 }
mbed_official 376:cb4d9db17537 2271 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 2272 {
mbed_official 376:cb4d9db17537 2273 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2274 break;
mbed_official 376:cb4d9db17537 2275 }
mbed_official 376:cb4d9db17537 2276 default :
mbed_official 376:cb4d9db17537 2277 {
mbed_official 376:cb4d9db17537 2278 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2279 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2280 break;
mbed_official 376:cb4d9db17537 2281 }
mbed_official 376:cb4d9db17537 2282 }
mbed_official 376:cb4d9db17537 2283 /* Enable the Peripheral */
mbed_official 376:cb4d9db17537 2284 __HAL_TIM_ENABLE(htim);
mbed_official 376:cb4d9db17537 2285
mbed_official 376:cb4d9db17537 2286 /* Return function status */
mbed_official 376:cb4d9db17537 2287 return HAL_OK;
mbed_official 376:cb4d9db17537 2288 }
mbed_official 376:cb4d9db17537 2289
mbed_official 376:cb4d9db17537 2290 /**
mbed_official 376:cb4d9db17537 2291 * @brief Stops the TIM Encoder Interface.
mbed_official 490:119543c9f674 2292 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2293 * @param Channel: TIM Channels to be disabled.
mbed_official 376:cb4d9db17537 2294 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2295 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2296 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 490:119543c9f674 2297 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 376:cb4d9db17537 2298 * @retval HAL status
mbed_official 376:cb4d9db17537 2299 */
mbed_official 376:cb4d9db17537 2300 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 2301 {
mbed_official 376:cb4d9db17537 2302 /* Check the parameters */
mbed_official 376:cb4d9db17537 2303 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2304
mbed_official 376:cb4d9db17537 2305 /* Disable the Input Capture channels 1 and 2
mbed_official 376:cb4d9db17537 2306 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 376:cb4d9db17537 2307 switch (Channel)
mbed_official 376:cb4d9db17537 2308 {
mbed_official 376:cb4d9db17537 2309 case TIM_CHANNEL_1:
mbed_official 376:cb4d9db17537 2310 {
mbed_official 376:cb4d9db17537 2311 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2312 break;
mbed_official 376:cb4d9db17537 2313 }
mbed_official 376:cb4d9db17537 2314 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 2315 {
mbed_official 376:cb4d9db17537 2316 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2317 break;
mbed_official 376:cb4d9db17537 2318 }
mbed_official 376:cb4d9db17537 2319 default :
mbed_official 376:cb4d9db17537 2320 {
mbed_official 376:cb4d9db17537 2321 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2322 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2323 break;
mbed_official 376:cb4d9db17537 2324 }
mbed_official 376:cb4d9db17537 2325 }
mbed_official 376:cb4d9db17537 2326 /* Disable the Peripheral */
mbed_official 376:cb4d9db17537 2327 __HAL_TIM_DISABLE(htim);
mbed_official 376:cb4d9db17537 2328
mbed_official 376:cb4d9db17537 2329 /* Return function status */
mbed_official 376:cb4d9db17537 2330 return HAL_OK;
mbed_official 376:cb4d9db17537 2331 }
mbed_official 376:cb4d9db17537 2332
mbed_official 376:cb4d9db17537 2333 /**
mbed_official 376:cb4d9db17537 2334 * @brief Starts the TIM Encoder Interface in interrupt mode.
mbed_official 490:119543c9f674 2335 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2336 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 2337 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2338 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2339 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 490:119543c9f674 2340 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 376:cb4d9db17537 2341 * @retval HAL status
mbed_official 376:cb4d9db17537 2342 */
mbed_official 376:cb4d9db17537 2343 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 2344 {
mbed_official 376:cb4d9db17537 2345 /* Check the parameters */
mbed_official 376:cb4d9db17537 2346 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2347
mbed_official 376:cb4d9db17537 2348 /* Enable the encoder interface channels */
mbed_official 376:cb4d9db17537 2349 /* Enable the capture compare Interrupts 1 and/or 2 */
mbed_official 376:cb4d9db17537 2350 switch (Channel)
mbed_official 376:cb4d9db17537 2351 {
mbed_official 376:cb4d9db17537 2352 case TIM_CHANNEL_1:
mbed_official 376:cb4d9db17537 2353 {
mbed_official 376:cb4d9db17537 2354 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2355 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 376:cb4d9db17537 2356 break;
mbed_official 376:cb4d9db17537 2357 }
mbed_official 376:cb4d9db17537 2358 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 2359 {
mbed_official 376:cb4d9db17537 2360 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2361 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 376:cb4d9db17537 2362 break;
mbed_official 376:cb4d9db17537 2363 }
mbed_official 376:cb4d9db17537 2364 default :
mbed_official 376:cb4d9db17537 2365 {
mbed_official 376:cb4d9db17537 2366 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2367 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2368 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 376:cb4d9db17537 2369 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 376:cb4d9db17537 2370 break;
mbed_official 376:cb4d9db17537 2371 }
mbed_official 376:cb4d9db17537 2372 }
mbed_official 376:cb4d9db17537 2373
mbed_official 376:cb4d9db17537 2374 /* Enable the Peripheral */
mbed_official 376:cb4d9db17537 2375 __HAL_TIM_ENABLE(htim);
mbed_official 376:cb4d9db17537 2376
mbed_official 376:cb4d9db17537 2377 /* Return function status */
mbed_official 376:cb4d9db17537 2378 return HAL_OK;
mbed_official 376:cb4d9db17537 2379 }
mbed_official 376:cb4d9db17537 2380
mbed_official 376:cb4d9db17537 2381 /**
mbed_official 376:cb4d9db17537 2382 * @brief Stops the TIM Encoder Interface in interrupt mode.
mbed_official 490:119543c9f674 2383 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2384 * @param Channel: TIM Channels to be disabled.
mbed_official 376:cb4d9db17537 2385 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2386 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2387 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 490:119543c9f674 2388 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 376:cb4d9db17537 2389 * @retval HAL status
mbed_official 376:cb4d9db17537 2390 */
mbed_official 376:cb4d9db17537 2391 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 2392 {
mbed_official 376:cb4d9db17537 2393 /* Check the parameters */
mbed_official 376:cb4d9db17537 2394 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2395
mbed_official 376:cb4d9db17537 2396 /* Disable the Input Capture channels 1 and 2
mbed_official 376:cb4d9db17537 2397 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 376:cb4d9db17537 2398 if(Channel == TIM_CHANNEL_1)
mbed_official 376:cb4d9db17537 2399 {
mbed_official 376:cb4d9db17537 2400 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2401
mbed_official 376:cb4d9db17537 2402 /* Disable the capture compare Interrupts 1 */
mbed_official 376:cb4d9db17537 2403 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 376:cb4d9db17537 2404 }
mbed_official 376:cb4d9db17537 2405 else if(Channel == TIM_CHANNEL_2)
mbed_official 376:cb4d9db17537 2406 {
mbed_official 376:cb4d9db17537 2407 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2408
mbed_official 376:cb4d9db17537 2409 /* Disable the capture compare Interrupts 2 */
mbed_official 376:cb4d9db17537 2410 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 376:cb4d9db17537 2411 }
mbed_official 376:cb4d9db17537 2412 else
mbed_official 376:cb4d9db17537 2413 {
mbed_official 376:cb4d9db17537 2414 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2415 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2416
mbed_official 376:cb4d9db17537 2417 /* Disable the capture compare Interrupts 1 and 2 */
mbed_official 376:cb4d9db17537 2418 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 376:cb4d9db17537 2419 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 376:cb4d9db17537 2420 }
mbed_official 376:cb4d9db17537 2421
mbed_official 376:cb4d9db17537 2422 /* Disable the Peripheral */
mbed_official 376:cb4d9db17537 2423 __HAL_TIM_DISABLE(htim);
mbed_official 376:cb4d9db17537 2424
mbed_official 376:cb4d9db17537 2425 /* Change the htim state */
mbed_official 376:cb4d9db17537 2426 htim->State = HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 2427
mbed_official 376:cb4d9db17537 2428 /* Return function status */
mbed_official 376:cb4d9db17537 2429 return HAL_OK;
mbed_official 376:cb4d9db17537 2430 }
mbed_official 376:cb4d9db17537 2431
mbed_official 376:cb4d9db17537 2432 /**
mbed_official 376:cb4d9db17537 2433 * @brief Starts the TIM Encoder Interface in DMA mode.
mbed_official 490:119543c9f674 2434 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2435 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 2436 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2437 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2438 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 490:119543c9f674 2439 * @arg TIM_CHANNEL_ALL : TIM Channel 1 and 2 selected
mbed_official 376:cb4d9db17537 2440 * @param pData1: The destination Buffer address for IC1.
mbed_official 376:cb4d9db17537 2441 * @param pData2: The destination Buffer address for IC2.
mbed_official 376:cb4d9db17537 2442 * @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official 376:cb4d9db17537 2443 * @retval HAL status
mbed_official 376:cb4d9db17537 2444 */
mbed_official 376:cb4d9db17537 2445 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
mbed_official 376:cb4d9db17537 2446 {
mbed_official 376:cb4d9db17537 2447 /* Check the parameters */
mbed_official 376:cb4d9db17537 2448 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2449
mbed_official 376:cb4d9db17537 2450 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 376:cb4d9db17537 2451 {
mbed_official 376:cb4d9db17537 2452 return HAL_BUSY;
mbed_official 376:cb4d9db17537 2453 }
mbed_official 376:cb4d9db17537 2454 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 376:cb4d9db17537 2455 {
mbed_official 376:cb4d9db17537 2456 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
mbed_official 376:cb4d9db17537 2457 {
mbed_official 376:cb4d9db17537 2458 return HAL_ERROR;
mbed_official 376:cb4d9db17537 2459 }
mbed_official 376:cb4d9db17537 2460 else
mbed_official 376:cb4d9db17537 2461 {
mbed_official 376:cb4d9db17537 2462 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 2463 }
mbed_official 376:cb4d9db17537 2464 }
mbed_official 376:cb4d9db17537 2465
mbed_official 376:cb4d9db17537 2466 switch (Channel)
mbed_official 376:cb4d9db17537 2467 {
mbed_official 376:cb4d9db17537 2468 case TIM_CHANNEL_1:
mbed_official 376:cb4d9db17537 2469 {
mbed_official 376:cb4d9db17537 2470 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 2471 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 376:cb4d9db17537 2472
mbed_official 376:cb4d9db17537 2473 /* Set the DMA error callback */
mbed_official 490:119543c9f674 2474 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 2475
mbed_official 376:cb4d9db17537 2476 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 2477 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
mbed_official 376:cb4d9db17537 2478
mbed_official 376:cb4d9db17537 2479 /* Enable the TIM Input Capture DMA request */
mbed_official 376:cb4d9db17537 2480 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 376:cb4d9db17537 2481
mbed_official 376:cb4d9db17537 2482 /* Enable the Peripheral */
mbed_official 376:cb4d9db17537 2483 __HAL_TIM_ENABLE(htim);
mbed_official 376:cb4d9db17537 2484
mbed_official 376:cb4d9db17537 2485 /* Enable the Capture compare channel */
mbed_official 376:cb4d9db17537 2486 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2487 }
mbed_official 376:cb4d9db17537 2488 break;
mbed_official 376:cb4d9db17537 2489
mbed_official 376:cb4d9db17537 2490 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 2491 {
mbed_official 376:cb4d9db17537 2492 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 2493 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 376:cb4d9db17537 2494
mbed_official 376:cb4d9db17537 2495 /* Set the DMA error callback */
mbed_official 490:119543c9f674 2496 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
mbed_official 376:cb4d9db17537 2497 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 2498 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 376:cb4d9db17537 2499
mbed_official 376:cb4d9db17537 2500 /* Enable the TIM Input Capture DMA request */
mbed_official 376:cb4d9db17537 2501 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 376:cb4d9db17537 2502
mbed_official 376:cb4d9db17537 2503 /* Enable the Peripheral */
mbed_official 376:cb4d9db17537 2504 __HAL_TIM_ENABLE(htim);
mbed_official 376:cb4d9db17537 2505
mbed_official 376:cb4d9db17537 2506 /* Enable the Capture compare channel */
mbed_official 376:cb4d9db17537 2507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2508 }
mbed_official 376:cb4d9db17537 2509 break;
mbed_official 376:cb4d9db17537 2510
mbed_official 376:cb4d9db17537 2511 case TIM_CHANNEL_ALL:
mbed_official 376:cb4d9db17537 2512 {
mbed_official 376:cb4d9db17537 2513 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 2514 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 376:cb4d9db17537 2515
mbed_official 376:cb4d9db17537 2516 /* Set the DMA error callback */
mbed_official 490:119543c9f674 2517 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 2518
mbed_official 376:cb4d9db17537 2519 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 2520 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
mbed_official 376:cb4d9db17537 2521
mbed_official 376:cb4d9db17537 2522 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 2523 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 376:cb4d9db17537 2524
mbed_official 376:cb4d9db17537 2525 /* Set the DMA error callback */
mbed_official 490:119543c9f674 2526 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 2527
mbed_official 376:cb4d9db17537 2528 /* Enable the DMA Stream */
mbed_official 376:cb4d9db17537 2529 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 376:cb4d9db17537 2530
mbed_official 376:cb4d9db17537 2531 /* Enable the Peripheral */
mbed_official 376:cb4d9db17537 2532 __HAL_TIM_ENABLE(htim);
mbed_official 376:cb4d9db17537 2533
mbed_official 376:cb4d9db17537 2534 /* Enable the Capture compare channel */
mbed_official 376:cb4d9db17537 2535 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2536 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 376:cb4d9db17537 2537
mbed_official 376:cb4d9db17537 2538 /* Enable the TIM Input Capture DMA request */
mbed_official 376:cb4d9db17537 2539 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 376:cb4d9db17537 2540 /* Enable the TIM Input Capture DMA request */
mbed_official 376:cb4d9db17537 2541 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 376:cb4d9db17537 2542 }
mbed_official 376:cb4d9db17537 2543 break;
mbed_official 376:cb4d9db17537 2544
mbed_official 376:cb4d9db17537 2545 default:
mbed_official 376:cb4d9db17537 2546 break;
mbed_official 376:cb4d9db17537 2547 }
mbed_official 376:cb4d9db17537 2548 /* Return function status */
mbed_official 376:cb4d9db17537 2549 return HAL_OK;
mbed_official 376:cb4d9db17537 2550 }
mbed_official 376:cb4d9db17537 2551
mbed_official 376:cb4d9db17537 2552 /**
mbed_official 376:cb4d9db17537 2553 * @brief Stops the TIM Encoder Interface in DMA mode.
mbed_official 490:119543c9f674 2554 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2555 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 2556 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2557 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2558 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 490:119543c9f674 2559 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 376:cb4d9db17537 2560 * @retval HAL status
mbed_official 376:cb4d9db17537 2561 */
mbed_official 376:cb4d9db17537 2562 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 2563 {
mbed_official 376:cb4d9db17537 2564 /* Check the parameters */
mbed_official 376:cb4d9db17537 2565 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2566
mbed_official 376:cb4d9db17537 2567 /* Disable the Input Capture channels 1 and 2
mbed_official 376:cb4d9db17537 2568 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 376:cb4d9db17537 2569 if(Channel == TIM_CHANNEL_1)
mbed_official 376:cb4d9db17537 2570 {
mbed_official 376:cb4d9db17537 2571 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2572
mbed_official 376:cb4d9db17537 2573 /* Disable the capture compare DMA Request 1 */
mbed_official 376:cb4d9db17537 2574 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 376:cb4d9db17537 2575 }
mbed_official 376:cb4d9db17537 2576 else if(Channel == TIM_CHANNEL_2)
mbed_official 376:cb4d9db17537 2577 {
mbed_official 376:cb4d9db17537 2578 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2579
mbed_official 376:cb4d9db17537 2580 /* Disable the capture compare DMA Request 2 */
mbed_official 376:cb4d9db17537 2581 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 376:cb4d9db17537 2582 }
mbed_official 376:cb4d9db17537 2583 else
mbed_official 376:cb4d9db17537 2584 {
mbed_official 376:cb4d9db17537 2585 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2586 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 376:cb4d9db17537 2587
mbed_official 376:cb4d9db17537 2588 /* Disable the capture compare DMA Request 1 and 2 */
mbed_official 376:cb4d9db17537 2589 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 376:cb4d9db17537 2590 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 376:cb4d9db17537 2591 }
mbed_official 376:cb4d9db17537 2592
mbed_official 376:cb4d9db17537 2593 /* Disable the Peripheral */
mbed_official 376:cb4d9db17537 2594 __HAL_TIM_DISABLE(htim);
mbed_official 376:cb4d9db17537 2595
mbed_official 376:cb4d9db17537 2596 /* Change the htim state */
mbed_official 376:cb4d9db17537 2597 htim->State = HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 2598
mbed_official 376:cb4d9db17537 2599 /* Return function status */
mbed_official 376:cb4d9db17537 2600 return HAL_OK;
mbed_official 376:cb4d9db17537 2601 }
mbed_official 376:cb4d9db17537 2602
mbed_official 376:cb4d9db17537 2603 /**
mbed_official 376:cb4d9db17537 2604 * @}
mbed_official 376:cb4d9db17537 2605 */
mbed_official 376:cb4d9db17537 2606
mbed_official 490:119543c9f674 2607 /** @addtogroup TIM_Exported_Functions_Group7
mbed_official 490:119543c9f674 2608 * @brief IRQ handler management
mbed_official 490:119543c9f674 2609 *
mbed_official 490:119543c9f674 2610 @verbatim
mbed_official 490:119543c9f674 2611 ==============================================================================
mbed_official 490:119543c9f674 2612 ##### IRQ handler management #####
mbed_official 490:119543c9f674 2613 ==============================================================================
mbed_official 490:119543c9f674 2614 [..]
mbed_official 490:119543c9f674 2615 This section provides Timer IRQ handler function.
mbed_official 490:119543c9f674 2616
mbed_official 490:119543c9f674 2617 @endverbatim
mbed_official 490:119543c9f674 2618 * @{
mbed_official 490:119543c9f674 2619 */
mbed_official 490:119543c9f674 2620 /**
mbed_official 490:119543c9f674 2621 * @brief This function handles TIM interrupts requests.
mbed_official 490:119543c9f674 2622 * @param htim: TIM handle
mbed_official 490:119543c9f674 2623 * @retval None
mbed_official 490:119543c9f674 2624 */
mbed_official 490:119543c9f674 2625 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
mbed_official 490:119543c9f674 2626 {
mbed_official 490:119543c9f674 2627 /* Capture compare 1 event */
mbed_official 490:119543c9f674 2628 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
mbed_official 490:119543c9f674 2629 {
mbed_official 490:119543c9f674 2630 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
mbed_official 490:119543c9f674 2631 {
mbed_official 490:119543c9f674 2632 {
mbed_official 490:119543c9f674 2633 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
mbed_official 490:119543c9f674 2634 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 490:119543c9f674 2635
mbed_official 490:119543c9f674 2636 /* Input capture event */
mbed_official 490:119543c9f674 2637 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
mbed_official 490:119543c9f674 2638 {
mbed_official 490:119543c9f674 2639 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 490:119543c9f674 2640 }
mbed_official 490:119543c9f674 2641 /* Output compare event */
mbed_official 490:119543c9f674 2642 else
mbed_official 490:119543c9f674 2643 {
mbed_official 490:119543c9f674 2644 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 490:119543c9f674 2645 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 490:119543c9f674 2646 }
mbed_official 490:119543c9f674 2647 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 490:119543c9f674 2648 }
mbed_official 490:119543c9f674 2649 }
mbed_official 490:119543c9f674 2650 }
mbed_official 490:119543c9f674 2651 /* Capture compare 2 event */
mbed_official 490:119543c9f674 2652 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
mbed_official 490:119543c9f674 2653 {
mbed_official 490:119543c9f674 2654 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
mbed_official 490:119543c9f674 2655 {
mbed_official 490:119543c9f674 2656 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
mbed_official 490:119543c9f674 2657 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 490:119543c9f674 2658 /* Input capture event */
mbed_official 490:119543c9f674 2659 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
mbed_official 490:119543c9f674 2660 {
mbed_official 490:119543c9f674 2661 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 490:119543c9f674 2662 }
mbed_official 490:119543c9f674 2663 /* Output compare event */
mbed_official 490:119543c9f674 2664 else
mbed_official 490:119543c9f674 2665 {
mbed_official 490:119543c9f674 2666 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 490:119543c9f674 2667 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 490:119543c9f674 2668 }
mbed_official 490:119543c9f674 2669 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 490:119543c9f674 2670 }
mbed_official 490:119543c9f674 2671 }
mbed_official 490:119543c9f674 2672 /* Capture compare 3 event */
mbed_official 490:119543c9f674 2673 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
mbed_official 490:119543c9f674 2674 {
mbed_official 490:119543c9f674 2675 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
mbed_official 490:119543c9f674 2676 {
mbed_official 490:119543c9f674 2677 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
mbed_official 490:119543c9f674 2678 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 490:119543c9f674 2679 /* Input capture event */
mbed_official 490:119543c9f674 2680 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
mbed_official 490:119543c9f674 2681 {
mbed_official 490:119543c9f674 2682 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 490:119543c9f674 2683 }
mbed_official 490:119543c9f674 2684 /* Output compare event */
mbed_official 490:119543c9f674 2685 else
mbed_official 490:119543c9f674 2686 {
mbed_official 490:119543c9f674 2687 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 490:119543c9f674 2688 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 490:119543c9f674 2689 }
mbed_official 490:119543c9f674 2690 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 490:119543c9f674 2691 }
mbed_official 490:119543c9f674 2692 }
mbed_official 490:119543c9f674 2693 /* Capture compare 4 event */
mbed_official 490:119543c9f674 2694 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
mbed_official 490:119543c9f674 2695 {
mbed_official 490:119543c9f674 2696 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
mbed_official 490:119543c9f674 2697 {
mbed_official 490:119543c9f674 2698 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
mbed_official 490:119543c9f674 2699 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 490:119543c9f674 2700 /* Input capture event */
mbed_official 490:119543c9f674 2701 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
mbed_official 490:119543c9f674 2702 {
mbed_official 490:119543c9f674 2703 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 490:119543c9f674 2704 }
mbed_official 490:119543c9f674 2705 /* Output compare event */
mbed_official 490:119543c9f674 2706 else
mbed_official 490:119543c9f674 2707 {
mbed_official 490:119543c9f674 2708 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 490:119543c9f674 2709 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 490:119543c9f674 2710 }
mbed_official 490:119543c9f674 2711 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 490:119543c9f674 2712 }
mbed_official 490:119543c9f674 2713 }
mbed_official 490:119543c9f674 2714 /* TIM Update event */
mbed_official 490:119543c9f674 2715 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
mbed_official 490:119543c9f674 2716 {
mbed_official 490:119543c9f674 2717 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
mbed_official 490:119543c9f674 2718 {
mbed_official 490:119543c9f674 2719 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
mbed_official 490:119543c9f674 2720 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 490:119543c9f674 2721 }
mbed_official 490:119543c9f674 2722 }
mbed_official 490:119543c9f674 2723 /* TIM Trigger detection event */
mbed_official 490:119543c9f674 2724 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
mbed_official 490:119543c9f674 2725 {
mbed_official 490:119543c9f674 2726 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
mbed_official 490:119543c9f674 2727 {
mbed_official 490:119543c9f674 2728 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
mbed_official 490:119543c9f674 2729 HAL_TIM_TriggerCallback(htim);
mbed_official 490:119543c9f674 2730 }
mbed_official 490:119543c9f674 2731 }
mbed_official 490:119543c9f674 2732 }
mbed_official 490:119543c9f674 2733
mbed_official 490:119543c9f674 2734 /**
mbed_official 490:119543c9f674 2735 * @}
mbed_official 490:119543c9f674 2736 */
mbed_official 490:119543c9f674 2737
mbed_official 490:119543c9f674 2738 /** @addtogroup TIM_Exported_Functions_Group8
mbed_official 490:119543c9f674 2739 * @brief Peripheral Control functions
mbed_official 376:cb4d9db17537 2740 *
mbed_official 376:cb4d9db17537 2741 @verbatim
mbed_official 376:cb4d9db17537 2742 ==============================================================================
mbed_official 376:cb4d9db17537 2743 ##### Peripheral Control functions #####
mbed_official 376:cb4d9db17537 2744 ==============================================================================
mbed_official 376:cb4d9db17537 2745 [..]
mbed_official 376:cb4d9db17537 2746 This section provides functions allowing to:
mbed_official 490:119543c9f674 2747 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
mbed_official 376:cb4d9db17537 2748 (+) Configure External Clock source.
mbed_official 376:cb4d9db17537 2749 (+) Configure Master and the Slave synchronization.
mbed_official 376:cb4d9db17537 2750 (+) Configure the DMA Burst Mode.
mbed_official 490:119543c9f674 2751
mbed_official 376:cb4d9db17537 2752 @endverbatim
mbed_official 376:cb4d9db17537 2753 * @{
mbed_official 376:cb4d9db17537 2754 */
mbed_official 376:cb4d9db17537 2755 /**
mbed_official 376:cb4d9db17537 2756 * @brief Initializes the TIM Output Compare Channels according to the specified
mbed_official 376:cb4d9db17537 2757 * parameters in the TIM_OC_InitTypeDef.
mbed_official 490:119543c9f674 2758 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2759 * @param sConfig: TIM Output Compare configuration structure
mbed_official 376:cb4d9db17537 2760 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 2761 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2762 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2763 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 2764 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 490:119543c9f674 2765 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 2766 * @retval HAL status
mbed_official 376:cb4d9db17537 2767 */
mbed_official 376:cb4d9db17537 2768 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 376:cb4d9db17537 2769 {
mbed_official 376:cb4d9db17537 2770 /* Check the parameters */
mbed_official 376:cb4d9db17537 2771 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 376:cb4d9db17537 2772 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
mbed_official 376:cb4d9db17537 2773 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 376:cb4d9db17537 2774
mbed_official 376:cb4d9db17537 2775 /* Check input state */
mbed_official 490:119543c9f674 2776 __HAL_LOCK(htim);
mbed_official 490:119543c9f674 2777
mbed_official 376:cb4d9db17537 2778 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 2779
mbed_official 376:cb4d9db17537 2780 switch (Channel)
mbed_official 376:cb4d9db17537 2781 {
mbed_official 376:cb4d9db17537 2782 case TIM_CHANNEL_1:
mbed_official 376:cb4d9db17537 2783 {
mbed_official 376:cb4d9db17537 2784 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2785 /* Configure the TIM Channel 1 in Output Compare */
mbed_official 376:cb4d9db17537 2786 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 376:cb4d9db17537 2787 }
mbed_official 376:cb4d9db17537 2788 break;
mbed_official 376:cb4d9db17537 2789
mbed_official 376:cb4d9db17537 2790 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 2791 {
mbed_official 376:cb4d9db17537 2792 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2793 /* Configure the TIM Channel 2 in Output Compare */
mbed_official 376:cb4d9db17537 2794 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 376:cb4d9db17537 2795 }
mbed_official 376:cb4d9db17537 2796 break;
mbed_official 376:cb4d9db17537 2797
mbed_official 376:cb4d9db17537 2798 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 2799 {
mbed_official 376:cb4d9db17537 2800 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2801 /* Configure the TIM Channel 3 in Output Compare */
mbed_official 376:cb4d9db17537 2802 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 376:cb4d9db17537 2803 }
mbed_official 376:cb4d9db17537 2804 break;
mbed_official 376:cb4d9db17537 2805
mbed_official 376:cb4d9db17537 2806 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 2807 {
mbed_official 376:cb4d9db17537 2808 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2809 /* Configure the TIM Channel 4 in Output Compare */
mbed_official 376:cb4d9db17537 2810 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 376:cb4d9db17537 2811 }
mbed_official 376:cb4d9db17537 2812 break;
mbed_official 376:cb4d9db17537 2813
mbed_official 376:cb4d9db17537 2814 default:
mbed_official 376:cb4d9db17537 2815 break;
mbed_official 376:cb4d9db17537 2816 }
mbed_official 376:cb4d9db17537 2817 htim->State = HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 2818
mbed_official 490:119543c9f674 2819 __HAL_UNLOCK(htim);
mbed_official 376:cb4d9db17537 2820
mbed_official 376:cb4d9db17537 2821 return HAL_OK;
mbed_official 376:cb4d9db17537 2822 }
mbed_official 376:cb4d9db17537 2823
mbed_official 376:cb4d9db17537 2824 /**
mbed_official 376:cb4d9db17537 2825 * @brief Initializes the TIM Input Capture Channels according to the specified
mbed_official 376:cb4d9db17537 2826 * parameters in the TIM_IC_InitTypeDef.
mbed_official 490:119543c9f674 2827 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2828 * @param sConfig: TIM Input Capture configuration structure
mbed_official 376:cb4d9db17537 2829 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 2830 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2831 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2832 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 2833 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 490:119543c9f674 2834 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 2835 * @retval HAL status
mbed_official 376:cb4d9db17537 2836 */
mbed_official 376:cb4d9db17537 2837 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 376:cb4d9db17537 2838 {
mbed_official 376:cb4d9db17537 2839 /* Check the parameters */
mbed_official 376:cb4d9db17537 2840 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2841 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
mbed_official 376:cb4d9db17537 2842 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
mbed_official 376:cb4d9db17537 2843 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
mbed_official 376:cb4d9db17537 2844 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
mbed_official 490:119543c9f674 2845
mbed_official 376:cb4d9db17537 2846 __HAL_LOCK(htim);
mbed_official 490:119543c9f674 2847
mbed_official 376:cb4d9db17537 2848 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 2849
mbed_official 376:cb4d9db17537 2850 if (Channel == TIM_CHANNEL_1)
mbed_official 376:cb4d9db17537 2851 {
mbed_official 376:cb4d9db17537 2852 /* TI1 Configuration */
mbed_official 376:cb4d9db17537 2853 TIM_TI1_SetConfig(htim->Instance,
mbed_official 376:cb4d9db17537 2854 sConfig->ICPolarity,
mbed_official 376:cb4d9db17537 2855 sConfig->ICSelection,
mbed_official 376:cb4d9db17537 2856 sConfig->ICFilter);
mbed_official 490:119543c9f674 2857
mbed_official 376:cb4d9db17537 2858 /* Reset the IC1PSC Bits */
mbed_official 376:cb4d9db17537 2859 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official 376:cb4d9db17537 2860
mbed_official 376:cb4d9db17537 2861 /* Set the IC1PSC value */
mbed_official 376:cb4d9db17537 2862 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
mbed_official 376:cb4d9db17537 2863 }
mbed_official 376:cb4d9db17537 2864 else if (Channel == TIM_CHANNEL_2)
mbed_official 376:cb4d9db17537 2865 {
mbed_official 376:cb4d9db17537 2866 /* TI2 Configuration */
mbed_official 376:cb4d9db17537 2867 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2868
mbed_official 490:119543c9f674 2869 TIM_TI2_SetConfig(htim->Instance,
mbed_official 376:cb4d9db17537 2870 sConfig->ICPolarity,
mbed_official 376:cb4d9db17537 2871 sConfig->ICSelection,
mbed_official 376:cb4d9db17537 2872 sConfig->ICFilter);
mbed_official 376:cb4d9db17537 2873
mbed_official 376:cb4d9db17537 2874 /* Reset the IC2PSC Bits */
mbed_official 376:cb4d9db17537 2875 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official 376:cb4d9db17537 2876
mbed_official 376:cb4d9db17537 2877 /* Set the IC2PSC value */
mbed_official 376:cb4d9db17537 2878 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
mbed_official 376:cb4d9db17537 2879 }
mbed_official 376:cb4d9db17537 2880 else if (Channel == TIM_CHANNEL_3)
mbed_official 376:cb4d9db17537 2881 {
mbed_official 376:cb4d9db17537 2882 /* TI3 Configuration */
mbed_official 376:cb4d9db17537 2883 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 2884
mbed_official 490:119543c9f674 2885 TIM_TI3_SetConfig(htim->Instance,
mbed_official 376:cb4d9db17537 2886 sConfig->ICPolarity,
mbed_official 376:cb4d9db17537 2887 sConfig->ICSelection,
mbed_official 376:cb4d9db17537 2888 sConfig->ICFilter);
mbed_official 376:cb4d9db17537 2889
mbed_official 376:cb4d9db17537 2890 /* Reset the IC3PSC Bits */
mbed_official 376:cb4d9db17537 2891 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
mbed_official 376:cb4d9db17537 2892
mbed_official 376:cb4d9db17537 2893 /* Set the IC3PSC value */
mbed_official 376:cb4d9db17537 2894 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
mbed_official 376:cb4d9db17537 2895 }
mbed_official 376:cb4d9db17537 2896 else
mbed_official 376:cb4d9db17537 2897 {
mbed_official 376:cb4d9db17537 2898 /* TI4 Configuration */
mbed_official 376:cb4d9db17537 2899 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 2900
mbed_official 490:119543c9f674 2901 TIM_TI4_SetConfig(htim->Instance,
mbed_official 376:cb4d9db17537 2902 sConfig->ICPolarity,
mbed_official 376:cb4d9db17537 2903 sConfig->ICSelection,
mbed_official 376:cb4d9db17537 2904 sConfig->ICFilter);
mbed_official 490:119543c9f674 2905
mbed_official 376:cb4d9db17537 2906 /* Reset the IC4PSC Bits */
mbed_official 376:cb4d9db17537 2907 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
mbed_official 376:cb4d9db17537 2908
mbed_official 376:cb4d9db17537 2909 /* Set the IC4PSC value */
mbed_official 376:cb4d9db17537 2910 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
mbed_official 376:cb4d9db17537 2911 }
mbed_official 490:119543c9f674 2912
mbed_official 376:cb4d9db17537 2913 htim->State = HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 2914
mbed_official 376:cb4d9db17537 2915 __HAL_UNLOCK(htim);
mbed_official 490:119543c9f674 2916
mbed_official 490:119543c9f674 2917 return HAL_OK;
mbed_official 376:cb4d9db17537 2918 }
mbed_official 376:cb4d9db17537 2919
mbed_official 376:cb4d9db17537 2920 /**
mbed_official 376:cb4d9db17537 2921 * @brief Initializes the TIM PWM channels according to the specified
mbed_official 376:cb4d9db17537 2922 * parameters in the TIM_OC_InitTypeDef.
mbed_official 490:119543c9f674 2923 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 2924 * @param sConfig: TIM PWM configuration structure
mbed_official 376:cb4d9db17537 2925 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 2926 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 2927 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 2928 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 2929 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 2930 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 2931 * @retval HAL status
mbed_official 376:cb4d9db17537 2932 */
mbed_official 376:cb4d9db17537 2933 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 376:cb4d9db17537 2934 {
mbed_official 376:cb4d9db17537 2935 __HAL_LOCK(htim);
mbed_official 490:119543c9f674 2936
mbed_official 490:119543c9f674 2937 /* Check the parameters */
mbed_official 490:119543c9f674 2938 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 376:cb4d9db17537 2939 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
mbed_official 376:cb4d9db17537 2940 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 490:119543c9f674 2941 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
mbed_official 376:cb4d9db17537 2942
mbed_official 376:cb4d9db17537 2943 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 2944
mbed_official 376:cb4d9db17537 2945 switch (Channel)
mbed_official 376:cb4d9db17537 2946 {
mbed_official 376:cb4d9db17537 2947 case TIM_CHANNEL_1:
mbed_official 376:cb4d9db17537 2948 {
mbed_official 376:cb4d9db17537 2949 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2950 /* Configure the Channel 1 in PWM mode */
mbed_official 376:cb4d9db17537 2951 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 490:119543c9f674 2952
mbed_official 376:cb4d9db17537 2953 /* Set the Preload enable bit for channel1 */
mbed_official 376:cb4d9db17537 2954 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
mbed_official 490:119543c9f674 2955
mbed_official 376:cb4d9db17537 2956 /* Configure the Output Fast mode */
mbed_official 376:cb4d9db17537 2957 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
mbed_official 376:cb4d9db17537 2958 htim->Instance->CCMR1 |= sConfig->OCFastMode;
mbed_official 376:cb4d9db17537 2959 }
mbed_official 376:cb4d9db17537 2960 break;
mbed_official 490:119543c9f674 2961
mbed_official 376:cb4d9db17537 2962 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 2963 {
mbed_official 376:cb4d9db17537 2964 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2965 /* Configure the Channel 2 in PWM mode */
mbed_official 376:cb4d9db17537 2966 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 490:119543c9f674 2967
mbed_official 376:cb4d9db17537 2968 /* Set the Preload enable bit for channel2 */
mbed_official 376:cb4d9db17537 2969 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
mbed_official 490:119543c9f674 2970
mbed_official 376:cb4d9db17537 2971 /* Configure the Output Fast mode */
mbed_official 376:cb4d9db17537 2972 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
mbed_official 376:cb4d9db17537 2973 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
mbed_official 376:cb4d9db17537 2974 }
mbed_official 376:cb4d9db17537 2975 break;
mbed_official 490:119543c9f674 2976
mbed_official 376:cb4d9db17537 2977 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 2978 {
mbed_official 376:cb4d9db17537 2979 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2980 /* Configure the Channel 3 in PWM mode */
mbed_official 376:cb4d9db17537 2981 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 490:119543c9f674 2982
mbed_official 376:cb4d9db17537 2983 /* Set the Preload enable bit for channel3 */
mbed_official 376:cb4d9db17537 2984 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
mbed_official 490:119543c9f674 2985
mbed_official 376:cb4d9db17537 2986 /* Configure the Output Fast mode */
mbed_official 376:cb4d9db17537 2987 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
mbed_official 490:119543c9f674 2988 htim->Instance->CCMR2 |= sConfig->OCFastMode;
mbed_official 376:cb4d9db17537 2989 }
mbed_official 376:cb4d9db17537 2990 break;
mbed_official 490:119543c9f674 2991
mbed_official 376:cb4d9db17537 2992 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 2993 {
mbed_official 376:cb4d9db17537 2994 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 2995 /* Configure the Channel 4 in PWM mode */
mbed_official 376:cb4d9db17537 2996 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 490:119543c9f674 2997
mbed_official 376:cb4d9db17537 2998 /* Set the Preload enable bit for channel4 */
mbed_official 376:cb4d9db17537 2999 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
mbed_official 490:119543c9f674 3000
mbed_official 376:cb4d9db17537 3001 /* Configure the Output Fast mode */
mbed_official 376:cb4d9db17537 3002 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
mbed_official 490:119543c9f674 3003 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
mbed_official 376:cb4d9db17537 3004 }
mbed_official 376:cb4d9db17537 3005 break;
mbed_official 490:119543c9f674 3006
mbed_official 376:cb4d9db17537 3007 default:
mbed_official 490:119543c9f674 3008 break;
mbed_official 376:cb4d9db17537 3009 }
mbed_official 376:cb4d9db17537 3010
mbed_official 376:cb4d9db17537 3011 htim->State = HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 3012
mbed_official 376:cb4d9db17537 3013 __HAL_UNLOCK(htim);
mbed_official 490:119543c9f674 3014
mbed_official 376:cb4d9db17537 3015 return HAL_OK;
mbed_official 376:cb4d9db17537 3016 }
mbed_official 376:cb4d9db17537 3017
mbed_official 376:cb4d9db17537 3018 /**
mbed_official 376:cb4d9db17537 3019 * @brief Initializes the TIM One Pulse Channels according to the specified
mbed_official 376:cb4d9db17537 3020 * parameters in the TIM_OnePulse_InitTypeDef.
mbed_official 490:119543c9f674 3021 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3022 * @param sConfig: TIM One Pulse configuration structure
mbed_official 376:cb4d9db17537 3023 * @param OutputChannel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 3024 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 3025 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 3026 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 3027 * @param InputChannel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 3028 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 3029 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 3030 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 3031 * @retval HAL status
mbed_official 376:cb4d9db17537 3032 */
mbed_official 376:cb4d9db17537 3033 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
mbed_official 376:cb4d9db17537 3034 {
mbed_official 376:cb4d9db17537 3035 TIM_OC_InitTypeDef temp1;
mbed_official 490:119543c9f674 3036
mbed_official 376:cb4d9db17537 3037 /* Check the parameters */
mbed_official 376:cb4d9db17537 3038 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
mbed_official 376:cb4d9db17537 3039 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
mbed_official 376:cb4d9db17537 3040
mbed_official 490:119543c9f674 3041 if(OutputChannel != InputChannel)
mbed_official 376:cb4d9db17537 3042 {
mbed_official 376:cb4d9db17537 3043 __HAL_LOCK(htim);
mbed_official 376:cb4d9db17537 3044
mbed_official 376:cb4d9db17537 3045 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 3046
mbed_official 490:119543c9f674 3047 /* Extract the Ouput compare configuration from sConfig structure */
mbed_official 376:cb4d9db17537 3048 temp1.OCMode = sConfig->OCMode;
mbed_official 376:cb4d9db17537 3049 temp1.Pulse = sConfig->Pulse;
mbed_official 490:119543c9f674 3050 temp1.OCPolarity = sConfig->OCPolarity;
mbed_official 490:119543c9f674 3051
mbed_official 376:cb4d9db17537 3052 switch (OutputChannel)
mbed_official 376:cb4d9db17537 3053 {
mbed_official 376:cb4d9db17537 3054 case TIM_CHANNEL_1:
mbed_official 376:cb4d9db17537 3055 {
mbed_official 376:cb4d9db17537 3056 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 3057
mbed_official 490:119543c9f674 3058 TIM_OC1_SetConfig(htim->Instance, &temp1);
mbed_official 376:cb4d9db17537 3059 }
mbed_official 376:cb4d9db17537 3060 break;
mbed_official 376:cb4d9db17537 3061 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 3062 {
mbed_official 376:cb4d9db17537 3063 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 3064
mbed_official 376:cb4d9db17537 3065 TIM_OC2_SetConfig(htim->Instance, &temp1);
mbed_official 376:cb4d9db17537 3066 }
mbed_official 376:cb4d9db17537 3067 break;
mbed_official 376:cb4d9db17537 3068 default:
mbed_official 490:119543c9f674 3069 break;
mbed_official 490:119543c9f674 3070 }
mbed_official 376:cb4d9db17537 3071 switch (InputChannel)
mbed_official 376:cb4d9db17537 3072 {
mbed_official 376:cb4d9db17537 3073 case TIM_CHANNEL_1:
mbed_official 376:cb4d9db17537 3074 {
mbed_official 376:cb4d9db17537 3075 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3076
mbed_official 376:cb4d9db17537 3077 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 376:cb4d9db17537 3078 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 490:119543c9f674 3079
mbed_official 376:cb4d9db17537 3080 /* Reset the IC1PSC Bits */
mbed_official 376:cb4d9db17537 3081 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official 376:cb4d9db17537 3082
mbed_official 376:cb4d9db17537 3083 /* Select the Trigger source */
mbed_official 376:cb4d9db17537 3084 htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official 376:cb4d9db17537 3085 htim->Instance->SMCR |= TIM_TS_TI1FP1;
mbed_official 490:119543c9f674 3086
mbed_official 490:119543c9f674 3087 /* Select the Slave Mode */
mbed_official 376:cb4d9db17537 3088 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 376:cb4d9db17537 3089 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 376:cb4d9db17537 3090 }
mbed_official 376:cb4d9db17537 3091 break;
mbed_official 376:cb4d9db17537 3092 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 3093 {
mbed_official 376:cb4d9db17537 3094 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 3095
mbed_official 376:cb4d9db17537 3096 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 376:cb4d9db17537 3097 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 490:119543c9f674 3098
mbed_official 376:cb4d9db17537 3099 /* Reset the IC2PSC Bits */
mbed_official 376:cb4d9db17537 3100 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official 376:cb4d9db17537 3101
mbed_official 376:cb4d9db17537 3102 /* Select the Trigger source */
mbed_official 376:cb4d9db17537 3103 htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official 376:cb4d9db17537 3104 htim->Instance->SMCR |= TIM_TS_TI2FP2;
mbed_official 490:119543c9f674 3105
mbed_official 490:119543c9f674 3106 /* Select the Slave Mode */
mbed_official 376:cb4d9db17537 3107 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 376:cb4d9db17537 3108 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 376:cb4d9db17537 3109 }
mbed_official 376:cb4d9db17537 3110 break;
mbed_official 490:119543c9f674 3111
mbed_official 376:cb4d9db17537 3112 default:
mbed_official 490:119543c9f674 3113 break;
mbed_official 376:cb4d9db17537 3114 }
mbed_official 490:119543c9f674 3115
mbed_official 376:cb4d9db17537 3116 htim->State = HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 3117
mbed_official 376:cb4d9db17537 3118 __HAL_UNLOCK(htim);
mbed_official 490:119543c9f674 3119
mbed_official 376:cb4d9db17537 3120 return HAL_OK;
mbed_official 376:cb4d9db17537 3121 }
mbed_official 376:cb4d9db17537 3122 else
mbed_official 376:cb4d9db17537 3123 {
mbed_official 376:cb4d9db17537 3124 return HAL_ERROR;
mbed_official 376:cb4d9db17537 3125 }
mbed_official 376:cb4d9db17537 3126 }
mbed_official 376:cb4d9db17537 3127
mbed_official 376:cb4d9db17537 3128 /**
mbed_official 490:119543c9f674 3129 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
mbed_official 490:119543c9f674 3130 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3131 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
mbed_official 376:cb4d9db17537 3132 * This parameters can be on of the following values:
mbed_official 490:119543c9f674 3133 * @arg TIM_DMABASE_CR1
mbed_official 490:119543c9f674 3134 * @arg TIM_DMABASE_CR2
mbed_official 490:119543c9f674 3135 * @arg TIM_DMABASE_SMCR
mbed_official 490:119543c9f674 3136 * @arg TIM_DMABASE_DIER
mbed_official 490:119543c9f674 3137 * @arg TIM_DMABASE_SR
mbed_official 490:119543c9f674 3138 * @arg TIM_DMABASE_EGR
mbed_official 490:119543c9f674 3139 * @arg TIM_DMABASE_CCMR1
mbed_official 490:119543c9f674 3140 * @arg TIM_DMABASE_CCMR2
mbed_official 490:119543c9f674 3141 * @arg TIM_DMABASE_CCER
mbed_official 490:119543c9f674 3142 * @arg TIM_DMABASE_CNT
mbed_official 490:119543c9f674 3143 * @arg TIM_DMABASE_PSC
mbed_official 490:119543c9f674 3144 * @arg TIM_DMABASE_ARR
mbed_official 490:119543c9f674 3145 * @arg TIM_DMABASE_CCR1
mbed_official 490:119543c9f674 3146 * @arg TIM_DMABASE_CCR2
mbed_official 490:119543c9f674 3147 * @arg TIM_DMABASE_CCR3
mbed_official 490:119543c9f674 3148 * @arg TIM_DMABASE_CCR4
mbed_official 490:119543c9f674 3149 * @arg TIM_DMABASE_DCR
mbed_official 376:cb4d9db17537 3150 * @param BurstRequestSrc: TIM DMA Request sources.
mbed_official 376:cb4d9db17537 3151 * This parameters can be on of the following values:
mbed_official 376:cb4d9db17537 3152 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 376:cb4d9db17537 3153 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 376:cb4d9db17537 3154 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 376:cb4d9db17537 3155 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 376:cb4d9db17537 3156 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 376:cb4d9db17537 3157 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 376:cb4d9db17537 3158 * @param BurstBuffer: The Buffer address.
mbed_official 376:cb4d9db17537 3159 * @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official 490:119543c9f674 3160 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
mbed_official 376:cb4d9db17537 3161 * @retval HAL status
mbed_official 376:cb4d9db17537 3162 */
mbed_official 376:cb4d9db17537 3163 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 376:cb4d9db17537 3164 uint32_t* BurstBuffer, uint32_t BurstLength)
mbed_official 376:cb4d9db17537 3165 {
mbed_official 376:cb4d9db17537 3166 /* Check the parameters */
mbed_official 376:cb4d9db17537 3167 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3168 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 376:cb4d9db17537 3169 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 376:cb4d9db17537 3170 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 376:cb4d9db17537 3171
mbed_official 376:cb4d9db17537 3172 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 376:cb4d9db17537 3173 {
mbed_official 376:cb4d9db17537 3174 return HAL_BUSY;
mbed_official 376:cb4d9db17537 3175 }
mbed_official 376:cb4d9db17537 3176 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 376:cb4d9db17537 3177 {
mbed_official 376:cb4d9db17537 3178 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 376:cb4d9db17537 3179 {
mbed_official 376:cb4d9db17537 3180 return HAL_ERROR;
mbed_official 376:cb4d9db17537 3181 }
mbed_official 376:cb4d9db17537 3182 else
mbed_official 376:cb4d9db17537 3183 {
mbed_official 376:cb4d9db17537 3184 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 3185 }
mbed_official 376:cb4d9db17537 3186 }
mbed_official 376:cb4d9db17537 3187 switch(BurstRequestSrc)
mbed_official 376:cb4d9db17537 3188 {
mbed_official 376:cb4d9db17537 3189 case TIM_DMA_UPDATE:
mbed_official 376:cb4d9db17537 3190 {
mbed_official 376:cb4d9db17537 3191 /* Set the DMA Period elapsed callback */
mbed_official 376:cb4d9db17537 3192 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 376:cb4d9db17537 3193
mbed_official 376:cb4d9db17537 3194 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3195 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 3196
mbed_official 376:cb4d9db17537 3197 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3198 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3199 }
mbed_official 376:cb4d9db17537 3200 break;
mbed_official 376:cb4d9db17537 3201 case TIM_DMA_CC1:
mbed_official 376:cb4d9db17537 3202 {
mbed_official 376:cb4d9db17537 3203 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 3204 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 376:cb4d9db17537 3205
mbed_official 376:cb4d9db17537 3206 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3207 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 3208
mbed_official 376:cb4d9db17537 3209 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3210 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3211 }
mbed_official 376:cb4d9db17537 3212 break;
mbed_official 376:cb4d9db17537 3213 case TIM_DMA_CC2:
mbed_official 376:cb4d9db17537 3214 {
mbed_official 376:cb4d9db17537 3215 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 3216 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 376:cb4d9db17537 3217
mbed_official 376:cb4d9db17537 3218 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3219 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 3220
mbed_official 376:cb4d9db17537 3221 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3222 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3223 }
mbed_official 376:cb4d9db17537 3224 break;
mbed_official 376:cb4d9db17537 3225 case TIM_DMA_CC3:
mbed_official 376:cb4d9db17537 3226 {
mbed_official 376:cb4d9db17537 3227 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 3228 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 376:cb4d9db17537 3229
mbed_official 376:cb4d9db17537 3230 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3231 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 3232
mbed_official 376:cb4d9db17537 3233 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3234 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3235 }
mbed_official 376:cb4d9db17537 3236 break;
mbed_official 376:cb4d9db17537 3237 case TIM_DMA_CC4:
mbed_official 376:cb4d9db17537 3238 {
mbed_official 376:cb4d9db17537 3239 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 3240 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 376:cb4d9db17537 3241
mbed_official 376:cb4d9db17537 3242 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3243 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 3244
mbed_official 376:cb4d9db17537 3245 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3246 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3247 }
mbed_official 376:cb4d9db17537 3248 break;
mbed_official 376:cb4d9db17537 3249 case TIM_DMA_TRIGGER:
mbed_official 376:cb4d9db17537 3250 {
mbed_official 376:cb4d9db17537 3251 /* Set the DMA Period elapsed callback */
mbed_official 376:cb4d9db17537 3252 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 376:cb4d9db17537 3253
mbed_official 376:cb4d9db17537 3254 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3255 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 3256
mbed_official 376:cb4d9db17537 3257 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3258 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3259 }
mbed_official 376:cb4d9db17537 3260 break;
mbed_official 376:cb4d9db17537 3261 default:
mbed_official 376:cb4d9db17537 3262 break;
mbed_official 376:cb4d9db17537 3263 }
mbed_official 376:cb4d9db17537 3264 /* configure the DMA Burst Mode */
mbed_official 490:119543c9f674 3265 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 490:119543c9f674 3266
mbed_official 376:cb4d9db17537 3267 /* Enable the TIM DMA Request */
mbed_official 490:119543c9f674 3268 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 490:119543c9f674 3269
mbed_official 376:cb4d9db17537 3270 htim->State = HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 3271
mbed_official 376:cb4d9db17537 3272 /* Return function status */
mbed_official 376:cb4d9db17537 3273 return HAL_OK;
mbed_official 376:cb4d9db17537 3274 }
mbed_official 376:cb4d9db17537 3275
mbed_official 376:cb4d9db17537 3276 /**
mbed_official 490:119543c9f674 3277 * @brief Stops the TIM DMA Burst mode
mbed_official 490:119543c9f674 3278 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3279 * @param BurstRequestSrc: TIM DMA Request sources to disable
mbed_official 376:cb4d9db17537 3280 * @retval HAL status
mbed_official 376:cb4d9db17537 3281 */
mbed_official 376:cb4d9db17537 3282 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 376:cb4d9db17537 3283 {
mbed_official 376:cb4d9db17537 3284 /* Check the parameters */
mbed_official 376:cb4d9db17537 3285 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 376:cb4d9db17537 3286
mbed_official 490:119543c9f674 3287 /* Abort the DMA transfer (at least disable the DMA channel) */
mbed_official 490:119543c9f674 3288 switch(BurstRequestSrc)
mbed_official 490:119543c9f674 3289 {
mbed_official 490:119543c9f674 3290 case TIM_DMA_UPDATE:
mbed_official 490:119543c9f674 3291 {
mbed_official 490:119543c9f674 3292 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
mbed_official 490:119543c9f674 3293 }
mbed_official 490:119543c9f674 3294 break;
mbed_official 490:119543c9f674 3295 case TIM_DMA_CC1:
mbed_official 490:119543c9f674 3296 {
mbed_official 490:119543c9f674 3297 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
mbed_official 490:119543c9f674 3298 }
mbed_official 490:119543c9f674 3299 break;
mbed_official 490:119543c9f674 3300 case TIM_DMA_CC2:
mbed_official 490:119543c9f674 3301 {
mbed_official 490:119543c9f674 3302 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
mbed_official 490:119543c9f674 3303 }
mbed_official 490:119543c9f674 3304 break;
mbed_official 490:119543c9f674 3305 case TIM_DMA_CC3:
mbed_official 490:119543c9f674 3306 {
mbed_official 490:119543c9f674 3307 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
mbed_official 490:119543c9f674 3308 }
mbed_official 490:119543c9f674 3309 break;
mbed_official 490:119543c9f674 3310 case TIM_DMA_CC4:
mbed_official 490:119543c9f674 3311 {
mbed_official 490:119543c9f674 3312 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
mbed_official 490:119543c9f674 3313 }
mbed_official 490:119543c9f674 3314 break;
mbed_official 490:119543c9f674 3315 case TIM_DMA_TRIGGER:
mbed_official 490:119543c9f674 3316 {
mbed_official 490:119543c9f674 3317 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
mbed_official 490:119543c9f674 3318 }
mbed_official 490:119543c9f674 3319 break;
mbed_official 490:119543c9f674 3320 default:
mbed_official 490:119543c9f674 3321 break;
mbed_official 490:119543c9f674 3322 }
mbed_official 376:cb4d9db17537 3323 /* Disable the TIM Update DMA request */
mbed_official 376:cb4d9db17537 3324 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 376:cb4d9db17537 3325
mbed_official 376:cb4d9db17537 3326 /* Return function status */
mbed_official 376:cb4d9db17537 3327 return HAL_OK;
mbed_official 376:cb4d9db17537 3328 }
mbed_official 376:cb4d9db17537 3329
mbed_official 376:cb4d9db17537 3330 /**
mbed_official 490:119543c9f674 3331 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
mbed_official 490:119543c9f674 3332 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3333 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
mbed_official 376:cb4d9db17537 3334 * This parameters can be on of the following values:
mbed_official 490:119543c9f674 3335 * @arg TIM_DMABASE_CR1
mbed_official 490:119543c9f674 3336 * @arg TIM_DMABASE_CR2
mbed_official 490:119543c9f674 3337 * @arg TIM_DMABASE_SMCR
mbed_official 490:119543c9f674 3338 * @arg TIM_DMABASE_DIER
mbed_official 490:119543c9f674 3339 * @arg TIM_DMABASE_SR
mbed_official 490:119543c9f674 3340 * @arg TIM_DMABASE_EGR
mbed_official 490:119543c9f674 3341 * @arg TIM_DMABASE_CCMR1
mbed_official 490:119543c9f674 3342 * @arg TIM_DMABASE_CCMR2
mbed_official 490:119543c9f674 3343 * @arg TIM_DMABASE_CCER
mbed_official 490:119543c9f674 3344 * @arg TIM_DMABASE_CNT
mbed_official 490:119543c9f674 3345 * @arg TIM_DMABASE_PSC
mbed_official 490:119543c9f674 3346 * @arg TIM_DMABASE_ARR
mbed_official 490:119543c9f674 3347 * @arg TIM_DMABASE_CCR1
mbed_official 490:119543c9f674 3348 * @arg TIM_DMABASE_CCR2
mbed_official 490:119543c9f674 3349 * @arg TIM_DMABASE_CCR3
mbed_official 490:119543c9f674 3350 * @arg TIM_DMABASE_CCR4
mbed_official 490:119543c9f674 3351 * @arg TIM_DMABASE_DCR
mbed_official 376:cb4d9db17537 3352 * @param BurstRequestSrc: TIM DMA Request sources.
mbed_official 376:cb4d9db17537 3353 * This parameters can be on of the following values:
mbed_official 376:cb4d9db17537 3354 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 376:cb4d9db17537 3355 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 376:cb4d9db17537 3356 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 376:cb4d9db17537 3357 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 376:cb4d9db17537 3358 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 376:cb4d9db17537 3359 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 376:cb4d9db17537 3360 * @param BurstBuffer: The Buffer address.
mbed_official 376:cb4d9db17537 3361 * @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official 490:119543c9f674 3362 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS .
mbed_official 376:cb4d9db17537 3363 * @retval HAL status
mbed_official 376:cb4d9db17537 3364 */
mbed_official 376:cb4d9db17537 3365 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 376:cb4d9db17537 3366 uint32_t *BurstBuffer, uint32_t BurstLength)
mbed_official 376:cb4d9db17537 3367 {
mbed_official 376:cb4d9db17537 3368 /* Check the parameters */
mbed_official 376:cb4d9db17537 3369 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3370 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 376:cb4d9db17537 3371 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 376:cb4d9db17537 3372 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 376:cb4d9db17537 3373
mbed_official 376:cb4d9db17537 3374 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 376:cb4d9db17537 3375 {
mbed_official 376:cb4d9db17537 3376 return HAL_BUSY;
mbed_official 376:cb4d9db17537 3377 }
mbed_official 376:cb4d9db17537 3378 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 376:cb4d9db17537 3379 {
mbed_official 490:119543c9f674 3380 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 376:cb4d9db17537 3381 {
mbed_official 490:119543c9f674 3382 return HAL_ERROR;
mbed_official 376:cb4d9db17537 3383 }
mbed_official 376:cb4d9db17537 3384 else
mbed_official 376:cb4d9db17537 3385 {
mbed_official 376:cb4d9db17537 3386 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 3387 }
mbed_official 490:119543c9f674 3388 }
mbed_official 376:cb4d9db17537 3389 switch(BurstRequestSrc)
mbed_official 376:cb4d9db17537 3390 {
mbed_official 376:cb4d9db17537 3391 case TIM_DMA_UPDATE:
mbed_official 490:119543c9f674 3392 {
mbed_official 376:cb4d9db17537 3393 /* Set the DMA Period elapsed callback */
mbed_official 376:cb4d9db17537 3394 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 490:119543c9f674 3395
mbed_official 376:cb4d9db17537 3396 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3397 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 3398
mbed_official 376:cb4d9db17537 3399 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3400 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3401 }
mbed_official 376:cb4d9db17537 3402 break;
mbed_official 376:cb4d9db17537 3403 case TIM_DMA_CC1:
mbed_official 490:119543c9f674 3404 {
mbed_official 376:cb4d9db17537 3405 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 3406 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 490:119543c9f674 3407
mbed_official 376:cb4d9db17537 3408 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3409 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 3410
mbed_official 376:cb4d9db17537 3411 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3412 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3413 }
mbed_official 376:cb4d9db17537 3414 break;
mbed_official 376:cb4d9db17537 3415 case TIM_DMA_CC2:
mbed_official 490:119543c9f674 3416 {
mbed_official 376:cb4d9db17537 3417 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 3418 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 490:119543c9f674 3419
mbed_official 376:cb4d9db17537 3420 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3421 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 3422
mbed_official 376:cb4d9db17537 3423 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3424 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3425 }
mbed_official 376:cb4d9db17537 3426 break;
mbed_official 376:cb4d9db17537 3427 case TIM_DMA_CC3:
mbed_official 490:119543c9f674 3428 {
mbed_official 376:cb4d9db17537 3429 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 3430 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 490:119543c9f674 3431
mbed_official 376:cb4d9db17537 3432 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3433 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 376:cb4d9db17537 3434
mbed_official 376:cb4d9db17537 3435 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3436 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3437 }
mbed_official 376:cb4d9db17537 3438 break;
mbed_official 376:cb4d9db17537 3439 case TIM_DMA_CC4:
mbed_official 490:119543c9f674 3440 {
mbed_official 376:cb4d9db17537 3441 /* Set the DMA Period elapsed callback */
mbed_official 490:119543c9f674 3442 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 490:119543c9f674 3443
mbed_official 376:cb4d9db17537 3444 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3445 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 3446
mbed_official 376:cb4d9db17537 3447 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3448 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3449 }
mbed_official 376:cb4d9db17537 3450 break;
mbed_official 376:cb4d9db17537 3451 case TIM_DMA_TRIGGER:
mbed_official 490:119543c9f674 3452 {
mbed_official 376:cb4d9db17537 3453 /* Set the DMA Period elapsed callback */
mbed_official 376:cb4d9db17537 3454 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 490:119543c9f674 3455
mbed_official 376:cb4d9db17537 3456 /* Set the DMA error callback */
mbed_official 490:119543c9f674 3457 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
mbed_official 490:119543c9f674 3458
mbed_official 376:cb4d9db17537 3459 /* Enable the DMA Stream */
mbed_official 490:119543c9f674 3460 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 376:cb4d9db17537 3461 }
mbed_official 376:cb4d9db17537 3462 break;
mbed_official 376:cb4d9db17537 3463 default:
mbed_official 490:119543c9f674 3464 break;
mbed_official 376:cb4d9db17537 3465 }
mbed_official 376:cb4d9db17537 3466
mbed_official 376:cb4d9db17537 3467 /* configure the DMA Burst Mode */
mbed_official 490:119543c9f674 3468 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 490:119543c9f674 3469
mbed_official 376:cb4d9db17537 3470 /* Enable the TIM DMA Request */
mbed_official 376:cb4d9db17537 3471 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 490:119543c9f674 3472
mbed_official 376:cb4d9db17537 3473 htim->State = HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 3474
mbed_official 376:cb4d9db17537 3475 /* Return function status */
mbed_official 376:cb4d9db17537 3476 return HAL_OK;
mbed_official 376:cb4d9db17537 3477 }
mbed_official 376:cb4d9db17537 3478
mbed_official 376:cb4d9db17537 3479 /**
mbed_official 490:119543c9f674 3480 * @brief Stop the DMA burst reading
mbed_official 490:119543c9f674 3481 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3482 * @param BurstRequestSrc: TIM DMA Request sources to disable.
mbed_official 376:cb4d9db17537 3483 * @retval HAL status
mbed_official 376:cb4d9db17537 3484 */
mbed_official 376:cb4d9db17537 3485 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 376:cb4d9db17537 3486 {
mbed_official 376:cb4d9db17537 3487 /* Check the parameters */
mbed_official 376:cb4d9db17537 3488 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 376:cb4d9db17537 3489
mbed_official 490:119543c9f674 3490 /* Abort the DMA transfer (at least disable the DMA channel) */
mbed_official 490:119543c9f674 3491 switch(BurstRequestSrc)
mbed_official 490:119543c9f674 3492 {
mbed_official 490:119543c9f674 3493 case TIM_DMA_UPDATE:
mbed_official 490:119543c9f674 3494 {
mbed_official 490:119543c9f674 3495 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
mbed_official 490:119543c9f674 3496 }
mbed_official 490:119543c9f674 3497 break;
mbed_official 490:119543c9f674 3498 case TIM_DMA_CC1:
mbed_official 490:119543c9f674 3499 {
mbed_official 490:119543c9f674 3500 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
mbed_official 490:119543c9f674 3501 }
mbed_official 490:119543c9f674 3502 break;
mbed_official 490:119543c9f674 3503 case TIM_DMA_CC2:
mbed_official 490:119543c9f674 3504 {
mbed_official 490:119543c9f674 3505 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
mbed_official 490:119543c9f674 3506 }
mbed_official 490:119543c9f674 3507 break;
mbed_official 490:119543c9f674 3508 case TIM_DMA_CC3:
mbed_official 490:119543c9f674 3509 {
mbed_official 490:119543c9f674 3510 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
mbed_official 490:119543c9f674 3511 }
mbed_official 490:119543c9f674 3512 break;
mbed_official 490:119543c9f674 3513 case TIM_DMA_CC4:
mbed_official 490:119543c9f674 3514 {
mbed_official 490:119543c9f674 3515 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
mbed_official 490:119543c9f674 3516 }
mbed_official 490:119543c9f674 3517 break;
mbed_official 490:119543c9f674 3518 case TIM_DMA_TRIGGER:
mbed_official 490:119543c9f674 3519 {
mbed_official 490:119543c9f674 3520 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
mbed_official 490:119543c9f674 3521 }
mbed_official 490:119543c9f674 3522 break;
mbed_official 490:119543c9f674 3523 default:
mbed_official 490:119543c9f674 3524 break;
mbed_official 490:119543c9f674 3525 }
mbed_official 490:119543c9f674 3526
mbed_official 376:cb4d9db17537 3527 /* Disable the TIM Update DMA request */
mbed_official 376:cb4d9db17537 3528 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 490:119543c9f674 3529
mbed_official 376:cb4d9db17537 3530 /* Return function status */
mbed_official 490:119543c9f674 3531 return HAL_OK;
mbed_official 376:cb4d9db17537 3532 }
mbed_official 376:cb4d9db17537 3533
mbed_official 376:cb4d9db17537 3534 /**
mbed_official 376:cb4d9db17537 3535 * @brief Generate a software event
mbed_official 490:119543c9f674 3536 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3537 * @param EventSource: specifies the event source.
mbed_official 376:cb4d9db17537 3538 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 3539 * @arg TIM_EventSource_Update: Timer update Event source
mbed_official 490:119543c9f674 3540 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
mbed_official 376:cb4d9db17537 3541 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
mbed_official 376:cb4d9db17537 3542 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
mbed_official 490:119543c9f674 3543 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
mbed_official 490:119543c9f674 3544 * @arg TIM_EVENTSOURCE_TRIGGER : Timer Trigger Event source
mbed_official 490:119543c9f674 3545 * @note TIM6 can only generate an update event.
mbed_official 376:cb4d9db17537 3546 * @retval HAL status
mbed_official 490:119543c9f674 3547 */
mbed_official 376:cb4d9db17537 3548
mbed_official 376:cb4d9db17537 3549 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
mbed_official 376:cb4d9db17537 3550 {
mbed_official 376:cb4d9db17537 3551 /* Check the parameters */
mbed_official 376:cb4d9db17537 3552 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3553 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
mbed_official 490:119543c9f674 3554
mbed_official 376:cb4d9db17537 3555 /* Process Locked */
mbed_official 376:cb4d9db17537 3556 __HAL_LOCK(htim);
mbed_official 490:119543c9f674 3557
mbed_official 376:cb4d9db17537 3558 /* Change the TIM state */
mbed_official 376:cb4d9db17537 3559 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 3560
mbed_official 376:cb4d9db17537 3561 /* Set the event sources */
mbed_official 376:cb4d9db17537 3562 htim->Instance->EGR = EventSource;
mbed_official 490:119543c9f674 3563
mbed_official 376:cb4d9db17537 3564 /* Change the TIM state */
mbed_official 376:cb4d9db17537 3565 htim->State = HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 3566
mbed_official 376:cb4d9db17537 3567 __HAL_UNLOCK(htim);
mbed_official 376:cb4d9db17537 3568
mbed_official 376:cb4d9db17537 3569 /* Return function status */
mbed_official 490:119543c9f674 3570 return HAL_OK;
mbed_official 376:cb4d9db17537 3571 }
mbed_official 376:cb4d9db17537 3572
mbed_official 376:cb4d9db17537 3573 /**
mbed_official 376:cb4d9db17537 3574 * @brief Configures the OCRef clear feature
mbed_official 490:119543c9f674 3575 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3576 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
mbed_official 490:119543c9f674 3577 * contains the OCREF clear feature and parameters for the TIM peripheral.
mbed_official 376:cb4d9db17537 3578 * @param Channel: specifies the TIM Channel.
mbed_official 376:cb4d9db17537 3579 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 3580 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 3581 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 3582 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 3583 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 3584 * @retval HAL status
mbed_official 490:119543c9f674 3585 */
mbed_official 376:cb4d9db17537 3586 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
mbed_official 490:119543c9f674 3587 {
mbed_official 376:cb4d9db17537 3588 /* Check the parameters */
mbed_official 376:cb4d9db17537 3589 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3590 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 376:cb4d9db17537 3591 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
mbed_official 376:cb4d9db17537 3592 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
mbed_official 376:cb4d9db17537 3593 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
mbed_official 376:cb4d9db17537 3594 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
mbed_official 490:119543c9f674 3595
mbed_official 376:cb4d9db17537 3596 /* Process Locked */
mbed_official 376:cb4d9db17537 3597 __HAL_LOCK(htim);
mbed_official 490:119543c9f674 3598
mbed_official 376:cb4d9db17537 3599 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 3600
mbed_official 376:cb4d9db17537 3601 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
mbed_official 376:cb4d9db17537 3602 {
mbed_official 490:119543c9f674 3603 TIM_ETR_SetConfig(htim->Instance,
mbed_official 376:cb4d9db17537 3604 sClearInputConfig->ClearInputPrescaler,
mbed_official 376:cb4d9db17537 3605 sClearInputConfig->ClearInputPolarity,
mbed_official 376:cb4d9db17537 3606 sClearInputConfig->ClearInputFilter);
mbed_official 376:cb4d9db17537 3607 }
mbed_official 490:119543c9f674 3608
mbed_official 376:cb4d9db17537 3609 switch (Channel)
mbed_official 376:cb4d9db17537 3610 {
mbed_official 376:cb4d9db17537 3611 case TIM_CHANNEL_1:
mbed_official 490:119543c9f674 3612 {
mbed_official 490:119543c9f674 3613 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 376:cb4d9db17537 3614 {
mbed_official 376:cb4d9db17537 3615 /* Enable the Ocref clear feature for Channel 1 */
mbed_official 376:cb4d9db17537 3616 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
mbed_official 376:cb4d9db17537 3617 }
mbed_official 376:cb4d9db17537 3618 else
mbed_official 376:cb4d9db17537 3619 {
mbed_official 376:cb4d9db17537 3620 /* Disable the Ocref clear feature for Channel 1 */
mbed_official 490:119543c9f674 3621 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
mbed_official 376:cb4d9db17537 3622 }
mbed_official 376:cb4d9db17537 3623 }
mbed_official 376:cb4d9db17537 3624 break;
mbed_official 376:cb4d9db17537 3625 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 3626 {
mbed_official 376:cb4d9db17537 3627 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3628 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 376:cb4d9db17537 3629 {
mbed_official 376:cb4d9db17537 3630 /* Enable the Ocref clear feature for Channel 2 */
mbed_official 376:cb4d9db17537 3631 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
mbed_official 376:cb4d9db17537 3632 }
mbed_official 376:cb4d9db17537 3633 else
mbed_official 376:cb4d9db17537 3634 {
mbed_official 376:cb4d9db17537 3635 /* Disable the Ocref clear feature for Channel 2 */
mbed_official 376:cb4d9db17537 3636 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
mbed_official 376:cb4d9db17537 3637 }
mbed_official 376:cb4d9db17537 3638 }
mbed_official 376:cb4d9db17537 3639 break;
mbed_official 376:cb4d9db17537 3640 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 3641 {
mbed_official 376:cb4d9db17537 3642 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3643 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 376:cb4d9db17537 3644 {
mbed_official 376:cb4d9db17537 3645 /* Enable the Ocref clear feature for Channel 3 */
mbed_official 376:cb4d9db17537 3646 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
mbed_official 376:cb4d9db17537 3647 }
mbed_official 376:cb4d9db17537 3648 else
mbed_official 376:cb4d9db17537 3649 {
mbed_official 376:cb4d9db17537 3650 /* Disable the Ocref clear feature for Channel 3 */
mbed_official 376:cb4d9db17537 3651 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
mbed_official 376:cb4d9db17537 3652 }
mbed_official 376:cb4d9db17537 3653 }
mbed_official 376:cb4d9db17537 3654 break;
mbed_official 376:cb4d9db17537 3655 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 3656 {
mbed_official 376:cb4d9db17537 3657 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3658 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 376:cb4d9db17537 3659 {
mbed_official 376:cb4d9db17537 3660 /* Enable the Ocref clear feature for Channel 4 */
mbed_official 376:cb4d9db17537 3661 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
mbed_official 376:cb4d9db17537 3662 }
mbed_official 376:cb4d9db17537 3663 else
mbed_official 376:cb4d9db17537 3664 {
mbed_official 376:cb4d9db17537 3665 /* Disable the Ocref clear feature for Channel 4 */
mbed_official 376:cb4d9db17537 3666 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
mbed_official 376:cb4d9db17537 3667 }
mbed_official 376:cb4d9db17537 3668 }
mbed_official 376:cb4d9db17537 3669 break;
mbed_official 376:cb4d9db17537 3670 default:
mbed_official 376:cb4d9db17537 3671 break;
mbed_official 376:cb4d9db17537 3672 }
mbed_official 376:cb4d9db17537 3673
mbed_official 376:cb4d9db17537 3674 htim->State = HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 3675
mbed_official 376:cb4d9db17537 3676 __HAL_UNLOCK(htim);
mbed_official 376:cb4d9db17537 3677
mbed_official 376:cb4d9db17537 3678 return HAL_OK;
mbed_official 376:cb4d9db17537 3679 }
mbed_official 376:cb4d9db17537 3680
mbed_official 376:cb4d9db17537 3681 /**
mbed_official 376:cb4d9db17537 3682 * @brief Configures the clock source to be used
mbed_official 490:119543c9f674 3683 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3684 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
mbed_official 376:cb4d9db17537 3685 * contains the clock source information for the TIM peripheral.
mbed_official 376:cb4d9db17537 3686 * @retval HAL status
mbed_official 376:cb4d9db17537 3687 */
mbed_official 376:cb4d9db17537 3688 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
mbed_official 376:cb4d9db17537 3689 {
mbed_official 376:cb4d9db17537 3690 uint32_t tmpsmcr = 0;
mbed_official 376:cb4d9db17537 3691
mbed_official 376:cb4d9db17537 3692 /* Process Locked */
mbed_official 376:cb4d9db17537 3693 __HAL_LOCK(htim);
mbed_official 376:cb4d9db17537 3694
mbed_official 376:cb4d9db17537 3695 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 3696
mbed_official 376:cb4d9db17537 3697 /* Check the parameters */
mbed_official 376:cb4d9db17537 3698 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
mbed_official 376:cb4d9db17537 3699 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official 376:cb4d9db17537 3700 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official 376:cb4d9db17537 3701 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official 376:cb4d9db17537 3702
mbed_official 376:cb4d9db17537 3703 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
mbed_official 376:cb4d9db17537 3704 tmpsmcr = htim->Instance->SMCR;
mbed_official 376:cb4d9db17537 3705 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
mbed_official 376:cb4d9db17537 3706 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 376:cb4d9db17537 3707 htim->Instance->SMCR = tmpsmcr;
mbed_official 376:cb4d9db17537 3708
mbed_official 376:cb4d9db17537 3709 switch (sClockSourceConfig->ClockSource)
mbed_official 376:cb4d9db17537 3710 {
mbed_official 376:cb4d9db17537 3711 case TIM_CLOCKSOURCE_INTERNAL:
mbed_official 376:cb4d9db17537 3712 {
mbed_official 376:cb4d9db17537 3713 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3714 /* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official 376:cb4d9db17537 3715 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 376:cb4d9db17537 3716 }
mbed_official 376:cb4d9db17537 3717 break;
mbed_official 376:cb4d9db17537 3718
mbed_official 376:cb4d9db17537 3719 case TIM_CLOCKSOURCE_ETRMODE1:
mbed_official 376:cb4d9db17537 3720 {
mbed_official 376:cb4d9db17537 3721 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3722 /* Configure the ETR Clock source */
mbed_official 376:cb4d9db17537 3723 TIM_ETR_SetConfig(htim->Instance,
mbed_official 376:cb4d9db17537 3724 sClockSourceConfig->ClockPrescaler,
mbed_official 376:cb4d9db17537 3725 sClockSourceConfig->ClockPolarity,
mbed_official 376:cb4d9db17537 3726 sClockSourceConfig->ClockFilter);
mbed_official 376:cb4d9db17537 3727 /* Get the TIMx SMCR register value */
mbed_official 376:cb4d9db17537 3728 tmpsmcr = htim->Instance->SMCR;
mbed_official 376:cb4d9db17537 3729 /* Reset the SMS and TS Bits */
mbed_official 376:cb4d9db17537 3730 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
mbed_official 376:cb4d9db17537 3731 /* Select the External clock mode1 and the ETRF trigger */
mbed_official 376:cb4d9db17537 3732 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
mbed_official 376:cb4d9db17537 3733 /* Write to TIMx SMCR */
mbed_official 376:cb4d9db17537 3734 htim->Instance->SMCR = tmpsmcr;
mbed_official 376:cb4d9db17537 3735 }
mbed_official 376:cb4d9db17537 3736 break;
mbed_official 376:cb4d9db17537 3737
mbed_official 376:cb4d9db17537 3738 case TIM_CLOCKSOURCE_ETRMODE2:
mbed_official 376:cb4d9db17537 3739 {
mbed_official 376:cb4d9db17537 3740 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3741 /* Configure the ETR Clock source */
mbed_official 376:cb4d9db17537 3742 TIM_ETR_SetConfig(htim->Instance,
mbed_official 376:cb4d9db17537 3743 sClockSourceConfig->ClockPrescaler,
mbed_official 376:cb4d9db17537 3744 sClockSourceConfig->ClockPolarity,
mbed_official 376:cb4d9db17537 3745 sClockSourceConfig->ClockFilter);
mbed_official 376:cb4d9db17537 3746 /* Enable the External clock mode2 */
mbed_official 376:cb4d9db17537 3747 htim->Instance->SMCR |= TIM_SMCR_ECE;
mbed_official 376:cb4d9db17537 3748 }
mbed_official 376:cb4d9db17537 3749 break;
mbed_official 376:cb4d9db17537 3750
mbed_official 376:cb4d9db17537 3751 case TIM_CLOCKSOURCE_TI1:
mbed_official 376:cb4d9db17537 3752 {
mbed_official 376:cb4d9db17537 3753 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3754 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 376:cb4d9db17537 3755 sClockSourceConfig->ClockPolarity,
mbed_official 376:cb4d9db17537 3756 sClockSourceConfig->ClockFilter);
mbed_official 376:cb4d9db17537 3757 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
mbed_official 376:cb4d9db17537 3758 }
mbed_official 376:cb4d9db17537 3759 break;
mbed_official 376:cb4d9db17537 3760 case TIM_CLOCKSOURCE_TI2:
mbed_official 376:cb4d9db17537 3761 {
mbed_official 376:cb4d9db17537 3762 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3763 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 376:cb4d9db17537 3764 sClockSourceConfig->ClockPolarity,
mbed_official 376:cb4d9db17537 3765 sClockSourceConfig->ClockFilter);
mbed_official 376:cb4d9db17537 3766 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
mbed_official 376:cb4d9db17537 3767 }
mbed_official 376:cb4d9db17537 3768 break;
mbed_official 376:cb4d9db17537 3769 case TIM_CLOCKSOURCE_TI1ED:
mbed_official 376:cb4d9db17537 3770 {
mbed_official 376:cb4d9db17537 3771 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3772 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 376:cb4d9db17537 3773 sClockSourceConfig->ClockPolarity,
mbed_official 376:cb4d9db17537 3774 sClockSourceConfig->ClockFilter);
mbed_official 376:cb4d9db17537 3775 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
mbed_official 376:cb4d9db17537 3776 }
mbed_official 376:cb4d9db17537 3777 break;
mbed_official 376:cb4d9db17537 3778 case TIM_CLOCKSOURCE_ITR0:
mbed_official 376:cb4d9db17537 3779 {
mbed_official 376:cb4d9db17537 3780 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3781 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
mbed_official 376:cb4d9db17537 3782 }
mbed_official 376:cb4d9db17537 3783 break;
mbed_official 376:cb4d9db17537 3784 case TIM_CLOCKSOURCE_ITR1:
mbed_official 376:cb4d9db17537 3785 {
mbed_official 376:cb4d9db17537 3786 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3787 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
mbed_official 376:cb4d9db17537 3788 }
mbed_official 376:cb4d9db17537 3789 break;
mbed_official 376:cb4d9db17537 3790 case TIM_CLOCKSOURCE_ITR2:
mbed_official 376:cb4d9db17537 3791 {
mbed_official 376:cb4d9db17537 3792 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3793 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
mbed_official 376:cb4d9db17537 3794 }
mbed_official 376:cb4d9db17537 3795 break;
mbed_official 376:cb4d9db17537 3796 case TIM_CLOCKSOURCE_ITR3:
mbed_official 376:cb4d9db17537 3797 {
mbed_official 376:cb4d9db17537 3798 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3799 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
mbed_official 376:cb4d9db17537 3800 }
mbed_official 376:cb4d9db17537 3801 break;
mbed_official 376:cb4d9db17537 3802
mbed_official 376:cb4d9db17537 3803 default:
mbed_official 376:cb4d9db17537 3804 break;
mbed_official 376:cb4d9db17537 3805 }
mbed_official 376:cb4d9db17537 3806 htim->State = HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 3807
mbed_official 376:cb4d9db17537 3808 __HAL_UNLOCK(htim);
mbed_official 376:cb4d9db17537 3809
mbed_official 376:cb4d9db17537 3810 return HAL_OK;
mbed_official 376:cb4d9db17537 3811 }
mbed_official 376:cb4d9db17537 3812
mbed_official 376:cb4d9db17537 3813 /**
mbed_official 376:cb4d9db17537 3814 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
mbed_official 376:cb4d9db17537 3815 * or a XOR combination between CH1_input, CH2_input & CH3_input
mbed_official 490:119543c9f674 3816 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3817 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
mbed_official 376:cb4d9db17537 3818 * output of a XOR gate.
mbed_official 376:cb4d9db17537 3819 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 3820 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
mbed_official 376:cb4d9db17537 3821 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
mbed_official 376:cb4d9db17537 3822 * pins are connected to the TI1 input (XOR combination)
mbed_official 376:cb4d9db17537 3823 * @retval HAL status
mbed_official 376:cb4d9db17537 3824 */
mbed_official 376:cb4d9db17537 3825 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
mbed_official 376:cb4d9db17537 3826 {
mbed_official 376:cb4d9db17537 3827 uint32_t tmpcr2 = 0;
mbed_official 376:cb4d9db17537 3828
mbed_official 376:cb4d9db17537 3829 /* Check the parameters */
mbed_official 376:cb4d9db17537 3830 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3831 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
mbed_official 376:cb4d9db17537 3832
mbed_official 376:cb4d9db17537 3833 /* Get the TIMx CR2 register value */
mbed_official 376:cb4d9db17537 3834 tmpcr2 = htim->Instance->CR2;
mbed_official 376:cb4d9db17537 3835
mbed_official 376:cb4d9db17537 3836 /* Reset the TI1 selection */
mbed_official 376:cb4d9db17537 3837 tmpcr2 &= ~TIM_CR2_TI1S;
mbed_official 376:cb4d9db17537 3838
mbed_official 376:cb4d9db17537 3839 /* Set the the TI1 selection */
mbed_official 376:cb4d9db17537 3840 tmpcr2 |= TI1_Selection;
mbed_official 376:cb4d9db17537 3841
mbed_official 376:cb4d9db17537 3842 /* Write to TIMxCR2 */
mbed_official 376:cb4d9db17537 3843 htim->Instance->CR2 = tmpcr2;
mbed_official 376:cb4d9db17537 3844
mbed_official 376:cb4d9db17537 3845 return HAL_OK;
mbed_official 376:cb4d9db17537 3846 }
mbed_official 376:cb4d9db17537 3847
mbed_official 376:cb4d9db17537 3848 /**
mbed_official 376:cb4d9db17537 3849 * @brief Configures the TIM in Slave mode
mbed_official 490:119543c9f674 3850 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3851 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official 376:cb4d9db17537 3852 * contains the selected trigger (internal trigger input, filtered
mbed_official 376:cb4d9db17537 3853 * timer input or external trigger input) and the ) and the Slave
mbed_official 376:cb4d9db17537 3854 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official 376:cb4d9db17537 3855 * @retval HAL status
mbed_official 376:cb4d9db17537 3856 */
mbed_official 376:cb4d9db17537 3857 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 376:cb4d9db17537 3858 {
mbed_official 376:cb4d9db17537 3859 /* Check the parameters */
mbed_official 376:cb4d9db17537 3860 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3861 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official 376:cb4d9db17537 3862 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official 376:cb4d9db17537 3863
mbed_official 376:cb4d9db17537 3864 __HAL_LOCK(htim);
mbed_official 376:cb4d9db17537 3865
mbed_official 376:cb4d9db17537 3866 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 376:cb4d9db17537 3867
mbed_official 490:119543c9f674 3868 /* Configuration in slave mode */
mbed_official 490:119543c9f674 3869 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
mbed_official 490:119543c9f674 3870
mbed_official 490:119543c9f674 3871 /* Disable Trigger Interrupt */
mbed_official 490:119543c9f674 3872 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
mbed_official 376:cb4d9db17537 3873
mbed_official 490:119543c9f674 3874 /* Disable Trigger DMA request */
mbed_official 490:119543c9f674 3875 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
mbed_official 490:119543c9f674 3876
mbed_official 490:119543c9f674 3877 /* Set the new state */
mbed_official 376:cb4d9db17537 3878 htim->State = HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 3879
mbed_official 376:cb4d9db17537 3880 __HAL_UNLOCK(htim);
mbed_official 376:cb4d9db17537 3881
mbed_official 376:cb4d9db17537 3882 return HAL_OK;
mbed_official 376:cb4d9db17537 3883 }
mbed_official 376:cb4d9db17537 3884
mbed_official 376:cb4d9db17537 3885 /**
mbed_official 490:119543c9f674 3886 * @brief Configures the TIM in Slave mode in interrupt mode
mbed_official 490:119543c9f674 3887 * @param htim : TIM handle.
mbed_official 490:119543c9f674 3888 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official 490:119543c9f674 3889 * contains the selected trigger (internal trigger input, filtered
mbed_official 490:119543c9f674 3890 * timer input or external trigger input) and the ) and the Slave
mbed_official 490:119543c9f674 3891 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official 490:119543c9f674 3892 * @retval HAL status
mbed_official 490:119543c9f674 3893 */
mbed_official 490:119543c9f674 3894 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
mbed_official 490:119543c9f674 3895 TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 490:119543c9f674 3896 {
mbed_official 490:119543c9f674 3897 /* Check the parameters */
mbed_official 490:119543c9f674 3898 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 3899 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official 490:119543c9f674 3900 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official 490:119543c9f674 3901
mbed_official 490:119543c9f674 3902 __HAL_LOCK(htim);
mbed_official 490:119543c9f674 3903
mbed_official 490:119543c9f674 3904 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 490:119543c9f674 3905
mbed_official 490:119543c9f674 3906 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
mbed_official 490:119543c9f674 3907
mbed_official 490:119543c9f674 3908 /* Enable Trigger Interrupt */
mbed_official 490:119543c9f674 3909 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
mbed_official 490:119543c9f674 3910
mbed_official 490:119543c9f674 3911 /* Disable Trigger DMA request */
mbed_official 490:119543c9f674 3912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
mbed_official 490:119543c9f674 3913
mbed_official 490:119543c9f674 3914 htim->State = HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 3915
mbed_official 490:119543c9f674 3916 __HAL_UNLOCK(htim);
mbed_official 490:119543c9f674 3917
mbed_official 490:119543c9f674 3918 return HAL_OK;
mbed_official 490:119543c9f674 3919 }
mbed_official 490:119543c9f674 3920
mbed_official 490:119543c9f674 3921 /**
mbed_official 376:cb4d9db17537 3922 * @brief Read the captured value from Capture Compare unit
mbed_official 490:119543c9f674 3923 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 3924 * @param Channel: TIM Channels to be enabled.
mbed_official 376:cb4d9db17537 3925 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 3926 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 376:cb4d9db17537 3927 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 376:cb4d9db17537 3928 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 376:cb4d9db17537 3929 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 376:cb4d9db17537 3930 * @retval Captured value
mbed_official 376:cb4d9db17537 3931 */
mbed_official 376:cb4d9db17537 3932 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 376:cb4d9db17537 3933 {
mbed_official 376:cb4d9db17537 3934 uint32_t tmpreg = 0;
mbed_official 376:cb4d9db17537 3935
mbed_official 376:cb4d9db17537 3936 __HAL_LOCK(htim);
mbed_official 376:cb4d9db17537 3937
mbed_official 376:cb4d9db17537 3938 switch (Channel)
mbed_official 376:cb4d9db17537 3939 {
mbed_official 376:cb4d9db17537 3940 case TIM_CHANNEL_1:
mbed_official 376:cb4d9db17537 3941 {
mbed_official 376:cb4d9db17537 3942 /* Check the parameters */
mbed_official 376:cb4d9db17537 3943 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3944
mbed_official 376:cb4d9db17537 3945 /* Return the capture 1 value */
mbed_official 376:cb4d9db17537 3946 tmpreg = htim->Instance->CCR1;
mbed_official 376:cb4d9db17537 3947
mbed_official 376:cb4d9db17537 3948 break;
mbed_official 376:cb4d9db17537 3949 }
mbed_official 376:cb4d9db17537 3950 case TIM_CHANNEL_2:
mbed_official 376:cb4d9db17537 3951 {
mbed_official 376:cb4d9db17537 3952 /* Check the parameters */
mbed_official 376:cb4d9db17537 3953 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3954
mbed_official 376:cb4d9db17537 3955 /* Return the capture 2 value */
mbed_official 376:cb4d9db17537 3956 tmpreg = htim->Instance->CCR2;
mbed_official 376:cb4d9db17537 3957
mbed_official 376:cb4d9db17537 3958 break;
mbed_official 376:cb4d9db17537 3959 }
mbed_official 376:cb4d9db17537 3960
mbed_official 376:cb4d9db17537 3961 case TIM_CHANNEL_3:
mbed_official 376:cb4d9db17537 3962 {
mbed_official 376:cb4d9db17537 3963 /* Check the parameters */
mbed_official 376:cb4d9db17537 3964 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3965
mbed_official 376:cb4d9db17537 3966 /* Return the capture 3 value */
mbed_official 376:cb4d9db17537 3967 tmpreg = htim->Instance->CCR3;
mbed_official 376:cb4d9db17537 3968
mbed_official 376:cb4d9db17537 3969 break;
mbed_official 376:cb4d9db17537 3970 }
mbed_official 376:cb4d9db17537 3971
mbed_official 376:cb4d9db17537 3972 case TIM_CHANNEL_4:
mbed_official 376:cb4d9db17537 3973 {
mbed_official 376:cb4d9db17537 3974 /* Check the parameters */
mbed_official 376:cb4d9db17537 3975 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 376:cb4d9db17537 3976
mbed_official 376:cb4d9db17537 3977 /* Return the capture 4 value */
mbed_official 376:cb4d9db17537 3978 tmpreg = htim->Instance->CCR4;
mbed_official 376:cb4d9db17537 3979
mbed_official 376:cb4d9db17537 3980 break;
mbed_official 376:cb4d9db17537 3981 }
mbed_official 376:cb4d9db17537 3982
mbed_official 376:cb4d9db17537 3983 default:
mbed_official 376:cb4d9db17537 3984 break;
mbed_official 376:cb4d9db17537 3985 }
mbed_official 376:cb4d9db17537 3986
mbed_official 376:cb4d9db17537 3987 __HAL_UNLOCK(htim);
mbed_official 376:cb4d9db17537 3988 return tmpreg;
mbed_official 376:cb4d9db17537 3989 }
mbed_official 376:cb4d9db17537 3990
mbed_official 376:cb4d9db17537 3991 /**
mbed_official 376:cb4d9db17537 3992 * @}
mbed_official 376:cb4d9db17537 3993 */
mbed_official 376:cb4d9db17537 3994
mbed_official 490:119543c9f674 3995 /** @addtogroup TIM_Exported_Functions_Group9
mbed_official 376:cb4d9db17537 3996 * @brief TIM Callbacks functions
mbed_official 376:cb4d9db17537 3997 *
mbed_official 376:cb4d9db17537 3998 @verbatim
mbed_official 376:cb4d9db17537 3999 ==============================================================================
mbed_official 376:cb4d9db17537 4000 ##### TIM Callbacks functions #####
mbed_official 376:cb4d9db17537 4001 ==============================================================================
mbed_official 376:cb4d9db17537 4002 [..]
mbed_official 376:cb4d9db17537 4003 This section provides TIM callback functions:
mbed_official 376:cb4d9db17537 4004 (+) Timer Period elapsed callback
mbed_official 376:cb4d9db17537 4005 (+) Timer Output Compare callback
mbed_official 376:cb4d9db17537 4006 (+) Timer Input capture callback
mbed_official 376:cb4d9db17537 4007 (+) Timer Trigger callback
mbed_official 376:cb4d9db17537 4008 (+) Timer Error callback
mbed_official 376:cb4d9db17537 4009
mbed_official 376:cb4d9db17537 4010 @endverbatim
mbed_official 376:cb4d9db17537 4011 * @{
mbed_official 376:cb4d9db17537 4012 */
mbed_official 376:cb4d9db17537 4013
mbed_official 376:cb4d9db17537 4014 /**
mbed_official 376:cb4d9db17537 4015 * @brief Period elapsed callback in non blocking mode
mbed_official 490:119543c9f674 4016 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 4017 * @retval None
mbed_official 376:cb4d9db17537 4018 */
mbed_official 376:cb4d9db17537 4019 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4020 {
mbed_official 376:cb4d9db17537 4021 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 376:cb4d9db17537 4022 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
mbed_official 376:cb4d9db17537 4023 */
mbed_official 376:cb4d9db17537 4024
mbed_official 376:cb4d9db17537 4025 }
mbed_official 376:cb4d9db17537 4026 /**
mbed_official 376:cb4d9db17537 4027 * @brief Output Compare callback in non blocking mode
mbed_official 490:119543c9f674 4028 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 4029 * @retval None
mbed_official 376:cb4d9db17537 4030 */
mbed_official 376:cb4d9db17537 4031 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4032 {
mbed_official 376:cb4d9db17537 4033 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 376:cb4d9db17537 4034 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
mbed_official 376:cb4d9db17537 4035 */
mbed_official 376:cb4d9db17537 4036 }
mbed_official 376:cb4d9db17537 4037 /**
mbed_official 376:cb4d9db17537 4038 * @brief Input Capture callback in non blocking mode
mbed_official 376:cb4d9db17537 4039 * @param htim: TIM IC handle
mbed_official 376:cb4d9db17537 4040 * @retval None
mbed_official 376:cb4d9db17537 4041 */
mbed_official 376:cb4d9db17537 4042 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4043 {
mbed_official 376:cb4d9db17537 4044 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 376:cb4d9db17537 4045 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
mbed_official 376:cb4d9db17537 4046 */
mbed_official 376:cb4d9db17537 4047 }
mbed_official 376:cb4d9db17537 4048
mbed_official 376:cb4d9db17537 4049 /**
mbed_official 376:cb4d9db17537 4050 * @brief PWM Pulse finished callback in non blocking mode
mbed_official 490:119543c9f674 4051 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 4052 * @retval None
mbed_official 376:cb4d9db17537 4053 */
mbed_official 376:cb4d9db17537 4054 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4055 {
mbed_official 376:cb4d9db17537 4056 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 376:cb4d9db17537 4057 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
mbed_official 376:cb4d9db17537 4058 */
mbed_official 376:cb4d9db17537 4059 }
mbed_official 376:cb4d9db17537 4060
mbed_official 376:cb4d9db17537 4061 /**
mbed_official 376:cb4d9db17537 4062 * @brief Hall Trigger detection callback in non blocking mode
mbed_official 490:119543c9f674 4063 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 4064 * @retval None
mbed_official 376:cb4d9db17537 4065 */
mbed_official 376:cb4d9db17537 4066 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4067 {
mbed_official 376:cb4d9db17537 4068 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 376:cb4d9db17537 4069 the HAL_TIM_TriggerCallback could be implemented in the user file
mbed_official 376:cb4d9db17537 4070 */
mbed_official 376:cb4d9db17537 4071 }
mbed_official 376:cb4d9db17537 4072
mbed_official 376:cb4d9db17537 4073 /**
mbed_official 376:cb4d9db17537 4074 * @brief Timer error callback in non blocking mode
mbed_official 490:119543c9f674 4075 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 4076 * @retval None
mbed_official 376:cb4d9db17537 4077 */
mbed_official 376:cb4d9db17537 4078 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4079 {
mbed_official 376:cb4d9db17537 4080 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 376:cb4d9db17537 4081 the HAL_TIM_ErrorCallback could be implemented in the user file
mbed_official 376:cb4d9db17537 4082 */
mbed_official 376:cb4d9db17537 4083 }
mbed_official 376:cb4d9db17537 4084
mbed_official 376:cb4d9db17537 4085 /**
mbed_official 376:cb4d9db17537 4086 * @}
mbed_official 376:cb4d9db17537 4087 */
mbed_official 376:cb4d9db17537 4088
mbed_official 490:119543c9f674 4089 /** @addtogroup TIM_Exported_Functions_Group10
mbed_official 376:cb4d9db17537 4090 * @brief Peripheral State functions
mbed_official 376:cb4d9db17537 4091 *
mbed_official 376:cb4d9db17537 4092 @verbatim
mbed_official 376:cb4d9db17537 4093 ==============================================================================
mbed_official 376:cb4d9db17537 4094 ##### Peripheral State functions #####
mbed_official 376:cb4d9db17537 4095 ==============================================================================
mbed_official 376:cb4d9db17537 4096 [..]
mbed_official 376:cb4d9db17537 4097 This subsection permits to get in run-time the status of the peripheral
mbed_official 376:cb4d9db17537 4098 and the data flow.
mbed_official 376:cb4d9db17537 4099
mbed_official 376:cb4d9db17537 4100 @endverbatim
mbed_official 376:cb4d9db17537 4101 * @{
mbed_official 376:cb4d9db17537 4102 */
mbed_official 376:cb4d9db17537 4103
mbed_official 376:cb4d9db17537 4104 /**
mbed_official 376:cb4d9db17537 4105 * @brief Return the TIM Base state
mbed_official 490:119543c9f674 4106 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 4107 * @retval HAL state
mbed_official 376:cb4d9db17537 4108 */
mbed_official 376:cb4d9db17537 4109 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4110 {
mbed_official 376:cb4d9db17537 4111 return htim->State;
mbed_official 376:cb4d9db17537 4112 }
mbed_official 376:cb4d9db17537 4113
mbed_official 376:cb4d9db17537 4114 /**
mbed_official 376:cb4d9db17537 4115 * @brief Return the TIM OC state
mbed_official 376:cb4d9db17537 4116 * @param htim: TIM Ouput Compare handle
mbed_official 376:cb4d9db17537 4117 * @retval HAL state
mbed_official 376:cb4d9db17537 4118 */
mbed_official 376:cb4d9db17537 4119 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4120 {
mbed_official 376:cb4d9db17537 4121 return htim->State;
mbed_official 376:cb4d9db17537 4122 }
mbed_official 376:cb4d9db17537 4123
mbed_official 376:cb4d9db17537 4124 /**
mbed_official 376:cb4d9db17537 4125 * @brief Return the TIM PWM state
mbed_official 490:119543c9f674 4126 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 4127 * @retval HAL state
mbed_official 376:cb4d9db17537 4128 */
mbed_official 376:cb4d9db17537 4129 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4130 {
mbed_official 376:cb4d9db17537 4131 return htim->State;
mbed_official 376:cb4d9db17537 4132 }
mbed_official 376:cb4d9db17537 4133
mbed_official 376:cb4d9db17537 4134 /**
mbed_official 376:cb4d9db17537 4135 * @brief Return the TIM Input Capture state
mbed_official 490:119543c9f674 4136 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 4137 * @retval HAL state
mbed_official 376:cb4d9db17537 4138 */
mbed_official 376:cb4d9db17537 4139 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4140 {
mbed_official 376:cb4d9db17537 4141 return htim->State;
mbed_official 376:cb4d9db17537 4142 }
mbed_official 376:cb4d9db17537 4143
mbed_official 376:cb4d9db17537 4144 /**
mbed_official 376:cb4d9db17537 4145 * @brief Return the TIM One Pulse Mode state
mbed_official 376:cb4d9db17537 4146 * @param htim: TIM OPM handle
mbed_official 376:cb4d9db17537 4147 * @retval HAL state
mbed_official 376:cb4d9db17537 4148 */
mbed_official 376:cb4d9db17537 4149 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4150 {
mbed_official 376:cb4d9db17537 4151 return htim->State;
mbed_official 376:cb4d9db17537 4152 }
mbed_official 376:cb4d9db17537 4153
mbed_official 376:cb4d9db17537 4154 /**
mbed_official 376:cb4d9db17537 4155 * @brief Return the TIM Encoder Mode state
mbed_official 490:119543c9f674 4156 * @param htim : TIM handle
mbed_official 376:cb4d9db17537 4157 * @retval HAL state
mbed_official 376:cb4d9db17537 4158 */
mbed_official 376:cb4d9db17537 4159 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
mbed_official 376:cb4d9db17537 4160 {
mbed_official 376:cb4d9db17537 4161 return htim->State;
mbed_official 376:cb4d9db17537 4162 }
mbed_official 376:cb4d9db17537 4163
mbed_official 490:119543c9f674 4164
mbed_official 376:cb4d9db17537 4165
mbed_official 376:cb4d9db17537 4166 /**
mbed_official 376:cb4d9db17537 4167 * @brief TIM DMA error callback
mbed_official 376:cb4d9db17537 4168 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 376:cb4d9db17537 4169 * the configuration information for the specified DMA module.
mbed_official 376:cb4d9db17537 4170 * @retval None
mbed_official 376:cb4d9db17537 4171 */
mbed_official 490:119543c9f674 4172 void TIM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 376:cb4d9db17537 4173 {
mbed_official 376:cb4d9db17537 4174 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 376:cb4d9db17537 4175
mbed_official 376:cb4d9db17537 4176 htim->State= HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 4177
mbed_official 376:cb4d9db17537 4178 HAL_TIM_ErrorCallback(htim);
mbed_official 376:cb4d9db17537 4179 }
mbed_official 376:cb4d9db17537 4180
mbed_official 376:cb4d9db17537 4181 /**
mbed_official 376:cb4d9db17537 4182 * @brief TIM DMA Delay Pulse complete callback.
mbed_official 490:119543c9f674 4183 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 376:cb4d9db17537 4184 * the configuration information for the specified DMA module.
mbed_official 376:cb4d9db17537 4185 * @retval None
mbed_official 376:cb4d9db17537 4186 */
mbed_official 490:119543c9f674 4187 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
mbed_official 376:cb4d9db17537 4188 {
mbed_official 376:cb4d9db17537 4189 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 376:cb4d9db17537 4190
mbed_official 376:cb4d9db17537 4191 htim->State= HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 4192
mbed_official 490:119543c9f674 4193 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
mbed_official 490:119543c9f674 4194 {
mbed_official 490:119543c9f674 4195 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 490:119543c9f674 4196 }
mbed_official 490:119543c9f674 4197 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
mbed_official 490:119543c9f674 4198 {
mbed_official 490:119543c9f674 4199 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 490:119543c9f674 4200 }
mbed_official 490:119543c9f674 4201 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
mbed_official 490:119543c9f674 4202 {
mbed_official 490:119543c9f674 4203 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 490:119543c9f674 4204 }
mbed_official 490:119543c9f674 4205 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
mbed_official 490:119543c9f674 4206 {
mbed_official 490:119543c9f674 4207 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 490:119543c9f674 4208 }
mbed_official 376:cb4d9db17537 4209 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 490:119543c9f674 4210
mbed_official 490:119543c9f674 4211 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 376:cb4d9db17537 4212 }
mbed_official 376:cb4d9db17537 4213 /**
mbed_official 376:cb4d9db17537 4214 * @brief TIM DMA Capture complete callback.
mbed_official 490:119543c9f674 4215 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 376:cb4d9db17537 4216 * the configuration information for the specified DMA module.
mbed_official 376:cb4d9db17537 4217 * @retval None
mbed_official 376:cb4d9db17537 4218 */
mbed_official 490:119543c9f674 4219 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
mbed_official 376:cb4d9db17537 4220 {
mbed_official 376:cb4d9db17537 4221 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 490:119543c9f674 4222
mbed_official 490:119543c9f674 4223 htim->State= HAL_TIM_STATE_READY;
mbed_official 490:119543c9f674 4224
mbed_official 490:119543c9f674 4225 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
mbed_official 490:119543c9f674 4226 {
mbed_official 490:119543c9f674 4227 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 490:119543c9f674 4228 }
mbed_official 490:119543c9f674 4229 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
mbed_official 490:119543c9f674 4230 {
mbed_official 490:119543c9f674 4231 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 490:119543c9f674 4232 }
mbed_official 490:119543c9f674 4233 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
mbed_official 490:119543c9f674 4234 {
mbed_official 490:119543c9f674 4235 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 490:119543c9f674 4236 }
mbed_official 490:119543c9f674 4237 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
mbed_official 490:119543c9f674 4238 {
mbed_official 490:119543c9f674 4239 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 490:119543c9f674 4240 }
mbed_official 490:119543c9f674 4241
mbed_official 490:119543c9f674 4242 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 490:119543c9f674 4243
mbed_official 490:119543c9f674 4244 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 376:cb4d9db17537 4245 }
mbed_official 376:cb4d9db17537 4246
mbed_official 490:119543c9f674 4247
mbed_official 376:cb4d9db17537 4248 /**
mbed_official 376:cb4d9db17537 4249 * @}
mbed_official 376:cb4d9db17537 4250 */
mbed_official 376:cb4d9db17537 4251
mbed_official 376:cb4d9db17537 4252 /**
mbed_official 490:119543c9f674 4253 * @}
mbed_official 490:119543c9f674 4254 */
mbed_official 490:119543c9f674 4255 /*************************************************************/
mbed_official 490:119543c9f674 4256 /* Private functions */
mbed_official 490:119543c9f674 4257 /*************************************************************/
mbed_official 490:119543c9f674 4258
mbed_official 490:119543c9f674 4259 /** @defgroup TIM_Private_Functions TIM Private Functions
mbed_official 490:119543c9f674 4260 * @{
mbed_official 490:119543c9f674 4261 */
mbed_official 490:119543c9f674 4262 /**
mbed_official 376:cb4d9db17537 4263 * @brief TIM DMA Period Elapse complete callback.
mbed_official 490:119543c9f674 4264 * @param hdma : pointer to DMA handle.
mbed_official 376:cb4d9db17537 4265 * @retval None
mbed_official 376:cb4d9db17537 4266 */
mbed_official 376:cb4d9db17537 4267 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
mbed_official 376:cb4d9db17537 4268 {
mbed_official 376:cb4d9db17537 4269 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 376:cb4d9db17537 4270
mbed_official 376:cb4d9db17537 4271 htim->State= HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 4272
mbed_official 376:cb4d9db17537 4273 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 376:cb4d9db17537 4274 }
mbed_official 376:cb4d9db17537 4275
mbed_official 376:cb4d9db17537 4276
mbed_official 376:cb4d9db17537 4277 /**
mbed_official 376:cb4d9db17537 4278 * @brief TIM DMA Trigger callback.
mbed_official 490:119543c9f674 4279 * @param hdma : pointer to DMA handle.
mbed_official 376:cb4d9db17537 4280 * @retval None
mbed_official 376:cb4d9db17537 4281 */
mbed_official 376:cb4d9db17537 4282 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
mbed_official 376:cb4d9db17537 4283 {
mbed_official 376:cb4d9db17537 4284 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 376:cb4d9db17537 4285
mbed_official 376:cb4d9db17537 4286 htim->State= HAL_TIM_STATE_READY;
mbed_official 376:cb4d9db17537 4287
mbed_official 376:cb4d9db17537 4288 HAL_TIM_TriggerCallback(htim);
mbed_official 376:cb4d9db17537 4289 }
mbed_official 376:cb4d9db17537 4290
mbed_official 376:cb4d9db17537 4291 /**
mbed_official 376:cb4d9db17537 4292 * @brief Time Base configuration
mbed_official 490:119543c9f674 4293 * @param TIMx : TIM peripheral
mbed_official 490:119543c9f674 4294 * @param Structure : TIM Base configuration structure
mbed_official 376:cb4d9db17537 4295 * @retval None
mbed_official 376:cb4d9db17537 4296 */
mbed_official 376:cb4d9db17537 4297 static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
mbed_official 376:cb4d9db17537 4298 {
mbed_official 376:cb4d9db17537 4299 uint32_t tmpcr1 = 0;
mbed_official 376:cb4d9db17537 4300 tmpcr1 = TIMx->CR1;
mbed_official 376:cb4d9db17537 4301
mbed_official 376:cb4d9db17537 4302 /* Set TIM Time Base Unit parameters ---------------------------------------*/
mbed_official 490:119543c9f674 4303 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
mbed_official 376:cb4d9db17537 4304 {
mbed_official 376:cb4d9db17537 4305 /* Select the Counter Mode */
mbed_official 376:cb4d9db17537 4306 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
mbed_official 376:cb4d9db17537 4307 tmpcr1 |= Structure->CounterMode;
mbed_official 376:cb4d9db17537 4308 }
mbed_official 376:cb4d9db17537 4309
mbed_official 376:cb4d9db17537 4310 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
mbed_official 376:cb4d9db17537 4311 {
mbed_official 376:cb4d9db17537 4312 /* Set the clock division */
mbed_official 376:cb4d9db17537 4313 tmpcr1 &= ~TIM_CR1_CKD;
mbed_official 376:cb4d9db17537 4314 tmpcr1 |= (uint32_t)Structure->ClockDivision;
mbed_official 376:cb4d9db17537 4315 }
mbed_official 376:cb4d9db17537 4316
mbed_official 376:cb4d9db17537 4317 TIMx->CR1 = tmpcr1;
mbed_official 376:cb4d9db17537 4318
mbed_official 376:cb4d9db17537 4319 /* Set the Autoreload value */
mbed_official 376:cb4d9db17537 4320 TIMx->ARR = (uint32_t)Structure->Period ;
mbed_official 376:cb4d9db17537 4321
mbed_official 376:cb4d9db17537 4322 /* Set the Prescaler value */
mbed_official 376:cb4d9db17537 4323 TIMx->PSC = (uint32_t)Structure->Prescaler;
mbed_official 376:cb4d9db17537 4324
mbed_official 376:cb4d9db17537 4325 /* Generate an update event to reload the Prescaler value immediatly */
mbed_official 376:cb4d9db17537 4326 TIMx->EGR = TIM_EGR_UG;
mbed_official 376:cb4d9db17537 4327 }
mbed_official 376:cb4d9db17537 4328
mbed_official 376:cb4d9db17537 4329 /**
mbed_official 376:cb4d9db17537 4330 * @brief Time Ouput Compare 1 configuration
mbed_official 376:cb4d9db17537 4331 * @param TIMx to select the TIM peripheral
mbed_official 376:cb4d9db17537 4332 * @param OC_Config: The ouput configuration structure
mbed_official 376:cb4d9db17537 4333 * @retval None
mbed_official 376:cb4d9db17537 4334 */
mbed_official 376:cb4d9db17537 4335 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 376:cb4d9db17537 4336 {
mbed_official 376:cb4d9db17537 4337 uint32_t tmpccmrx = 0;
mbed_official 376:cb4d9db17537 4338 uint32_t tmpccer = 0;
mbed_official 376:cb4d9db17537 4339 uint32_t tmpcr2 = 0;
mbed_official 376:cb4d9db17537 4340
mbed_official 376:cb4d9db17537 4341 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 376:cb4d9db17537 4342 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 376:cb4d9db17537 4343
mbed_official 376:cb4d9db17537 4344 /* Get the TIMx CCER register value */
mbed_official 376:cb4d9db17537 4345 tmpccer = TIMx->CCER;
mbed_official 376:cb4d9db17537 4346 /* Get the TIMx CR2 register value */
mbed_official 376:cb4d9db17537 4347 tmpcr2 = TIMx->CR2;
mbed_official 376:cb4d9db17537 4348
mbed_official 376:cb4d9db17537 4349 /* Get the TIMx CCMR1 register value */
mbed_official 376:cb4d9db17537 4350 tmpccmrx = TIMx->CCMR1;
mbed_official 376:cb4d9db17537 4351
mbed_official 376:cb4d9db17537 4352 /* Reset the Output Compare Mode Bits */
mbed_official 376:cb4d9db17537 4353 tmpccmrx &= ~TIM_CCMR1_OC1M;
mbed_official 376:cb4d9db17537 4354 tmpccmrx &= ~TIM_CCMR1_CC1S;
mbed_official 376:cb4d9db17537 4355 /* Select the Output Compare Mode */
mbed_official 376:cb4d9db17537 4356 tmpccmrx |= OC_Config->OCMode;
mbed_official 376:cb4d9db17537 4357
mbed_official 376:cb4d9db17537 4358 /* Reset the Output Polarity level */
mbed_official 376:cb4d9db17537 4359 tmpccer &= ~TIM_CCER_CC1P;
mbed_official 376:cb4d9db17537 4360 /* Set the Output Compare Polarity */
mbed_official 376:cb4d9db17537 4361 tmpccer |= OC_Config->OCPolarity;
mbed_official 376:cb4d9db17537 4362
mbed_official 376:cb4d9db17537 4363 /* Write to TIMx CR2 */
mbed_official 376:cb4d9db17537 4364 TIMx->CR2 = tmpcr2;
mbed_official 376:cb4d9db17537 4365
mbed_official 376:cb4d9db17537 4366 /* Write to TIMx CCMR1 */
mbed_official 376:cb4d9db17537 4367 TIMx->CCMR1 = tmpccmrx;
mbed_official 376:cb4d9db17537 4368
mbed_official 376:cb4d9db17537 4369 /* Set the Capture Compare Register value */
mbed_official 376:cb4d9db17537 4370 TIMx->CCR1 = OC_Config->Pulse;
mbed_official 376:cb4d9db17537 4371
mbed_official 376:cb4d9db17537 4372 /* Write to TIMx CCER */
mbed_official 376:cb4d9db17537 4373 TIMx->CCER = tmpccer;
mbed_official 376:cb4d9db17537 4374 }
mbed_official 376:cb4d9db17537 4375
mbed_official 376:cb4d9db17537 4376 /**
mbed_official 376:cb4d9db17537 4377 * @brief Time Ouput Compare 2 configuration
mbed_official 376:cb4d9db17537 4378 * @param TIMx to select the TIM peripheral
mbed_official 376:cb4d9db17537 4379 * @param OC_Config: The ouput configuration structure
mbed_official 376:cb4d9db17537 4380 * @retval None
mbed_official 376:cb4d9db17537 4381 */
mbed_official 376:cb4d9db17537 4382 static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 376:cb4d9db17537 4383 {
mbed_official 376:cb4d9db17537 4384 uint32_t tmpccmrx = 0;
mbed_official 376:cb4d9db17537 4385 uint32_t tmpccer = 0;
mbed_official 376:cb4d9db17537 4386 uint32_t tmpcr2 = 0;
mbed_official 376:cb4d9db17537 4387
mbed_official 376:cb4d9db17537 4388 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 376:cb4d9db17537 4389 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 376:cb4d9db17537 4390
mbed_official 376:cb4d9db17537 4391 /* Get the TIMx CCER register value */
mbed_official 376:cb4d9db17537 4392 tmpccer = TIMx->CCER;
mbed_official 376:cb4d9db17537 4393 /* Get the TIMx CR2 register value */
mbed_official 376:cb4d9db17537 4394 tmpcr2 = TIMx->CR2;
mbed_official 376:cb4d9db17537 4395
mbed_official 376:cb4d9db17537 4396 /* Get the TIMx CCMR1 register value */
mbed_official 376:cb4d9db17537 4397 tmpccmrx = TIMx->CCMR1;
mbed_official 376:cb4d9db17537 4398
mbed_official 376:cb4d9db17537 4399 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 376:cb4d9db17537 4400 tmpccmrx &= ~TIM_CCMR1_OC2M;
mbed_official 376:cb4d9db17537 4401 tmpccmrx &= ~TIM_CCMR1_CC2S;
mbed_official 376:cb4d9db17537 4402
mbed_official 376:cb4d9db17537 4403 /* Select the Output Compare Mode */
mbed_official 376:cb4d9db17537 4404 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 376:cb4d9db17537 4405
mbed_official 376:cb4d9db17537 4406 /* Reset the Output Polarity level */
mbed_official 376:cb4d9db17537 4407 tmpccer &= ~TIM_CCER_CC2P;
mbed_official 376:cb4d9db17537 4408 /* Set the Output Compare Polarity */
mbed_official 376:cb4d9db17537 4409 tmpccer |= (OC_Config->OCPolarity << 4);
mbed_official 376:cb4d9db17537 4410
mbed_official 376:cb4d9db17537 4411 /* Write to TIMx CR2 */
mbed_official 376:cb4d9db17537 4412 TIMx->CR2 = tmpcr2;
mbed_official 376:cb4d9db17537 4413
mbed_official 376:cb4d9db17537 4414 /* Write to TIMx CCMR1 */
mbed_official 376:cb4d9db17537 4415 TIMx->CCMR1 = tmpccmrx;
mbed_official 376:cb4d9db17537 4416
mbed_official 376:cb4d9db17537 4417 /* Set the Capture Compare Register value */
mbed_official 376:cb4d9db17537 4418 TIMx->CCR2 = OC_Config->Pulse;
mbed_official 376:cb4d9db17537 4419
mbed_official 376:cb4d9db17537 4420 /* Write to TIMx CCER */
mbed_official 376:cb4d9db17537 4421 TIMx->CCER = tmpccer;
mbed_official 376:cb4d9db17537 4422 }
mbed_official 376:cb4d9db17537 4423
mbed_official 376:cb4d9db17537 4424 /**
mbed_official 376:cb4d9db17537 4425 * @brief Time Ouput Compare 3 configuration
mbed_official 376:cb4d9db17537 4426 * @param TIMx to select the TIM peripheral
mbed_official 376:cb4d9db17537 4427 * @param OC_Config: The ouput configuration structure
mbed_official 376:cb4d9db17537 4428 * @retval None
mbed_official 376:cb4d9db17537 4429 */
mbed_official 376:cb4d9db17537 4430 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 376:cb4d9db17537 4431 {
mbed_official 376:cb4d9db17537 4432 uint32_t tmpccmrx = 0;
mbed_official 376:cb4d9db17537 4433 uint32_t tmpccer = 0;
mbed_official 376:cb4d9db17537 4434 uint32_t tmpcr2 = 0;
mbed_official 376:cb4d9db17537 4435
mbed_official 376:cb4d9db17537 4436 /* Disable the Channel 3: Reset the CC2E Bit */
mbed_official 376:cb4d9db17537 4437 TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official 376:cb4d9db17537 4438
mbed_official 376:cb4d9db17537 4439 /* Get the TIMx CCER register value */
mbed_official 376:cb4d9db17537 4440 tmpccer = TIMx->CCER;
mbed_official 376:cb4d9db17537 4441 /* Get the TIMx CR2 register value */
mbed_official 376:cb4d9db17537 4442 tmpcr2 = TIMx->CR2;
mbed_official 376:cb4d9db17537 4443
mbed_official 376:cb4d9db17537 4444 /* Get the TIMx CCMR2 register value */
mbed_official 376:cb4d9db17537 4445 tmpccmrx = TIMx->CCMR2;
mbed_official 376:cb4d9db17537 4446
mbed_official 376:cb4d9db17537 4447 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 376:cb4d9db17537 4448 tmpccmrx &= ~TIM_CCMR2_OC3M;
mbed_official 376:cb4d9db17537 4449 tmpccmrx &= ~TIM_CCMR2_CC3S;
mbed_official 376:cb4d9db17537 4450 /* Select the Output Compare Mode */
mbed_official 376:cb4d9db17537 4451 tmpccmrx |= OC_Config->OCMode;
mbed_official 376:cb4d9db17537 4452
mbed_official 376:cb4d9db17537 4453 /* Reset the Output Polarity level */
mbed_official 376:cb4d9db17537 4454 tmpccer &= ~TIM_CCER_CC3P;
mbed_official 376:cb4d9db17537 4455 /* Set the Output Compare Polarity */
mbed_official 376:cb4d9db17537 4456 tmpccer |= (OC_Config->OCPolarity << 8);
mbed_official 376:cb4d9db17537 4457
mbed_official 376:cb4d9db17537 4458 /* Write to TIMx CR2 */
mbed_official 376:cb4d9db17537 4459 TIMx->CR2 = tmpcr2;
mbed_official 376:cb4d9db17537 4460
mbed_official 376:cb4d9db17537 4461 /* Write to TIMx CCMR2 */
mbed_official 376:cb4d9db17537 4462 TIMx->CCMR2 = tmpccmrx;
mbed_official 376:cb4d9db17537 4463
mbed_official 376:cb4d9db17537 4464 /* Set the Capture Compare Register value */
mbed_official 376:cb4d9db17537 4465 TIMx->CCR3 = OC_Config->Pulse;
mbed_official 376:cb4d9db17537 4466
mbed_official 376:cb4d9db17537 4467 /* Write to TIMx CCER */
mbed_official 376:cb4d9db17537 4468 TIMx->CCER = tmpccer;
mbed_official 376:cb4d9db17537 4469 }
mbed_official 376:cb4d9db17537 4470
mbed_official 376:cb4d9db17537 4471 /**
mbed_official 376:cb4d9db17537 4472 * @brief Time Ouput Compare 4 configuration
mbed_official 376:cb4d9db17537 4473 * @param TIMx to select the TIM peripheral
mbed_official 376:cb4d9db17537 4474 * @param OC_Config: The ouput configuration structure
mbed_official 376:cb4d9db17537 4475 * @retval None
mbed_official 376:cb4d9db17537 4476 */
mbed_official 376:cb4d9db17537 4477 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 376:cb4d9db17537 4478 {
mbed_official 376:cb4d9db17537 4479 uint32_t tmpccmrx = 0;
mbed_official 376:cb4d9db17537 4480 uint32_t tmpccer = 0;
mbed_official 376:cb4d9db17537 4481 uint32_t tmpcr2 = 0;
mbed_official 376:cb4d9db17537 4482
mbed_official 376:cb4d9db17537 4483 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 376:cb4d9db17537 4484 TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official 376:cb4d9db17537 4485
mbed_official 376:cb4d9db17537 4486 /* Get the TIMx CCER register value */
mbed_official 376:cb4d9db17537 4487 tmpccer = TIMx->CCER;
mbed_official 376:cb4d9db17537 4488 /* Get the TIMx CR2 register value */
mbed_official 376:cb4d9db17537 4489 tmpcr2 = TIMx->CR2;
mbed_official 376:cb4d9db17537 4490
mbed_official 376:cb4d9db17537 4491 /* Get the TIMx CCMR2 register value */
mbed_official 376:cb4d9db17537 4492 tmpccmrx = TIMx->CCMR2;
mbed_official 376:cb4d9db17537 4493
mbed_official 376:cb4d9db17537 4494 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 376:cb4d9db17537 4495 tmpccmrx &= ~TIM_CCMR2_OC4M;
mbed_official 376:cb4d9db17537 4496 tmpccmrx &= ~TIM_CCMR2_CC4S;
mbed_official 376:cb4d9db17537 4497
mbed_official 376:cb4d9db17537 4498 /* Select the Output Compare Mode */
mbed_official 376:cb4d9db17537 4499 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 376:cb4d9db17537 4500
mbed_official 376:cb4d9db17537 4501 /* Reset the Output Polarity level */
mbed_official 376:cb4d9db17537 4502 tmpccer &= ~TIM_CCER_CC4P;
mbed_official 376:cb4d9db17537 4503 /* Set the Output Compare Polarity */
mbed_official 376:cb4d9db17537 4504 tmpccer |= (OC_Config->OCPolarity << 12);
mbed_official 376:cb4d9db17537 4505
mbed_official 376:cb4d9db17537 4506 /* Write to TIMx CR2 */
mbed_official 376:cb4d9db17537 4507 TIMx->CR2 = tmpcr2;
mbed_official 376:cb4d9db17537 4508
mbed_official 376:cb4d9db17537 4509 /* Write to TIMx CCMR2 */
mbed_official 376:cb4d9db17537 4510 TIMx->CCMR2 = tmpccmrx;
mbed_official 376:cb4d9db17537 4511
mbed_official 376:cb4d9db17537 4512 /* Set the Capture Compare Register value */
mbed_official 376:cb4d9db17537 4513 TIMx->CCR4 = OC_Config->Pulse;
mbed_official 376:cb4d9db17537 4514
mbed_official 376:cb4d9db17537 4515 /* Write to TIMx CCER */
mbed_official 376:cb4d9db17537 4516 TIMx->CCER = tmpccer;
mbed_official 376:cb4d9db17537 4517 }
mbed_official 376:cb4d9db17537 4518
mbed_official 376:cb4d9db17537 4519 /**
mbed_official 376:cb4d9db17537 4520 * @brief Configure the TI1 as Input.
mbed_official 376:cb4d9db17537 4521 * @param TIMx to select the TIM peripheral.
mbed_official 376:cb4d9db17537 4522 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 376:cb4d9db17537 4523 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4524 * @arg TIM_ICPolarity_Rising
mbed_official 376:cb4d9db17537 4525 * @arg TIM_ICPolarity_Falling
mbed_official 376:cb4d9db17537 4526 * @arg TIM_ICPolarity_BothEdge
mbed_official 376:cb4d9db17537 4527 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 376:cb4d9db17537 4528 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4529 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
mbed_official 376:cb4d9db17537 4530 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
mbed_official 376:cb4d9db17537 4531 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
mbed_official 376:cb4d9db17537 4532 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 376:cb4d9db17537 4533 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 376:cb4d9db17537 4534 * @retval None
mbed_official 376:cb4d9db17537 4535 */
mbed_official 376:cb4d9db17537 4536 static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 376:cb4d9db17537 4537 uint32_t TIM_ICFilter)
mbed_official 376:cb4d9db17537 4538 {
mbed_official 376:cb4d9db17537 4539 uint32_t tmpccmr1 = 0;
mbed_official 376:cb4d9db17537 4540 uint32_t tmpccer = 0;
mbed_official 376:cb4d9db17537 4541
mbed_official 376:cb4d9db17537 4542 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 376:cb4d9db17537 4543 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 376:cb4d9db17537 4544 tmpccmr1 = TIMx->CCMR1;
mbed_official 376:cb4d9db17537 4545 tmpccer = TIMx->CCER;
mbed_official 376:cb4d9db17537 4546
mbed_official 376:cb4d9db17537 4547 /* Select the Input */
mbed_official 376:cb4d9db17537 4548 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
mbed_official 376:cb4d9db17537 4549 {
mbed_official 376:cb4d9db17537 4550 tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official 376:cb4d9db17537 4551 tmpccmr1 |= TIM_ICSelection;
mbed_official 376:cb4d9db17537 4552 }
mbed_official 376:cb4d9db17537 4553 else
mbed_official 376:cb4d9db17537 4554 {
mbed_official 376:cb4d9db17537 4555 tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official 376:cb4d9db17537 4556 tmpccmr1 |= TIM_CCMR1_CC1S_0;
mbed_official 376:cb4d9db17537 4557 }
mbed_official 376:cb4d9db17537 4558
mbed_official 376:cb4d9db17537 4559 /* Set the filter */
mbed_official 376:cb4d9db17537 4560 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 490:119543c9f674 4561 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
mbed_official 376:cb4d9db17537 4562
mbed_official 376:cb4d9db17537 4563 /* Select the Polarity and set the CC1E Bit */
mbed_official 376:cb4d9db17537 4564 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
mbed_official 490:119543c9f674 4565 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
mbed_official 376:cb4d9db17537 4566
mbed_official 376:cb4d9db17537 4567 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 376:cb4d9db17537 4568 TIMx->CCMR1 = tmpccmr1;
mbed_official 376:cb4d9db17537 4569 TIMx->CCER = tmpccer;
mbed_official 376:cb4d9db17537 4570 }
mbed_official 376:cb4d9db17537 4571
mbed_official 376:cb4d9db17537 4572 /**
mbed_official 376:cb4d9db17537 4573 * @brief Configure the Polarity and Filter for TI1.
mbed_official 376:cb4d9db17537 4574 * @param TIMx to select the TIM peripheral.
mbed_official 376:cb4d9db17537 4575 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 376:cb4d9db17537 4576 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4577 * @arg TIM_ICPolarity_Rising
mbed_official 376:cb4d9db17537 4578 * @arg TIM_ICPolarity_Falling
mbed_official 376:cb4d9db17537 4579 * @arg TIM_ICPolarity_BothEdge
mbed_official 376:cb4d9db17537 4580 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 376:cb4d9db17537 4581 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 376:cb4d9db17537 4582 * @retval None
mbed_official 376:cb4d9db17537 4583 */
mbed_official 376:cb4d9db17537 4584 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 376:cb4d9db17537 4585 {
mbed_official 376:cb4d9db17537 4586 uint32_t tmpccmr1 = 0;
mbed_official 376:cb4d9db17537 4587 uint32_t tmpccer = 0;
mbed_official 376:cb4d9db17537 4588
mbed_official 376:cb4d9db17537 4589 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 376:cb4d9db17537 4590 tmpccer = TIMx->CCER;
mbed_official 376:cb4d9db17537 4591 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 376:cb4d9db17537 4592 tmpccmr1 = TIMx->CCMR1;
mbed_official 376:cb4d9db17537 4593
mbed_official 376:cb4d9db17537 4594 /* Set the filter */
mbed_official 376:cb4d9db17537 4595 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 376:cb4d9db17537 4596 tmpccmr1 |= (TIM_ICFilter << 4);
mbed_official 376:cb4d9db17537 4597
mbed_official 376:cb4d9db17537 4598 /* Select the Polarity and set the CC1E Bit */
mbed_official 376:cb4d9db17537 4599 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
mbed_official 376:cb4d9db17537 4600 tmpccer |= TIM_ICPolarity;
mbed_official 376:cb4d9db17537 4601
mbed_official 376:cb4d9db17537 4602 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 376:cb4d9db17537 4603 TIMx->CCMR1 = tmpccmr1;
mbed_official 376:cb4d9db17537 4604 TIMx->CCER = tmpccer;
mbed_official 376:cb4d9db17537 4605 }
mbed_official 376:cb4d9db17537 4606
mbed_official 376:cb4d9db17537 4607 /**
mbed_official 376:cb4d9db17537 4608 * @brief Configure the TI2 as Input.
mbed_official 376:cb4d9db17537 4609 * @param TIMx to select the TIM peripheral
mbed_official 376:cb4d9db17537 4610 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 376:cb4d9db17537 4611 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4612 * @arg TIM_ICPolarity_Rising
mbed_official 376:cb4d9db17537 4613 * @arg TIM_ICPolarity_Falling
mbed_official 376:cb4d9db17537 4614 * @arg TIM_ICPolarity_BothEdge
mbed_official 376:cb4d9db17537 4615 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 376:cb4d9db17537 4616 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4617 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
mbed_official 376:cb4d9db17537 4618 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
mbed_official 376:cb4d9db17537 4619 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
mbed_official 376:cb4d9db17537 4620 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 376:cb4d9db17537 4621 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 376:cb4d9db17537 4622 * @retval None
mbed_official 376:cb4d9db17537 4623 */
mbed_official 376:cb4d9db17537 4624 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 376:cb4d9db17537 4625 uint32_t TIM_ICFilter)
mbed_official 376:cb4d9db17537 4626 {
mbed_official 376:cb4d9db17537 4627 uint32_t tmpccmr1 = 0;
mbed_official 376:cb4d9db17537 4628 uint32_t tmpccer = 0;
mbed_official 376:cb4d9db17537 4629
mbed_official 376:cb4d9db17537 4630 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 376:cb4d9db17537 4631 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 376:cb4d9db17537 4632 tmpccmr1 = TIMx->CCMR1;
mbed_official 376:cb4d9db17537 4633 tmpccer = TIMx->CCER;
mbed_official 376:cb4d9db17537 4634
mbed_official 376:cb4d9db17537 4635 /* Select the Input */
mbed_official 376:cb4d9db17537 4636 tmpccmr1 &= ~TIM_CCMR1_CC2S;
mbed_official 376:cb4d9db17537 4637 tmpccmr1 |= (TIM_ICSelection << 8);
mbed_official 376:cb4d9db17537 4638
mbed_official 376:cb4d9db17537 4639 /* Set the filter */
mbed_official 376:cb4d9db17537 4640 tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official 490:119543c9f674 4641 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
mbed_official 376:cb4d9db17537 4642
mbed_official 376:cb4d9db17537 4643 /* Select the Polarity and set the CC2E Bit */
mbed_official 376:cb4d9db17537 4644 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
mbed_official 490:119543c9f674 4645 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
mbed_official 376:cb4d9db17537 4646
mbed_official 376:cb4d9db17537 4647 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 376:cb4d9db17537 4648 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 376:cb4d9db17537 4649 TIMx->CCER = tmpccer;
mbed_official 376:cb4d9db17537 4650 }
mbed_official 376:cb4d9db17537 4651
mbed_official 376:cb4d9db17537 4652 /**
mbed_official 376:cb4d9db17537 4653 * @brief Configure the Polarity and Filter for TI2.
mbed_official 376:cb4d9db17537 4654 * @param TIMx to select the TIM peripheral.
mbed_official 376:cb4d9db17537 4655 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 376:cb4d9db17537 4656 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4657 * @arg TIM_ICPolarity_Rising
mbed_official 376:cb4d9db17537 4658 * @arg TIM_ICPolarity_Falling
mbed_official 376:cb4d9db17537 4659 * @arg TIM_ICPolarity_BothEdge
mbed_official 376:cb4d9db17537 4660 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 376:cb4d9db17537 4661 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 376:cb4d9db17537 4662 * @retval None
mbed_official 376:cb4d9db17537 4663 */
mbed_official 376:cb4d9db17537 4664 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 376:cb4d9db17537 4665 {
mbed_official 376:cb4d9db17537 4666 uint32_t tmpccmr1 = 0;
mbed_official 376:cb4d9db17537 4667 uint32_t tmpccer = 0;
mbed_official 376:cb4d9db17537 4668
mbed_official 376:cb4d9db17537 4669 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 376:cb4d9db17537 4670 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 376:cb4d9db17537 4671 tmpccmr1 = TIMx->CCMR1;
mbed_official 376:cb4d9db17537 4672 tmpccer = TIMx->CCER;
mbed_official 376:cb4d9db17537 4673
mbed_official 376:cb4d9db17537 4674 /* Set the filter */
mbed_official 376:cb4d9db17537 4675 tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official 376:cb4d9db17537 4676 tmpccmr1 |= (TIM_ICFilter << 12);
mbed_official 376:cb4d9db17537 4677
mbed_official 376:cb4d9db17537 4678 /* Select the Polarity and set the CC2E Bit */
mbed_official 376:cb4d9db17537 4679 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
mbed_official 376:cb4d9db17537 4680 tmpccer |= (TIM_ICPolarity << 4);
mbed_official 376:cb4d9db17537 4681
mbed_official 376:cb4d9db17537 4682 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 376:cb4d9db17537 4683 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 376:cb4d9db17537 4684 TIMx->CCER = tmpccer;
mbed_official 376:cb4d9db17537 4685 }
mbed_official 376:cb4d9db17537 4686
mbed_official 376:cb4d9db17537 4687 /**
mbed_official 376:cb4d9db17537 4688 * @brief Configure the TI3 as Input.
mbed_official 376:cb4d9db17537 4689 * @param TIMx to select the TIM peripheral
mbed_official 376:cb4d9db17537 4690 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 376:cb4d9db17537 4691 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4692 * @arg TIM_ICPolarity_Rising
mbed_official 376:cb4d9db17537 4693 * @arg TIM_ICPolarity_Falling
mbed_official 376:cb4d9db17537 4694 * @arg TIM_ICPolarity_BothEdge
mbed_official 376:cb4d9db17537 4695 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 376:cb4d9db17537 4696 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4697 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
mbed_official 376:cb4d9db17537 4698 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
mbed_official 376:cb4d9db17537 4699 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
mbed_official 376:cb4d9db17537 4700 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 376:cb4d9db17537 4701 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 376:cb4d9db17537 4702 * @retval None
mbed_official 376:cb4d9db17537 4703 */
mbed_official 376:cb4d9db17537 4704 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 376:cb4d9db17537 4705 uint32_t TIM_ICFilter)
mbed_official 376:cb4d9db17537 4706 {
mbed_official 376:cb4d9db17537 4707 uint32_t tmpccmr2 = 0;
mbed_official 376:cb4d9db17537 4708 uint32_t tmpccer = 0;
mbed_official 376:cb4d9db17537 4709
mbed_official 376:cb4d9db17537 4710 /* Disable the Channel 3: Reset the CC3E Bit */
mbed_official 376:cb4d9db17537 4711 TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official 376:cb4d9db17537 4712 tmpccmr2 = TIMx->CCMR2;
mbed_official 376:cb4d9db17537 4713 tmpccer = TIMx->CCER;
mbed_official 376:cb4d9db17537 4714
mbed_official 376:cb4d9db17537 4715 /* Select the Input */
mbed_official 376:cb4d9db17537 4716 tmpccmr2 &= ~TIM_CCMR2_CC3S;
mbed_official 376:cb4d9db17537 4717 tmpccmr2 |= TIM_ICSelection;
mbed_official 376:cb4d9db17537 4718
mbed_official 376:cb4d9db17537 4719 /* Set the filter */
mbed_official 376:cb4d9db17537 4720 tmpccmr2 &= ~TIM_CCMR2_IC3F;
mbed_official 490:119543c9f674 4721 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
mbed_official 376:cb4d9db17537 4722
mbed_official 376:cb4d9db17537 4723 /* Select the Polarity and set the CC3E Bit */
mbed_official 376:cb4d9db17537 4724 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
mbed_official 490:119543c9f674 4725 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
mbed_official 376:cb4d9db17537 4726
mbed_official 376:cb4d9db17537 4727 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 376:cb4d9db17537 4728 TIMx->CCMR2 = tmpccmr2;
mbed_official 376:cb4d9db17537 4729 TIMx->CCER = tmpccer;
mbed_official 376:cb4d9db17537 4730 }
mbed_official 376:cb4d9db17537 4731
mbed_official 376:cb4d9db17537 4732 /**
mbed_official 376:cb4d9db17537 4733 * @brief Configure the TI4 as Input.
mbed_official 376:cb4d9db17537 4734 * @param TIMx to select the TIM peripheral
mbed_official 376:cb4d9db17537 4735 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 376:cb4d9db17537 4736 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4737 * @arg TIM_ICPolarity_Rising
mbed_official 376:cb4d9db17537 4738 * @arg TIM_ICPolarity_Falling
mbed_official 376:cb4d9db17537 4739 * @arg TIM_ICPolarity_BothEdge
mbed_official 376:cb4d9db17537 4740 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 376:cb4d9db17537 4741 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4742 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
mbed_official 376:cb4d9db17537 4743 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
mbed_official 376:cb4d9db17537 4744 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
mbed_official 376:cb4d9db17537 4745 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 376:cb4d9db17537 4746 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 376:cb4d9db17537 4747 * @retval None
mbed_official 376:cb4d9db17537 4748 */
mbed_official 376:cb4d9db17537 4749 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 376:cb4d9db17537 4750 uint32_t TIM_ICFilter)
mbed_official 376:cb4d9db17537 4751 {
mbed_official 376:cb4d9db17537 4752 uint32_t tmpccmr2 = 0;
mbed_official 376:cb4d9db17537 4753 uint32_t tmpccer = 0;
mbed_official 376:cb4d9db17537 4754
mbed_official 376:cb4d9db17537 4755 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 376:cb4d9db17537 4756 TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official 376:cb4d9db17537 4757 tmpccmr2 = TIMx->CCMR2;
mbed_official 376:cb4d9db17537 4758 tmpccer = TIMx->CCER;
mbed_official 376:cb4d9db17537 4759
mbed_official 376:cb4d9db17537 4760 /* Select the Input */
mbed_official 376:cb4d9db17537 4761 tmpccmr2 &= ~TIM_CCMR2_CC4S;
mbed_official 376:cb4d9db17537 4762 tmpccmr2 |= (TIM_ICSelection << 8);
mbed_official 376:cb4d9db17537 4763
mbed_official 376:cb4d9db17537 4764 /* Set the filter */
mbed_official 376:cb4d9db17537 4765 tmpccmr2 &= ~TIM_CCMR2_IC4F;
mbed_official 490:119543c9f674 4766 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
mbed_official 376:cb4d9db17537 4767
mbed_official 376:cb4d9db17537 4768 /* Select the Polarity and set the CC4E Bit */
mbed_official 376:cb4d9db17537 4769 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
mbed_official 490:119543c9f674 4770 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
mbed_official 376:cb4d9db17537 4771
mbed_official 376:cb4d9db17537 4772 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 376:cb4d9db17537 4773 TIMx->CCMR2 = tmpccmr2;
mbed_official 376:cb4d9db17537 4774 TIMx->CCER = tmpccer ;
mbed_official 376:cb4d9db17537 4775 }
mbed_official 376:cb4d9db17537 4776
mbed_official 376:cb4d9db17537 4777 /**
mbed_official 376:cb4d9db17537 4778 * @brief Selects the Input Trigger source
mbed_official 376:cb4d9db17537 4779 * @param TIMx to select the TIM peripheral
mbed_official 376:cb4d9db17537 4780 * @param InputTriggerSource: The Input Trigger source.
mbed_official 376:cb4d9db17537 4781 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4782 * @arg TIM_TS_ITR0: Internal Trigger 0
mbed_official 376:cb4d9db17537 4783 * @arg TIM_TS_ITR1: Internal Trigger 1
mbed_official 376:cb4d9db17537 4784 * @arg TIM_TS_ITR2: Internal Trigger 2
mbed_official 376:cb4d9db17537 4785 * @arg TIM_TS_ITR3: Internal Trigger 3
mbed_official 376:cb4d9db17537 4786 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
mbed_official 376:cb4d9db17537 4787 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
mbed_official 376:cb4d9db17537 4788 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
mbed_official 376:cb4d9db17537 4789 * @arg TIM_TS_ETRF: External Trigger input
mbed_official 376:cb4d9db17537 4790 * @retval None
mbed_official 376:cb4d9db17537 4791 */
mbed_official 490:119543c9f674 4792 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
mbed_official 376:cb4d9db17537 4793 {
mbed_official 376:cb4d9db17537 4794 uint32_t tmpsmcr = 0;
mbed_official 376:cb4d9db17537 4795
mbed_official 376:cb4d9db17537 4796 /* Get the TIMx SMCR register value */
mbed_official 376:cb4d9db17537 4797 tmpsmcr = TIMx->SMCR;
mbed_official 376:cb4d9db17537 4798 /* Reset the TS Bits */
mbed_official 376:cb4d9db17537 4799 tmpsmcr &= ~TIM_SMCR_TS;
mbed_official 376:cb4d9db17537 4800 /* Set the Input Trigger source and the slave mode*/
mbed_official 490:119543c9f674 4801 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
mbed_official 376:cb4d9db17537 4802 /* Write to TIMx SMCR */
mbed_official 376:cb4d9db17537 4803 TIMx->SMCR = tmpsmcr;
mbed_official 376:cb4d9db17537 4804 }
mbed_official 376:cb4d9db17537 4805 /**
mbed_official 376:cb4d9db17537 4806 * @brief Configures the TIMx External Trigger (ETR).
mbed_official 376:cb4d9db17537 4807 * @param TIMx to select the TIM peripheral
mbed_official 376:cb4d9db17537 4808 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official 376:cb4d9db17537 4809 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4810 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
mbed_official 376:cb4d9db17537 4811 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official 376:cb4d9db17537 4812 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official 376:cb4d9db17537 4813 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official 376:cb4d9db17537 4814 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official 376:cb4d9db17537 4815 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4816 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official 376:cb4d9db17537 4817 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official 376:cb4d9db17537 4818 * @param ExtTRGFilter: External Trigger Filter.
mbed_official 376:cb4d9db17537 4819 * This parameter must be a value between 0x00 and 0x0F
mbed_official 376:cb4d9db17537 4820 * @retval None
mbed_official 376:cb4d9db17537 4821 */
mbed_official 376:cb4d9db17537 4822 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 376:cb4d9db17537 4823 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
mbed_official 376:cb4d9db17537 4824 {
mbed_official 376:cb4d9db17537 4825 uint32_t tmpsmcr = 0;
mbed_official 376:cb4d9db17537 4826
mbed_official 376:cb4d9db17537 4827 tmpsmcr = TIMx->SMCR;
mbed_official 376:cb4d9db17537 4828
mbed_official 376:cb4d9db17537 4829 /* Reset the ETR Bits */
mbed_official 376:cb4d9db17537 4830 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 376:cb4d9db17537 4831
mbed_official 376:cb4d9db17537 4832 /* Set the Prescaler, the Filter value and the Polarity */
mbed_official 376:cb4d9db17537 4833 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
mbed_official 376:cb4d9db17537 4834
mbed_official 376:cb4d9db17537 4835 /* Write to TIMx SMCR */
mbed_official 376:cb4d9db17537 4836 TIMx->SMCR = tmpsmcr;
mbed_official 376:cb4d9db17537 4837 }
mbed_official 376:cb4d9db17537 4838
mbed_official 376:cb4d9db17537 4839 /**
mbed_official 376:cb4d9db17537 4840 * @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official 376:cb4d9db17537 4841 * @param TIMx to select the TIM peripheral
mbed_official 376:cb4d9db17537 4842 * @param Channel: specifies the TIM Channel
mbed_official 376:cb4d9db17537 4843 * This parameter can be one of the following values:
mbed_official 376:cb4d9db17537 4844 * @arg TIM_Channel_1: TIM Channel 1
mbed_official 376:cb4d9db17537 4845 * @arg TIM_Channel_2: TIM Channel 2
mbed_official 376:cb4d9db17537 4846 * @arg TIM_Channel_3: TIM Channel 3
mbed_official 376:cb4d9db17537 4847 * @arg TIM_Channel_4: TIM Channel 4
mbed_official 376:cb4d9db17537 4848 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
mbed_official 376:cb4d9db17537 4849 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
mbed_official 376:cb4d9db17537 4850 * @retval None
mbed_official 376:cb4d9db17537 4851 */
mbed_official 376:cb4d9db17537 4852 static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
mbed_official 376:cb4d9db17537 4853 {
mbed_official 376:cb4d9db17537 4854 uint32_t tmp = 0;
mbed_official 376:cb4d9db17537 4855
mbed_official 376:cb4d9db17537 4856 /* Check the parameters */
mbed_official 490:119543c9f674 4857 assert_param(IS_TIM_CCX_INSTANCE(TIMx,Channel));
mbed_official 376:cb4d9db17537 4858
mbed_official 376:cb4d9db17537 4859 tmp = TIM_CCER_CC1E << Channel;
mbed_official 376:cb4d9db17537 4860
mbed_official 376:cb4d9db17537 4861 /* Reset the CCxE Bit */
mbed_official 376:cb4d9db17537 4862 TIMx->CCER &= ~tmp;
mbed_official 376:cb4d9db17537 4863
mbed_official 376:cb4d9db17537 4864 /* Set or reset the CCxE Bit */
mbed_official 376:cb4d9db17537 4865 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
mbed_official 376:cb4d9db17537 4866 }
mbed_official 490:119543c9f674 4867 /**
mbed_official 490:119543c9f674 4868 * @brief Set the slave timer configuration.
mbed_official 490:119543c9f674 4869 * @param htim : TIM handle
mbed_official 490:119543c9f674 4870 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official 490:119543c9f674 4871 * contains the selected trigger (internal trigger input, filtered
mbed_official 490:119543c9f674 4872 * timer input or external trigger input) and the ) and the Slave
mbed_official 490:119543c9f674 4873 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official 490:119543c9f674 4874 * @retval None
mbed_official 490:119543c9f674 4875 */
mbed_official 490:119543c9f674 4876 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
mbed_official 490:119543c9f674 4877 TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 490:119543c9f674 4878 {
mbed_official 490:119543c9f674 4879 uint32_t tmpsmcr = 0;
mbed_official 490:119543c9f674 4880 uint32_t tmpccmr1 = 0;
mbed_official 490:119543c9f674 4881 uint32_t tmpccer = 0;
mbed_official 490:119543c9f674 4882
mbed_official 490:119543c9f674 4883 /* Get the TIMx SMCR register value */
mbed_official 490:119543c9f674 4884 tmpsmcr = htim->Instance->SMCR;
mbed_official 490:119543c9f674 4885
mbed_official 490:119543c9f674 4886 /* Reset the Trigger Selection Bits */
mbed_official 490:119543c9f674 4887 tmpsmcr &= ~TIM_SMCR_TS;
mbed_official 490:119543c9f674 4888 /* Set the Input Trigger source */
mbed_official 490:119543c9f674 4889 tmpsmcr |= sSlaveConfig->InputTrigger;
mbed_official 490:119543c9f674 4890
mbed_official 490:119543c9f674 4891 /* Reset the slave mode Bits */
mbed_official 490:119543c9f674 4892 tmpsmcr &= ~TIM_SMCR_SMS;
mbed_official 490:119543c9f674 4893 /* Set the slave mode */
mbed_official 490:119543c9f674 4894 tmpsmcr |= sSlaveConfig->SlaveMode;
mbed_official 490:119543c9f674 4895
mbed_official 490:119543c9f674 4896 /* Write to TIMx SMCR */
mbed_official 490:119543c9f674 4897 htim->Instance->SMCR = tmpsmcr;
mbed_official 490:119543c9f674 4898
mbed_official 490:119543c9f674 4899 /* Configure the trigger prescaler, filter, and polarity */
mbed_official 490:119543c9f674 4900 switch (sSlaveConfig->InputTrigger)
mbed_official 490:119543c9f674 4901 {
mbed_official 490:119543c9f674 4902 case TIM_TS_ETRF:
mbed_official 490:119543c9f674 4903 {
mbed_official 490:119543c9f674 4904 /* Check the parameters */
mbed_official 490:119543c9f674 4905 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 4906 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
mbed_official 490:119543c9f674 4907 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 490:119543c9f674 4908 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 490:119543c9f674 4909 /* Configure the ETR Trigger source */
mbed_official 490:119543c9f674 4910 TIM_ETR_SetConfig(htim->Instance,
mbed_official 490:119543c9f674 4911 sSlaveConfig->TriggerPrescaler,
mbed_official 490:119543c9f674 4912 sSlaveConfig->TriggerPolarity,
mbed_official 490:119543c9f674 4913 sSlaveConfig->TriggerFilter);
mbed_official 490:119543c9f674 4914 }
mbed_official 490:119543c9f674 4915 break;
mbed_official 490:119543c9f674 4916
mbed_official 490:119543c9f674 4917 case TIM_TS_TI1F_ED:
mbed_official 490:119543c9f674 4918 {
mbed_official 490:119543c9f674 4919 /* Check the parameters */
mbed_official 490:119543c9f674 4920 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 4921 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 490:119543c9f674 4922
mbed_official 490:119543c9f674 4923 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 490:119543c9f674 4924 tmpccer = htim->Instance->CCER;
mbed_official 490:119543c9f674 4925 htim->Instance->CCER &= ~TIM_CCER_CC1E;
mbed_official 490:119543c9f674 4926 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 490:119543c9f674 4927
mbed_official 490:119543c9f674 4928 /* Set the filter */
mbed_official 490:119543c9f674 4929 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 490:119543c9f674 4930 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
mbed_official 490:119543c9f674 4931
mbed_official 490:119543c9f674 4932 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 490:119543c9f674 4933 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 490:119543c9f674 4934 htim->Instance->CCER = tmpccer;
mbed_official 490:119543c9f674 4935
mbed_official 490:119543c9f674 4936 }
mbed_official 490:119543c9f674 4937 break;
mbed_official 490:119543c9f674 4938
mbed_official 490:119543c9f674 4939 case TIM_TS_TI1FP1:
mbed_official 490:119543c9f674 4940 {
mbed_official 490:119543c9f674 4941 /* Check the parameters */
mbed_official 490:119543c9f674 4942 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 4943 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 490:119543c9f674 4944 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 490:119543c9f674 4945
mbed_official 490:119543c9f674 4946 /* Configure TI1 Filter and Polarity */
mbed_official 490:119543c9f674 4947 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 490:119543c9f674 4948 sSlaveConfig->TriggerPolarity,
mbed_official 490:119543c9f674 4949 sSlaveConfig->TriggerFilter);
mbed_official 490:119543c9f674 4950 }
mbed_official 490:119543c9f674 4951 break;
mbed_official 490:119543c9f674 4952
mbed_official 490:119543c9f674 4953 case TIM_TS_TI2FP2:
mbed_official 490:119543c9f674 4954 {
mbed_official 490:119543c9f674 4955 /* Check the parameters */
mbed_official 490:119543c9f674 4956 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 4957 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 490:119543c9f674 4958 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 490:119543c9f674 4959
mbed_official 490:119543c9f674 4960 /* Configure TI2 Filter and Polarity */
mbed_official 490:119543c9f674 4961 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 490:119543c9f674 4962 sSlaveConfig->TriggerPolarity,
mbed_official 490:119543c9f674 4963 sSlaveConfig->TriggerFilter);
mbed_official 490:119543c9f674 4964 }
mbed_official 490:119543c9f674 4965 break;
mbed_official 490:119543c9f674 4966
mbed_official 490:119543c9f674 4967 case TIM_TS_ITR0:
mbed_official 490:119543c9f674 4968 {
mbed_official 490:119543c9f674 4969 /* Check the parameter */
mbed_official 490:119543c9f674 4970 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 4971 }
mbed_official 490:119543c9f674 4972 break;
mbed_official 490:119543c9f674 4973
mbed_official 490:119543c9f674 4974 case TIM_TS_ITR1:
mbed_official 490:119543c9f674 4975 {
mbed_official 490:119543c9f674 4976 /* Check the parameter */
mbed_official 490:119543c9f674 4977 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 4978 }
mbed_official 490:119543c9f674 4979 break;
mbed_official 490:119543c9f674 4980
mbed_official 490:119543c9f674 4981 case TIM_TS_ITR2:
mbed_official 490:119543c9f674 4982 {
mbed_official 490:119543c9f674 4983 /* Check the parameter */
mbed_official 490:119543c9f674 4984 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 4985 }
mbed_official 490:119543c9f674 4986 break;
mbed_official 490:119543c9f674 4987
mbed_official 490:119543c9f674 4988 case TIM_TS_ITR3:
mbed_official 490:119543c9f674 4989 {
mbed_official 490:119543c9f674 4990 /* Check the parameter */
mbed_official 490:119543c9f674 4991 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 490:119543c9f674 4992 }
mbed_official 490:119543c9f674 4993 break;
mbed_official 490:119543c9f674 4994
mbed_official 490:119543c9f674 4995 default:
mbed_official 490:119543c9f674 4996 break;
mbed_official 490:119543c9f674 4997 }
mbed_official 490:119543c9f674 4998 }
mbed_official 490:119543c9f674 4999
mbed_official 490:119543c9f674 5000 /**
mbed_official 490:119543c9f674 5001 * @}
mbed_official 490:119543c9f674 5002 */
mbed_official 490:119543c9f674 5003
mbed_official 490:119543c9f674 5004 /**
mbed_official 490:119543c9f674 5005 * @}
mbed_official 490:119543c9f674 5006 */
mbed_official 376:cb4d9db17537 5007
mbed_official 376:cb4d9db17537 5008 /**
mbed_official 376:cb4d9db17537 5009 * @}
mbed_official 376:cb4d9db17537 5010 */
mbed_official 376:cb4d9db17537 5011
mbed_official 376:cb4d9db17537 5012 #endif /* HAL_TIM_MODULE_ENABLED */
mbed_official 376:cb4d9db17537 5013 /**
mbed_official 376:cb4d9db17537 5014 * @}
mbed_official 376:cb4d9db17537 5015 */
mbed_official 376:cb4d9db17537 5016
mbed_official 376:cb4d9db17537 5017 /**
mbed_official 376:cb4d9db17537 5018 * @}
mbed_official 376:cb4d9db17537 5019 */
mbed_official 376:cb4d9db17537 5020 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 490:119543c9f674 5021