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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c@636:a11c0372f0ba, 2015-09-30 (annotated)

Committer:: mbed_official
Date:: Wed Sep 30 17:00:09 2015 +0100
Revision:: 636:a11c0372f0ba
Parent:: 631:825f75ca301e

Synchronized with git revision d29c98dae61be0946ddf3a3c641c7726056f9452

Full URL: https://github.com/mbedmicro/mbed/commit/d29c98dae61be0946ddf3a3c641c7726056f9452/

Added support for SAMW25

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_smbus.c
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	631:825f75ca301e	5	* @version V1.3.0
mbed_official	631:825f75ca301e	6	* @date 26-June-2015
mbed_official	340:28d1f895c6fe	7	* @brief SMBUS HAL module driver.
mbed_official	340:28d1f895c6fe	8	* This file provides firmware functions to manage the following
mbed_official	340:28d1f895c6fe	9	* functionalities of the System Management Bus (SMBus) peripheral,
mbed_official	631:825f75ca301e	10	* based on I2C principles of operation :
mbed_official	340:28d1f895c6fe	11	* + Initialization and de-initialization functions
mbed_official	340:28d1f895c6fe	12	* + IO operation functions
mbed_official	340:28d1f895c6fe	13	* + Peripheral State and Errors functions
mbed_official	631:825f75ca301e	14	*
mbed_official	340:28d1f895c6fe	15	@verbatim
mbed_official	340:28d1f895c6fe	16	==============================================================================
mbed_official	340:28d1f895c6fe	17	##### How to use this driver #####
mbed_official	340:28d1f895c6fe	18	==============================================================================
mbed_official	340:28d1f895c6fe	19	[..]
mbed_official	340:28d1f895c6fe	20	The SMBUS HAL driver can be used as follows:
mbed_official	340:28d1f895c6fe	21
mbed_official	340:28d1f895c6fe	22	(#) Declare a SMBUS_HandleTypeDef handle structure, for example:
mbed_official	340:28d1f895c6fe	23	SMBUS_HandleTypeDef hsmbus;
mbed_official	340:28d1f895c6fe	24
mbed_official	631:825f75ca301e	25	(#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
mbed_official	631:825f75ca301e	26	(++) Enable the SMBUSx interface clock with __HAL_RCC_I2Cx_CLK_ENABLE()
mbed_official	631:825f75ca301e	27	(++) SMBUS pins configuration
mbed_official	340:28d1f895c6fe	28	(+++) Enable the clock for the SMBUS GPIOs
mbed_official	340:28d1f895c6fe	29	(+++) Configure SMBUS pins as alternate function open-drain
mbed_official	631:825f75ca301e	30	(++) NVIC configuration if you need to use interrupt process
mbed_official	340:28d1f895c6fe	31	(+++) Configure the SMBUSx interrupt priority
mbed_official	340:28d1f895c6fe	32	(+++) Enable the NVIC SMBUS IRQ Channel
mbed_official	340:28d1f895c6fe	33
mbed_official	631:825f75ca301e	34	(#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing Mode,
mbed_official	340:28d1f895c6fe	35	Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
mbed_official	340:28d1f895c6fe	36	Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
mbed_official	340:28d1f895c6fe	37
mbed_official	340:28d1f895c6fe	38	(#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
mbed_official	631:825f75ca301e	39	(++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official	631:825f75ca301e	40	by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
mbed_official	340:28d1f895c6fe	41
mbed_official	340:28d1f895c6fe	42	(#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
mbed_official	340:28d1f895c6fe	43
mbed_official	340:28d1f895c6fe	44	(#) For SMBUS IO operations, only one mode of operations is available within this driver :
mbed_official	340:28d1f895c6fe	45
mbed_official	340:28d1f895c6fe	46	* Interrupt mode IO operation *
mbed_official	340:28d1f895c6fe	47	===================================
mbed_official	340:28d1f895c6fe	48	[..]
mbed_official	631:825f75ca301e	49	(+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
mbed_official	631:825f75ca301e	50	(++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
mbed_official	631:825f75ca301e	51	add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
mbed_official	631:825f75ca301e	52	(+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
mbed_official	631:825f75ca301e	53	(++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
mbed_official	631:825f75ca301e	54	add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
mbed_official	631:825f75ca301e	55	(+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
mbed_official	340:28d1f895c6fe	56	(++) The associated previous transfer callback is called at the end of abort process
mbed_official	631:825f75ca301e	57	(++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
mbed_official	631:825f75ca301e	58	(++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
mbed_official	340:28d1f895c6fe	59	(+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
mbed_official	631:825f75ca301e	60	using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
mbed_official	631:825f75ca301e	61	(++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
mbed_official	340:28d1f895c6fe	62	add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
mbed_official	631:825f75ca301e	63	(++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
mbed_official	631:825f75ca301e	64	add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
mbed_official	631:825f75ca301e	65	(+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
mbed_official	631:825f75ca301e	66	(++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
mbed_official	631:825f75ca301e	67	add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
mbed_official	631:825f75ca301e	68	(+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
mbed_official	631:825f75ca301e	69	(++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
mbed_official	631:825f75ca301e	70	add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
mbed_official	340:28d1f895c6fe	71	(+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
mbed_official	340:28d1f895c6fe	72	(++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
mbed_official	631:825f75ca301e	73	add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
mbed_official	340:28d1f895c6fe	74	to check the Alert Error Code using function HAL_SMBUS_GetError()
mbed_official	340:28d1f895c6fe	75	(+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
mbed_official	340:28d1f895c6fe	76	(+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
mbed_official	631:825f75ca301e	77	add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
mbed_official	340:28d1f895c6fe	78	to check the Error Code using function HAL_SMBUS_GetError()
mbed_official	340:28d1f895c6fe	79
mbed_official	340:28d1f895c6fe	80	* SMBUS HAL driver macros list *
mbed_official	340:28d1f895c6fe	81	==================================
mbed_official	340:28d1f895c6fe	82	[..]
mbed_official	340:28d1f895c6fe	83	Below the list of most used macros in SMBUS HAL driver.
mbed_official	340:28d1f895c6fe	84
mbed_official	340:28d1f895c6fe	85	(+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
mbed_official	340:28d1f895c6fe	86	(+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
mbed_official	340:28d1f895c6fe	87	(+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not
mbed_official	340:28d1f895c6fe	88	(+) __HAL_SMBUS_CLEAR_FLAG : Clears the specified SMBUS pending flag
mbed_official	340:28d1f895c6fe	89	(+) __HAL_SMBUS_ENABLE_IT: Enables the specified SMBUS interrupt
mbed_official	340:28d1f895c6fe	90	(+) __HAL_SMBUS_DISABLE_IT: Disables the specified SMBUS interrupt
mbed_official	340:28d1f895c6fe	91
mbed_official	340:28d1f895c6fe	92	[..]
mbed_official	340:28d1f895c6fe	93	(@) You can refer to the SMBUS HAL driver header file for more useful macros
mbed_official	340:28d1f895c6fe	94
mbed_official	340:28d1f895c6fe	95
mbed_official	340:28d1f895c6fe	96	@endverbatim
mbed_official	340:28d1f895c6fe	97	******************************************************************************
mbed_official	340:28d1f895c6fe	98	* @attention
mbed_official	340:28d1f895c6fe	99	*
mbed_official	631:825f75ca301e	100	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	101	*
mbed_official	340:28d1f895c6fe	102	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	103	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	104	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	105	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	106	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	107	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	108	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	109	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	110	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	111	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	112	*
mbed_official	340:28d1f895c6fe	113	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	114	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	115	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	116	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	117	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	118	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	119	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	120	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	121	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	122	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	123	*
mbed_official	340:28d1f895c6fe	124	******************************************************************************
mbed_official	340:28d1f895c6fe	125	*/
mbed_official	340:28d1f895c6fe	126
mbed_official	340:28d1f895c6fe	127	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	128	#include "stm32f0xx_hal.h"
mbed_official	340:28d1f895c6fe	129
mbed_official	340:28d1f895c6fe	130	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	131	* @{
mbed_official	340:28d1f895c6fe	132	*/
mbed_official	340:28d1f895c6fe	133
mbed_official	631:825f75ca301e	134	/** @defgroup SMBUS SMBUS
mbed_official	340:28d1f895c6fe	135	* @brief SMBUS HAL module driver
mbed_official	340:28d1f895c6fe	136	* @{
mbed_official	340:28d1f895c6fe	137	*/
mbed_official	340:28d1f895c6fe	138
mbed_official	340:28d1f895c6fe	139	#ifdef HAL_SMBUS_MODULE_ENABLED
mbed_official	340:28d1f895c6fe	140
mbed_official	340:28d1f895c6fe	141	/* Private typedef -----------------------------------------------------------*/
mbed_official	631:825f75ca301e	142	/* Private constants ---------------------------------------------------------*/
mbed_official	631:825f75ca301e	143	/** @defgroup SMBUS_Private_Define SMBUS Private Constants
mbed_official	340:28d1f895c6fe	144	* @{
mbed_official	340:28d1f895c6fe	145	*/
mbed_official	340:28d1f895c6fe	146	#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /<! SMBUS TIMING clear register Mask /
mbed_official	340:28d1f895c6fe	147	#define HAL_TIMEOUT_ADDR ((uint32_t)10000) /* 10 s */
mbed_official	340:28d1f895c6fe	148	#define HAL_TIMEOUT_BUSY ((uint32_t)25) /* 25 ms */
mbed_official	340:28d1f895c6fe	149	#define HAL_TIMEOUT_DIR ((uint32_t)25) /* 25 ms */
mbed_official	340:28d1f895c6fe	150	#define HAL_TIMEOUT_RXNE ((uint32_t)25) /* 25 ms */
mbed_official	340:28d1f895c6fe	151	#define HAL_TIMEOUT_STOPF ((uint32_t)25) /* 25 ms */
mbed_official	340:28d1f895c6fe	152	#define HAL_TIMEOUT_TC ((uint32_t)25) /* 25 ms */
mbed_official	340:28d1f895c6fe	153	#define HAL_TIMEOUT_TCR ((uint32_t)25) /* 25 ms */
mbed_official	340:28d1f895c6fe	154	#define HAL_TIMEOUT_TXIS ((uint32_t)25) /* 25 ms */
mbed_official	340:28d1f895c6fe	155	#define MAX_NBYTE_SIZE 255
mbed_official	340:28d1f895c6fe	156	/**
mbed_official	340:28d1f895c6fe	157	* @}
mbed_official	340:28d1f895c6fe	158	*/
mbed_official	340:28d1f895c6fe	159
mbed_official	340:28d1f895c6fe	160	/* Private macro -------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	161	/* Private variables ---------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	162	/* Private function prototypes -----------------------------------------------*/
mbed_official	631:825f75ca301e	163	/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
mbed_official	340:28d1f895c6fe	164	* @{
mbed_official	340:28d1f895c6fe	165	*/
mbed_official	340:28d1f895c6fe	166	static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
mbed_official	340:28d1f895c6fe	167
mbed_official	340:28d1f895c6fe	168	static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
mbed_official	340:28d1f895c6fe	169	static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
mbed_official	340:28d1f895c6fe	170	static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
mbed_official	340:28d1f895c6fe	171	static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
mbed_official	340:28d1f895c6fe	172
mbed_official	340:28d1f895c6fe	173	static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
mbed_official	340:28d1f895c6fe	174	/**
mbed_official	340:28d1f895c6fe	175	* @}
mbed_official	340:28d1f895c6fe	176	*/
mbed_official	340:28d1f895c6fe	177
mbed_official	631:825f75ca301e	178	/* Exported functions --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	179
mbed_official	340:28d1f895c6fe	180	/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions
mbed_official	340:28d1f895c6fe	181	* @{
mbed_official	340:28d1f895c6fe	182	*/
mbed_official	340:28d1f895c6fe	183
mbed_official	340:28d1f895c6fe	184	/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official	340:28d1f895c6fe	185	* @brief Initialization and Configuration functions
mbed_official	340:28d1f895c6fe	186	*
mbed_official	340:28d1f895c6fe	187	@verbatim
mbed_official	340:28d1f895c6fe	188	===============================================================================
mbed_official	340:28d1f895c6fe	189	##### Initialization and de-initialization functions #####
mbed_official	340:28d1f895c6fe	190	===============================================================================
mbed_official	340:28d1f895c6fe	191	[..] This subsection provides a set of functions allowing to initialize and
mbed_official	631:825f75ca301e	192	de-initialize the SMBUSx peripheral:
mbed_official	340:28d1f895c6fe	193
mbed_official	340:28d1f895c6fe	194	(+) User must Implement HAL_SMBUS_MspInit() function in which he configures
mbed_official	340:28d1f895c6fe	195	all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
mbed_official	340:28d1f895c6fe	196
mbed_official	340:28d1f895c6fe	197	(+) Call the function HAL_SMBUS_Init() to configure the selected device with
mbed_official	340:28d1f895c6fe	198	the selected configuration:
mbed_official	340:28d1f895c6fe	199	(++) Clock Timing
mbed_official	340:28d1f895c6fe	200	(++) Bus Timeout
mbed_official	340:28d1f895c6fe	201	(++) Analog Filer mode
mbed_official	340:28d1f895c6fe	202	(++) Own Address 1
mbed_official	340:28d1f895c6fe	203	(++) Addressing mode (Master, Slave)
mbed_official	340:28d1f895c6fe	204	(++) Dual Addressing mode
mbed_official	340:28d1f895c6fe	205	(++) Own Address 2
mbed_official	340:28d1f895c6fe	206	(++) Own Address 2 Mask
mbed_official	340:28d1f895c6fe	207	(++) General call mode
mbed_official	340:28d1f895c6fe	208	(++) Nostretch mode
mbed_official	340:28d1f895c6fe	209	(++) Packet Error Check mode
mbed_official	340:28d1f895c6fe	210	(++) Peripheral mode
mbed_official	340:28d1f895c6fe	211
mbed_official	340:28d1f895c6fe	212
mbed_official	340:28d1f895c6fe	213	(+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
mbed_official	631:825f75ca301e	214	of the selected SMBUSx peripheral.
mbed_official	340:28d1f895c6fe	215
mbed_official	340:28d1f895c6fe	216	@endverbatim
mbed_official	340:28d1f895c6fe	217	* @{
mbed_official	340:28d1f895c6fe	218	*/
mbed_official	340:28d1f895c6fe	219
mbed_official	340:28d1f895c6fe	220	/**
mbed_official	631:825f75ca301e	221	* @brief Initialize the SMBUS according to the specified parameters
mbed_official	631:825f75ca301e	222	* in the SMBUS_InitTypeDef and initialize the associated handle.
mbed_official	340:28d1f895c6fe	223	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	224	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	225	* @retval HAL status
mbed_official	340:28d1f895c6fe	226	*/
mbed_official	340:28d1f895c6fe	227	HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	228	{
mbed_official	340:28d1f895c6fe	229	/* Check the SMBUS handle allocation */
mbed_official	442:d2c15dda23c1	230	if(hsmbus == NULL)
mbed_official	340:28d1f895c6fe	231	{
mbed_official	340:28d1f895c6fe	232	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	233	}
mbed_official	340:28d1f895c6fe	234
mbed_official	340:28d1f895c6fe	235	/* Check the parameters */
mbed_official	340:28d1f895c6fe	236	assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
mbed_official	340:28d1f895c6fe	237	assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
mbed_official	340:28d1f895c6fe	238	assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1));
mbed_official	340:28d1f895c6fe	239	assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode));
mbed_official	340:28d1f895c6fe	240	assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode));
mbed_official	340:28d1f895c6fe	241	assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2));
mbed_official	340:28d1f895c6fe	242	assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks));
mbed_official	340:28d1f895c6fe	243	assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode));
mbed_official	340:28d1f895c6fe	244	assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode));
mbed_official	340:28d1f895c6fe	245	assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
mbed_official	340:28d1f895c6fe	246	assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
mbed_official	340:28d1f895c6fe	247
mbed_official	340:28d1f895c6fe	248	if(hsmbus->State == HAL_SMBUS_STATE_RESET)
mbed_official	340:28d1f895c6fe	249	{
mbed_official	631:825f75ca301e	250	/* Allocate lock resource and initialize it */
mbed_official	631:825f75ca301e	251	hsmbus->Lock = HAL_UNLOCKED;
mbed_official	631:825f75ca301e	252
mbed_official	340:28d1f895c6fe	253	/* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official	340:28d1f895c6fe	254	HAL_SMBUS_MspInit(hsmbus);
mbed_official	340:28d1f895c6fe	255	}
mbed_official	340:28d1f895c6fe	256
mbed_official	340:28d1f895c6fe	257	hsmbus->State = HAL_SMBUS_STATE_BUSY;
mbed_official	340:28d1f895c6fe	258
mbed_official	340:28d1f895c6fe	259	/* Disable the selected SMBUS peripheral */
mbed_official	340:28d1f895c6fe	260	__HAL_SMBUS_DISABLE(hsmbus);
mbed_official	340:28d1f895c6fe	261
mbed_official	340:28d1f895c6fe	262	/---------------------------- SMBUSx TIMINGR Configuration ------------------------/
mbed_official	340:28d1f895c6fe	263	/* Configure SMBUSx: Frequency range */
mbed_official	340:28d1f895c6fe	264	hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
mbed_official	340:28d1f895c6fe	265
mbed_official	340:28d1f895c6fe	266	/---------------------------- SMBUSx TIMEOUTR Configuration ------------------------/
mbed_official	340:28d1f895c6fe	267	/* Configure SMBUSx: Bus Timeout */
mbed_official	340:28d1f895c6fe	268	hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
mbed_official	340:28d1f895c6fe	269	hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
mbed_official	340:28d1f895c6fe	270	hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout;
mbed_official	340:28d1f895c6fe	271
mbed_official	340:28d1f895c6fe	272	/---------------------------- SMBUSx OAR1 Configuration -----------------------/
mbed_official	340:28d1f895c6fe	273	/* Configure SMBUSx: Own Address1 and ack own address1 mode */
mbed_official	340:28d1f895c6fe	274	hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
mbed_official	340:28d1f895c6fe	275
mbed_official	340:28d1f895c6fe	276	if(hsmbus->Init.OwnAddress1 != 0)
mbed_official	340:28d1f895c6fe	277	{
mbed_official	340:28d1f895c6fe	278	if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
mbed_official	340:28d1f895c6fe	279	{
mbed_official	340:28d1f895c6fe	280	hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN \| hsmbus->Init.OwnAddress1);
mbed_official	340:28d1f895c6fe	281	}
mbed_official	340:28d1f895c6fe	282	else /* SMBUS_ADDRESSINGMODE_10BIT */
mbed_official	340:28d1f895c6fe	283	{
mbed_official	340:28d1f895c6fe	284	hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN \| I2C_OAR1_OA1MODE \| hsmbus->Init.OwnAddress1);
mbed_official	340:28d1f895c6fe	285	}
mbed_official	340:28d1f895c6fe	286	}
mbed_official	340:28d1f895c6fe	287
mbed_official	340:28d1f895c6fe	288	/---------------------------- SMBUSx CR2 Configuration ------------------------/
mbed_official	340:28d1f895c6fe	289	/* Configure SMBUSx: Addressing Master mode */
mbed_official	340:28d1f895c6fe	290	if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
mbed_official	340:28d1f895c6fe	291	{
mbed_official	340:28d1f895c6fe	292	hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
mbed_official	340:28d1f895c6fe	293	}
mbed_official	340:28d1f895c6fe	294	/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
mbed_official	340:28d1f895c6fe	295	/* AUTOEND and NACK bit will be manage during Transfer process */
mbed_official	340:28d1f895c6fe	296	hsmbus->Instance->CR2 \|= (I2C_CR2_AUTOEND \| I2C_CR2_NACK);
mbed_official	340:28d1f895c6fe	297
mbed_official	340:28d1f895c6fe	298	/---------------------------- SMBUSx OAR2 Configuration -----------------------/
mbed_official	340:28d1f895c6fe	299	/* Configure SMBUSx: Dual mode and Own Address2 */
mbed_official	340:28d1f895c6fe	300	hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode \| hsmbus->Init.OwnAddress2 \| (hsmbus->Init.OwnAddress2Masks << 8));
mbed_official	340:28d1f895c6fe	301
mbed_official	340:28d1f895c6fe	302	/---------------------------- SMBUSx CR1 Configuration ------------------------/
mbed_official	340:28d1f895c6fe	303	/* Configure SMBUSx: Generalcall and NoStretch mode */
mbed_official	340:28d1f895c6fe	304	hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode \| hsmbus->Init.NoStretchMode \| hsmbus->Init.PacketErrorCheckMode \| hsmbus->Init.PeripheralMode \| hsmbus->Init.AnalogFilter);
mbed_official	340:28d1f895c6fe	305
mbed_official	340:28d1f895c6fe	306	/* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
mbed_official	631:825f75ca301e	307	if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
mbed_official	340:28d1f895c6fe	308	&& ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) \|\| (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
mbed_official	340:28d1f895c6fe	309	{
mbed_official	340:28d1f895c6fe	310	hsmbus->Instance->CR1 \|= I2C_CR1_SBC;
mbed_official	340:28d1f895c6fe	311	}
mbed_official	340:28d1f895c6fe	312
mbed_official	340:28d1f895c6fe	313	/* Enable the selected SMBUS peripheral */
mbed_official	340:28d1f895c6fe	314	__HAL_SMBUS_ENABLE(hsmbus);
mbed_official	340:28d1f895c6fe	315
mbed_official	340:28d1f895c6fe	316	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
mbed_official	340:28d1f895c6fe	317	hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	318	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	319
mbed_official	340:28d1f895c6fe	320	return HAL_OK;
mbed_official	340:28d1f895c6fe	321	}
mbed_official	340:28d1f895c6fe	322
mbed_official	340:28d1f895c6fe	323	/**
mbed_official	631:825f75ca301e	324	* @brief DeInitialize the SMBUS peripheral.
mbed_official	340:28d1f895c6fe	325	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	326	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	327	* @retval HAL status
mbed_official	340:28d1f895c6fe	328	*/
mbed_official	340:28d1f895c6fe	329	HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	330	{
mbed_official	340:28d1f895c6fe	331	/* Check the SMBUS handle allocation */
mbed_official	442:d2c15dda23c1	332	if(hsmbus == NULL)
mbed_official	340:28d1f895c6fe	333	{
mbed_official	340:28d1f895c6fe	334	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	335	}
mbed_official	340:28d1f895c6fe	336
mbed_official	340:28d1f895c6fe	337	/* Check the parameters */
mbed_official	340:28d1f895c6fe	338	assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
mbed_official	340:28d1f895c6fe	339
mbed_official	340:28d1f895c6fe	340	hsmbus->State = HAL_SMBUS_STATE_BUSY;
mbed_official	340:28d1f895c6fe	341
mbed_official	340:28d1f895c6fe	342	/* Disable the SMBUS Peripheral Clock */
mbed_official	340:28d1f895c6fe	343	__HAL_SMBUS_DISABLE(hsmbus);
mbed_official	340:28d1f895c6fe	344
mbed_official	340:28d1f895c6fe	345	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official	340:28d1f895c6fe	346	HAL_SMBUS_MspDeInit(hsmbus);
mbed_official	340:28d1f895c6fe	347
mbed_official	340:28d1f895c6fe	348	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
mbed_official	340:28d1f895c6fe	349	hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
mbed_official	340:28d1f895c6fe	350	hsmbus->State = HAL_SMBUS_STATE_RESET;
mbed_official	340:28d1f895c6fe	351
mbed_official	340:28d1f895c6fe	352	/* Release Lock */
mbed_official	340:28d1f895c6fe	353	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	354
mbed_official	340:28d1f895c6fe	355	return HAL_OK;
mbed_official	340:28d1f895c6fe	356	}
mbed_official	340:28d1f895c6fe	357
mbed_official	340:28d1f895c6fe	358	/**
mbed_official	631:825f75ca301e	359	* @brief Initialize the SMBUS MSP.
mbed_official	340:28d1f895c6fe	360	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	361	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	362	* @retval None
mbed_official	340:28d1f895c6fe	363	*/
mbed_official	340:28d1f895c6fe	364	__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	365	{
mbed_official	631:825f75ca301e	366	/* NOTE : This function should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	367	the HAL_SMBUS_MspInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	368	*/
mbed_official	340:28d1f895c6fe	369	}
mbed_official	340:28d1f895c6fe	370
mbed_official	340:28d1f895c6fe	371	/**
mbed_official	631:825f75ca301e	372	* @brief DeInitialize the SMBUS MSP.
mbed_official	340:28d1f895c6fe	373	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	374	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	375	* @retval None
mbed_official	340:28d1f895c6fe	376	*/
mbed_official	340:28d1f895c6fe	377	__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	378	{
mbed_official	631:825f75ca301e	379	/* NOTE : This function should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	380	the HAL_SMBUS_MspDeInit could be implemented in the user file
mbed_official	340:28d1f895c6fe	381	*/
mbed_official	340:28d1f895c6fe	382	}
mbed_official	340:28d1f895c6fe	383
mbed_official	340:28d1f895c6fe	384	/**
mbed_official	340:28d1f895c6fe	385	* @}
mbed_official	340:28d1f895c6fe	386	*/
mbed_official	340:28d1f895c6fe	387
mbed_official	340:28d1f895c6fe	388	/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
mbed_official	340:28d1f895c6fe	389	* @brief Data transfers functions
mbed_official	340:28d1f895c6fe	390	*
mbed_official	340:28d1f895c6fe	391	@verbatim
mbed_official	340:28d1f895c6fe	392	===============================================================================
mbed_official	340:28d1f895c6fe	393	##### IO operation functions #####
mbed_official	340:28d1f895c6fe	394	===============================================================================
mbed_official	340:28d1f895c6fe	395	[..]
mbed_official	340:28d1f895c6fe	396	This subsection provides a set of functions allowing to manage the SMBUS data
mbed_official	340:28d1f895c6fe	397	transfers.
mbed_official	340:28d1f895c6fe	398
mbed_official	340:28d1f895c6fe	399	(#) Blocking mode function to check if device is ready for usage is :
mbed_official	340:28d1f895c6fe	400	(++) HAL_SMBUS_IsDeviceReady()
mbed_official	340:28d1f895c6fe	401
mbed_official	340:28d1f895c6fe	402	(#) There is only one mode of transfer:
mbed_official	340:28d1f895c6fe	403	(++) No-Blocking mode : The communication is performed using Interrupts.
mbed_official	340:28d1f895c6fe	404	These functions return the status of the transfer startup.
mbed_official	340:28d1f895c6fe	405	The end of the data processing will be indicated through the
mbed_official	340:28d1f895c6fe	406	dedicated SMBUS IRQ when using Interrupt mode.
mbed_official	340:28d1f895c6fe	407
mbed_official	340:28d1f895c6fe	408	(#) No-Blocking mode functions with Interrupt are :
mbed_official	340:28d1f895c6fe	409	(++) HAL_SMBUS_Master_Transmit_IT()
mbed_official	340:28d1f895c6fe	410	(++) HAL_SMBUS_Master_Receive_IT()
mbed_official	340:28d1f895c6fe	411	(++) HAL_SMBUS_Slave_Transmit_IT()
mbed_official	340:28d1f895c6fe	412	(++) HAL_SMBUS_Slave_Receive_IT()
mbed_official	631:825f75ca301e	413	(++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
mbed_official	340:28d1f895c6fe	414	(++) HAL_SMBUS_DisableListen_IT()
mbed_official	340:28d1f895c6fe	415	(++) HAL_SMBUS_EnableAlert_IT()
mbed_official	340:28d1f895c6fe	416	(++) HAL_SMBUS_DisableAlert_IT()
mbed_official	340:28d1f895c6fe	417
mbed_official	340:28d1f895c6fe	418	(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
mbed_official	340:28d1f895c6fe	419	(++) HAL_SMBUS_MasterTxCpltCallback()
mbed_official	340:28d1f895c6fe	420	(++) HAL_SMBUS_MasterRxCpltCallback()
mbed_official	340:28d1f895c6fe	421	(++) HAL_SMBUS_SlaveTxCpltCallback()
mbed_official	340:28d1f895c6fe	422	(++) HAL_SMBUS_SlaveRxCpltCallback()
mbed_official	631:825f75ca301e	423	(++) HAL_SMBUS_AddrCallback()
mbed_official	631:825f75ca301e	424	(++) HAL_SMBUS_ListenCpltCallback()
mbed_official	340:28d1f895c6fe	425	(++) HAL_SMBUS_ErrorCallback()
mbed_official	340:28d1f895c6fe	426
mbed_official	340:28d1f895c6fe	427	@endverbatim
mbed_official	340:28d1f895c6fe	428	* @{
mbed_official	340:28d1f895c6fe	429	*/
mbed_official	340:28d1f895c6fe	430
mbed_official	340:28d1f895c6fe	431	/**
mbed_official	631:825f75ca301e	432	* @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
mbed_official	340:28d1f895c6fe	433	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	434	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	435	* @param DevAddress: Target device address
mbed_official	340:28d1f895c6fe	436	* @param pData: Pointer to data buffer
mbed_official	340:28d1f895c6fe	437	* @param Size: Amount of data to be sent
mbed_official	340:28d1f895c6fe	438	* @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
mbed_official	340:28d1f895c6fe	439	* @retval HAL status
mbed_official	340:28d1f895c6fe	440	*/
mbed_official	340:28d1f895c6fe	441	HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef hsmbus, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
mbed_official	340:28d1f895c6fe	442	{
mbed_official	340:28d1f895c6fe	443	/* Check the parameters */
mbed_official	340:28d1f895c6fe	444	assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
mbed_official	340:28d1f895c6fe	445
mbed_official	340:28d1f895c6fe	446	if(hsmbus->State == HAL_SMBUS_STATE_READY)
mbed_official	340:28d1f895c6fe	447	{
mbed_official	340:28d1f895c6fe	448	/* Process Locked */
mbed_official	340:28d1f895c6fe	449	__HAL_LOCK(hsmbus);
mbed_official	340:28d1f895c6fe	450
mbed_official	340:28d1f895c6fe	451	hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
mbed_official	340:28d1f895c6fe	452	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
mbed_official	340:28d1f895c6fe	453	/* Prepare transfer parameters */
mbed_official	340:28d1f895c6fe	454	hsmbus->pBuffPtr = pData;
mbed_official	340:28d1f895c6fe	455	hsmbus->XferCount = Size;
mbed_official	340:28d1f895c6fe	456	hsmbus->XferOptions = XferOptions;
mbed_official	340:28d1f895c6fe	457
mbed_official	340:28d1f895c6fe	458	/* In case of Quick command, remove autoend mode */
mbed_official	340:28d1f895c6fe	459	/* Manage the stop generation by software */
mbed_official	442:d2c15dda23c1	460	if(hsmbus->pBuffPtr == NULL)
mbed_official	340:28d1f895c6fe	461	{
mbed_official	340:28d1f895c6fe	462	hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
mbed_official	340:28d1f895c6fe	463	}
mbed_official	340:28d1f895c6fe	464
mbed_official	340:28d1f895c6fe	465	if(Size > MAX_NBYTE_SIZE)
mbed_official	340:28d1f895c6fe	466	{
mbed_official	340:28d1f895c6fe	467	hsmbus->XferSize = MAX_NBYTE_SIZE;
mbed_official	340:28d1f895c6fe	468	}
mbed_official	340:28d1f895c6fe	469	else
mbed_official	340:28d1f895c6fe	470	{
mbed_official	340:28d1f895c6fe	471	hsmbus->XferSize = Size;
mbed_official	340:28d1f895c6fe	472	}
mbed_official	340:28d1f895c6fe	473
mbed_official	340:28d1f895c6fe	474	/* Send Slave Address */
mbed_official	340:28d1f895c6fe	475	/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
mbed_official	340:28d1f895c6fe	476	if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
mbed_official	340:28d1f895c6fe	477	{
mbed_official	340:28d1f895c6fe	478	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE \| (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
mbed_official	340:28d1f895c6fe	479	}
mbed_official	340:28d1f895c6fe	480	else
mbed_official	340:28d1f895c6fe	481	{
mbed_official	340:28d1f895c6fe	482	/* If transfer direction not change, do not generate Restart Condition */
mbed_official	340:28d1f895c6fe	483	/* Mean Previous state is same as current state */
mbed_official	340:28d1f895c6fe	484	if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
mbed_official	340:28d1f895c6fe	485	{
mbed_official	340:28d1f895c6fe	486	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	487	}
mbed_official	340:28d1f895c6fe	488	/* Else transfer direction change, so generate Restart with new transfer direction */
mbed_official	340:28d1f895c6fe	489	else
mbed_official	340:28d1f895c6fe	490	{
mbed_official	340:28d1f895c6fe	491	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
mbed_official	340:28d1f895c6fe	492	}
mbed_official	340:28d1f895c6fe	493
mbed_official	340:28d1f895c6fe	494	/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
mbed_official	340:28d1f895c6fe	495	/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
mbed_official	631:825f75ca301e	496	if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
mbed_official	340:28d1f895c6fe	497	{
mbed_official	340:28d1f895c6fe	498	hsmbus->XferSize--;
mbed_official	340:28d1f895c6fe	499	hsmbus->XferCount--;
mbed_official	340:28d1f895c6fe	500	}
mbed_official	340:28d1f895c6fe	501	}
mbed_official	340:28d1f895c6fe	502
mbed_official	340:28d1f895c6fe	503	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	504	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	505
mbed_official	340:28d1f895c6fe	506	/* Note : The SMBUS interrupts must be enabled after unlocking current process
mbed_official	340:28d1f895c6fe	507	to avoid the risk of SMBUS interrupt handle execution before current
mbed_official	340:28d1f895c6fe	508	process unlock */
mbed_official	340:28d1f895c6fe	509	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
mbed_official	340:28d1f895c6fe	510
mbed_official	340:28d1f895c6fe	511	return HAL_OK;
mbed_official	340:28d1f895c6fe	512	}
mbed_official	340:28d1f895c6fe	513	else
mbed_official	340:28d1f895c6fe	514	{
mbed_official	340:28d1f895c6fe	515	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	516	}
mbed_official	340:28d1f895c6fe	517	}
mbed_official	340:28d1f895c6fe	518
mbed_official	340:28d1f895c6fe	519	/**
mbed_official	631:825f75ca301e	520	* @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
mbed_official	340:28d1f895c6fe	521	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	522	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	523	* @param DevAddress: Target device address
mbed_official	340:28d1f895c6fe	524	* @param pData: Pointer to data buffer
mbed_official	340:28d1f895c6fe	525	* @param Size: Amount of data to be sent
mbed_official	340:28d1f895c6fe	526	* @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
mbed_official	340:28d1f895c6fe	527	* @retval HAL status
mbed_official	340:28d1f895c6fe	528	*/
mbed_official	340:28d1f895c6fe	529	HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef hsmbus, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
mbed_official	340:28d1f895c6fe	530	{
mbed_official	340:28d1f895c6fe	531	/* Check the parameters */
mbed_official	340:28d1f895c6fe	532	assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
mbed_official	340:28d1f895c6fe	533
mbed_official	340:28d1f895c6fe	534	if(hsmbus->State == HAL_SMBUS_STATE_READY)
mbed_official	340:28d1f895c6fe	535	{
mbed_official	340:28d1f895c6fe	536	/* Process Locked */
mbed_official	340:28d1f895c6fe	537	__HAL_LOCK(hsmbus);
mbed_official	340:28d1f895c6fe	538
mbed_official	340:28d1f895c6fe	539	hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
mbed_official	340:28d1f895c6fe	540	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
mbed_official	340:28d1f895c6fe	541
mbed_official	340:28d1f895c6fe	542	/* Prepare transfer parameters */
mbed_official	340:28d1f895c6fe	543	hsmbus->pBuffPtr = pData;
mbed_official	340:28d1f895c6fe	544	hsmbus->XferCount = Size;
mbed_official	340:28d1f895c6fe	545	hsmbus->XferOptions = XferOptions;
mbed_official	340:28d1f895c6fe	546
mbed_official	340:28d1f895c6fe	547	/* In case of Quick command, remove autoend mode */
mbed_official	340:28d1f895c6fe	548	/* Manage the stop generation by software */
mbed_official	442:d2c15dda23c1	549	if(hsmbus->pBuffPtr == NULL)
mbed_official	340:28d1f895c6fe	550	{
mbed_official	340:28d1f895c6fe	551	hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
mbed_official	340:28d1f895c6fe	552	}
mbed_official	340:28d1f895c6fe	553
mbed_official	340:28d1f895c6fe	554	if(Size > MAX_NBYTE_SIZE)
mbed_official	340:28d1f895c6fe	555	{
mbed_official	340:28d1f895c6fe	556	hsmbus->XferSize = MAX_NBYTE_SIZE;
mbed_official	340:28d1f895c6fe	557	}
mbed_official	340:28d1f895c6fe	558	else
mbed_official	340:28d1f895c6fe	559	{
mbed_official	340:28d1f895c6fe	560	hsmbus->XferSize = Size;
mbed_official	340:28d1f895c6fe	561	}
mbed_official	340:28d1f895c6fe	562
mbed_official	340:28d1f895c6fe	563	/* Send Slave Address */
mbed_official	340:28d1f895c6fe	564	/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
mbed_official	340:28d1f895c6fe	565	if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
mbed_official	340:28d1f895c6fe	566	{
mbed_official	340:28d1f895c6fe	567	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE \| (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
mbed_official	340:28d1f895c6fe	568	}
mbed_official	340:28d1f895c6fe	569	else
mbed_official	340:28d1f895c6fe	570	{
mbed_official	340:28d1f895c6fe	571	/* If transfer direction not change, do not generate Restart Condition */
mbed_official	340:28d1f895c6fe	572	/* Mean Previous state is same as current state */
mbed_official	340:28d1f895c6fe	573	if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
mbed_official	340:28d1f895c6fe	574	{
mbed_official	340:28d1f895c6fe	575	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	576	}
mbed_official	340:28d1f895c6fe	577	/* Else transfer direction change, so generate Restart with new transfer direction */
mbed_official	340:28d1f895c6fe	578	else
mbed_official	340:28d1f895c6fe	579	{
mbed_official	340:28d1f895c6fe	580	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
mbed_official	340:28d1f895c6fe	581	}
mbed_official	340:28d1f895c6fe	582	}
mbed_official	340:28d1f895c6fe	583
mbed_official	340:28d1f895c6fe	584	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	585	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	586
mbed_official	340:28d1f895c6fe	587	/* Note : The SMBUS interrupts must be enabled after unlocking current process
mbed_official	340:28d1f895c6fe	588	to avoid the risk of SMBUS interrupt handle execution before current
mbed_official	340:28d1f895c6fe	589	process unlock */
mbed_official	340:28d1f895c6fe	590	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
mbed_official	340:28d1f895c6fe	591
mbed_official	340:28d1f895c6fe	592	return HAL_OK;
mbed_official	340:28d1f895c6fe	593	}
mbed_official	340:28d1f895c6fe	594	else
mbed_official	340:28d1f895c6fe	595	{
mbed_official	340:28d1f895c6fe	596	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	597	}
mbed_official	340:28d1f895c6fe	598	}
mbed_official	340:28d1f895c6fe	599
mbed_official	340:28d1f895c6fe	600	/**
mbed_official	631:825f75ca301e	601	* @brief Abort a master/host SMBUS process communication with Interrupt.
mbed_official	631:825f75ca301e	602	* @note This abort can be called only if state is ready
mbed_official	340:28d1f895c6fe	603	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	604	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	605	* @param DevAddress: Target device address
mbed_official	340:28d1f895c6fe	606	* @retval HAL status
mbed_official	340:28d1f895c6fe	607	*/
mbed_official	340:28d1f895c6fe	608	HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
mbed_official	340:28d1f895c6fe	609	{
mbed_official	340:28d1f895c6fe	610	if(hsmbus->State == HAL_SMBUS_STATE_READY)
mbed_official	340:28d1f895c6fe	611	{
mbed_official	340:28d1f895c6fe	612	/* Process Locked */
mbed_official	340:28d1f895c6fe	613	__HAL_LOCK(hsmbus);
mbed_official	340:28d1f895c6fe	614
mbed_official	340:28d1f895c6fe	615	/* Keep the same state as previous */
mbed_official	340:28d1f895c6fe	616	/* to perform as well the call of the corresponding end of transfer callback */
mbed_official	340:28d1f895c6fe	617	if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
mbed_official	340:28d1f895c6fe	618	{
mbed_official	340:28d1f895c6fe	619	hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
mbed_official	340:28d1f895c6fe	620	}
mbed_official	340:28d1f895c6fe	621	else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
mbed_official	340:28d1f895c6fe	622	{
mbed_official	340:28d1f895c6fe	623	hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
mbed_official	340:28d1f895c6fe	624	}
mbed_official	340:28d1f895c6fe	625	else
mbed_official	340:28d1f895c6fe	626	{
mbed_official	340:28d1f895c6fe	627	/* Wrong usage of abort function */
mbed_official	340:28d1f895c6fe	628	/* This function should be used only in case of abort monitored by master device */
mbed_official	340:28d1f895c6fe	629	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	630	}
mbed_official	340:28d1f895c6fe	631	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
mbed_official	340:28d1f895c6fe	632
mbed_official	340:28d1f895c6fe	633	/* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
mbed_official	340:28d1f895c6fe	634	/* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
mbed_official	340:28d1f895c6fe	635	SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	636
mbed_official	340:28d1f895c6fe	637	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	638	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	639
mbed_official	340:28d1f895c6fe	640	/* Note : The SMBUS interrupts must be enabled after unlocking current process
mbed_official	340:28d1f895c6fe	641	to avoid the risk of SMBUS interrupt handle execution before current
mbed_official	340:28d1f895c6fe	642	process unlock */
mbed_official	340:28d1f895c6fe	643	if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
mbed_official	340:28d1f895c6fe	644	{
mbed_official	340:28d1f895c6fe	645	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
mbed_official	340:28d1f895c6fe	646	}
mbed_official	340:28d1f895c6fe	647	else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
mbed_official	340:28d1f895c6fe	648	{
mbed_official	340:28d1f895c6fe	649	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
mbed_official	340:28d1f895c6fe	650	}
mbed_official	340:28d1f895c6fe	651
mbed_official	340:28d1f895c6fe	652	return HAL_OK;
mbed_official	340:28d1f895c6fe	653	}
mbed_official	340:28d1f895c6fe	654	else
mbed_official	340:28d1f895c6fe	655	{
mbed_official	340:28d1f895c6fe	656	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	657	}
mbed_official	340:28d1f895c6fe	658	}
mbed_official	340:28d1f895c6fe	659
mbed_official	340:28d1f895c6fe	660	/**
mbed_official	631:825f75ca301e	661	* @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
mbed_official	340:28d1f895c6fe	662	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	663	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	664	* @param pData: Pointer to data buffer
mbed_official	340:28d1f895c6fe	665	* @param Size: Amount of data to be sent
mbed_official	340:28d1f895c6fe	666	* @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
mbed_official	340:28d1f895c6fe	667	* @retval HAL status
mbed_official	340:28d1f895c6fe	668	*/
mbed_official	340:28d1f895c6fe	669	HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef hsmbus, uint8_t pData, uint16_t Size, uint32_t XferOptions)
mbed_official	340:28d1f895c6fe	670	{
mbed_official	340:28d1f895c6fe	671	/* Check the parameters */
mbed_official	340:28d1f895c6fe	672	assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
mbed_official	340:28d1f895c6fe	673
mbed_official	340:28d1f895c6fe	674	if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
mbed_official	340:28d1f895c6fe	675	{
mbed_official	442:d2c15dda23c1	676	if((pData == NULL) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	677	{
mbed_official	340:28d1f895c6fe	678	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	679	}
mbed_official	340:28d1f895c6fe	680
mbed_official	340:28d1f895c6fe	681	/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
mbed_official	340:28d1f895c6fe	682	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR \| SMBUS_IT_TX);
mbed_official	340:28d1f895c6fe	683
mbed_official	340:28d1f895c6fe	684	/* Process Locked */
mbed_official	340:28d1f895c6fe	685	__HAL_LOCK(hsmbus);
mbed_official	340:28d1f895c6fe	686
mbed_official	340:28d1f895c6fe	687	hsmbus->State \|= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
mbed_official	340:28d1f895c6fe	688	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
mbed_official	340:28d1f895c6fe	689
mbed_official	340:28d1f895c6fe	690	/* Set SBC bit to manage Acknowledge at each bit */
mbed_official	340:28d1f895c6fe	691	hsmbus->Instance->CR1 \|= I2C_CR1_SBC;
mbed_official	340:28d1f895c6fe	692
mbed_official	340:28d1f895c6fe	693	/* Enable Address Acknowledge */
mbed_official	340:28d1f895c6fe	694	hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
mbed_official	340:28d1f895c6fe	695
mbed_official	340:28d1f895c6fe	696	/* Prepare transfer parameters */
mbed_official	340:28d1f895c6fe	697	hsmbus->pBuffPtr = pData;
mbed_official	340:28d1f895c6fe	698	hsmbus->XferSize = Size;
mbed_official	340:28d1f895c6fe	699	hsmbus->XferCount = Size;
mbed_official	340:28d1f895c6fe	700	hsmbus->XferOptions = XferOptions;
mbed_official	340:28d1f895c6fe	701
mbed_official	340:28d1f895c6fe	702	if(Size > MAX_NBYTE_SIZE)
mbed_official	340:28d1f895c6fe	703	{
mbed_official	340:28d1f895c6fe	704	hsmbus->XferSize = MAX_NBYTE_SIZE;
mbed_official	340:28d1f895c6fe	705	}
mbed_official	340:28d1f895c6fe	706	else
mbed_official	340:28d1f895c6fe	707	{
mbed_official	340:28d1f895c6fe	708	hsmbus->XferSize = Size;
mbed_official	340:28d1f895c6fe	709	}
mbed_official	340:28d1f895c6fe	710
mbed_official	340:28d1f895c6fe	711	/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
mbed_official	340:28d1f895c6fe	712	if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
mbed_official	340:28d1f895c6fe	713	{
mbed_official	340:28d1f895c6fe	714	SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, SMBUS_RELOAD_MODE \| (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	715	}
mbed_official	340:28d1f895c6fe	716	else
mbed_official	340:28d1f895c6fe	717	{
mbed_official	340:28d1f895c6fe	718	/* Set NBYTE to transmit */
mbed_official	340:28d1f895c6fe	719	SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	720
mbed_official	340:28d1f895c6fe	721	/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
mbed_official	340:28d1f895c6fe	722	/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
mbed_official	631:825f75ca301e	723	if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
mbed_official	340:28d1f895c6fe	724	{
mbed_official	340:28d1f895c6fe	725	hsmbus->XferSize--;
mbed_official	340:28d1f895c6fe	726	hsmbus->XferCount--;
mbed_official	340:28d1f895c6fe	727	}
mbed_official	340:28d1f895c6fe	728	}
mbed_official	340:28d1f895c6fe	729
mbed_official	340:28d1f895c6fe	730	/* Clear ADDR flag after prepare the transfer parameters */
mbed_official	340:28d1f895c6fe	731	/* This action will generate an acknowledge to the HOST */
mbed_official	340:28d1f895c6fe	732	__HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
mbed_official	340:28d1f895c6fe	733
mbed_official	340:28d1f895c6fe	734	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	735	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	736
mbed_official	340:28d1f895c6fe	737	/* Note : The SMBUS interrupts must be enabled after unlocking current process
mbed_official	340:28d1f895c6fe	738	to avoid the risk of SMBUS interrupt handle execution before current
mbed_official	340:28d1f895c6fe	739	process unlock */
mbed_official	340:28d1f895c6fe	740	/* REnable ADDR interrupt */
mbed_official	340:28d1f895c6fe	741	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX \| SMBUS_IT_ADDR);
mbed_official	340:28d1f895c6fe	742
mbed_official	340:28d1f895c6fe	743	return HAL_OK;
mbed_official	340:28d1f895c6fe	744	}
mbed_official	340:28d1f895c6fe	745	else
mbed_official	340:28d1f895c6fe	746	{
mbed_official	340:28d1f895c6fe	747	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	748	}
mbed_official	340:28d1f895c6fe	749	}
mbed_official	340:28d1f895c6fe	750
mbed_official	340:28d1f895c6fe	751	/**
mbed_official	631:825f75ca301e	752	* @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt.
mbed_official	340:28d1f895c6fe	753	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	754	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	755	* @param pData: Pointer to data buffer
mbed_official	340:28d1f895c6fe	756	* @param Size: Amount of data to be sent
mbed_official	340:28d1f895c6fe	757	* @param XferOptions: Options of Transfer, value of @ref SMBUS_XferOptions_definition
mbed_official	340:28d1f895c6fe	758	* @retval HAL status
mbed_official	340:28d1f895c6fe	759	*/
mbed_official	340:28d1f895c6fe	760	HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef hsmbus, uint8_t pData, uint16_t Size, uint32_t XferOptions)
mbed_official	340:28d1f895c6fe	761	{
mbed_official	340:28d1f895c6fe	762	/* Check the parameters */
mbed_official	340:28d1f895c6fe	763	assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
mbed_official	340:28d1f895c6fe	764
mbed_official	340:28d1f895c6fe	765	if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
mbed_official	340:28d1f895c6fe	766	{
mbed_official	442:d2c15dda23c1	767	if((pData == NULL) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	768	{
mbed_official	340:28d1f895c6fe	769	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	770	}
mbed_official	340:28d1f895c6fe	771
mbed_official	340:28d1f895c6fe	772	/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
mbed_official	340:28d1f895c6fe	773	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR \| SMBUS_IT_RX);
mbed_official	340:28d1f895c6fe	774
mbed_official	340:28d1f895c6fe	775	/* Process Locked */
mbed_official	340:28d1f895c6fe	776	__HAL_LOCK(hsmbus);
mbed_official	340:28d1f895c6fe	777
mbed_official	340:28d1f895c6fe	778	hsmbus->State \|= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
mbed_official	340:28d1f895c6fe	779	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
mbed_official	340:28d1f895c6fe	780
mbed_official	340:28d1f895c6fe	781	/* Set SBC bit to manage Acknowledge at each bit */
mbed_official	340:28d1f895c6fe	782	hsmbus->Instance->CR1 \|= I2C_CR1_SBC;
mbed_official	340:28d1f895c6fe	783
mbed_official	340:28d1f895c6fe	784	/* Enable Address Acknowledge */
mbed_official	340:28d1f895c6fe	785	hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
mbed_official	340:28d1f895c6fe	786
mbed_official	340:28d1f895c6fe	787	/* Prepare transfer parameters */
mbed_official	340:28d1f895c6fe	788	hsmbus->pBuffPtr = pData;
mbed_official	340:28d1f895c6fe	789	hsmbus->XferSize = Size;
mbed_official	340:28d1f895c6fe	790	hsmbus->XferCount = Size;
mbed_official	340:28d1f895c6fe	791	hsmbus->XferOptions = XferOptions;
mbed_official	340:28d1f895c6fe	792
mbed_official	340:28d1f895c6fe	793	/* Set NBYTE to receive */
mbed_official	340:28d1f895c6fe	794	/* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */
mbed_official	340:28d1f895c6fe	795	/* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
mbed_official	340:28d1f895c6fe	796	/* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
mbed_official	340:28d1f895c6fe	797	/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
mbed_official	631:825f75ca301e	798	if((hsmbus->XferSize == 1) \|\| ((hsmbus->XferSize == 2) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
mbed_official	340:28d1f895c6fe	799	{
mbed_official	340:28d1f895c6fe	800	SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	801	}
mbed_official	340:28d1f895c6fe	802	else
mbed_official	340:28d1f895c6fe	803	{
mbed_official	340:28d1f895c6fe	804	SMBUS_TransferConfig(hsmbus,0, 1, hsmbus->XferOptions \| SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	805	}
mbed_official	340:28d1f895c6fe	806
mbed_official	340:28d1f895c6fe	807	/* Clear ADDR flag after prepare the transfer parameters */
mbed_official	340:28d1f895c6fe	808	/* This action will generate an acknowledge to the HOST */
mbed_official	340:28d1f895c6fe	809	__HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
mbed_official	340:28d1f895c6fe	810
mbed_official	340:28d1f895c6fe	811	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	812	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	813
mbed_official	340:28d1f895c6fe	814	/* Note : The SMBUS interrupts must be enabled after unlocking current process
mbed_official	340:28d1f895c6fe	815	to avoid the risk of SMBUS interrupt handle execution before current
mbed_official	340:28d1f895c6fe	816	process unlock */
mbed_official	340:28d1f895c6fe	817	/* REnable ADDR interrupt */
mbed_official	340:28d1f895c6fe	818	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX \| SMBUS_IT_ADDR);
mbed_official	340:28d1f895c6fe	819
mbed_official	340:28d1f895c6fe	820	return HAL_OK;
mbed_official	340:28d1f895c6fe	821	}
mbed_official	340:28d1f895c6fe	822	else
mbed_official	340:28d1f895c6fe	823	{
mbed_official	340:28d1f895c6fe	824	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	825	}
mbed_official	340:28d1f895c6fe	826	}
mbed_official	340:28d1f895c6fe	827
mbed_official	340:28d1f895c6fe	828	/**
mbed_official	631:825f75ca301e	829	* @brief Enable the Address listen mode with Interrupt.
mbed_official	340:28d1f895c6fe	830	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	831	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	832	* @retval HAL status
mbed_official	340:28d1f895c6fe	833	*/
mbed_official	631:825f75ca301e	834	HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	835	{
mbed_official	340:28d1f895c6fe	836	hsmbus->State = HAL_SMBUS_STATE_LISTEN;
mbed_official	340:28d1f895c6fe	837
mbed_official	340:28d1f895c6fe	838	/* Enable the Address Match interrupt */
mbed_official	340:28d1f895c6fe	839	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
mbed_official	340:28d1f895c6fe	840
mbed_official	340:28d1f895c6fe	841	return HAL_OK;
mbed_official	340:28d1f895c6fe	842	}
mbed_official	340:28d1f895c6fe	843
mbed_official	340:28d1f895c6fe	844	/**
mbed_official	631:825f75ca301e	845	* @brief Disable the Address listen mode with Interrupt.
mbed_official	340:28d1f895c6fe	846	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	847	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	848	* @retval HAL status
mbed_official	340:28d1f895c6fe	849	*/
mbed_official	340:28d1f895c6fe	850	HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	851	{
mbed_official	340:28d1f895c6fe	852	/* Disable Address listen mode only if a transfer is not ongoing */
mbed_official	340:28d1f895c6fe	853	if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
mbed_official	340:28d1f895c6fe	854	{
mbed_official	340:28d1f895c6fe	855	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	856
mbed_official	340:28d1f895c6fe	857	/* Disable the Address Match interrupt */
mbed_official	340:28d1f895c6fe	858	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
mbed_official	340:28d1f895c6fe	859
mbed_official	340:28d1f895c6fe	860	return HAL_OK;
mbed_official	340:28d1f895c6fe	861	}
mbed_official	340:28d1f895c6fe	862	else
mbed_official	340:28d1f895c6fe	863	{
mbed_official	340:28d1f895c6fe	864	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	865	}
mbed_official	340:28d1f895c6fe	866	}
mbed_official	340:28d1f895c6fe	867
mbed_official	340:28d1f895c6fe	868	/**
mbed_official	631:825f75ca301e	869	* @brief Enable the SMBUS alert mode with Interrupt.
mbed_official	340:28d1f895c6fe	870	* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	871	* the configuration information for the specified SMBUSx peripheral.
mbed_official	340:28d1f895c6fe	872	* @retval HAL status
mbed_official	340:28d1f895c6fe	873	*/
mbed_official	340:28d1f895c6fe	874	HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	875	{
mbed_official	340:28d1f895c6fe	876	/* Enable SMBus alert */
mbed_official	340:28d1f895c6fe	877	hsmbus->Instance->CR1 \|= I2C_CR1_ALERTEN;
mbed_official	340:28d1f895c6fe	878
mbed_official	340:28d1f895c6fe	879	/* Clear ALERT flag */
mbed_official	340:28d1f895c6fe	880	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
mbed_official	340:28d1f895c6fe	881
mbed_official	340:28d1f895c6fe	882	/* Enable Alert Interrupt */
mbed_official	340:28d1f895c6fe	883	SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
mbed_official	340:28d1f895c6fe	884
mbed_official	340:28d1f895c6fe	885	return HAL_OK;
mbed_official	340:28d1f895c6fe	886	}
mbed_official	340:28d1f895c6fe	887	/**
mbed_official	631:825f75ca301e	888	* @brief Disable the SMBUS alert mode with Interrupt.
mbed_official	340:28d1f895c6fe	889	* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	890	* the configuration information for the specified SMBUSx peripheral.
mbed_official	340:28d1f895c6fe	891	* @retval HAL status
mbed_official	340:28d1f895c6fe	892	*/
mbed_official	340:28d1f895c6fe	893	HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	894	{
mbed_official	340:28d1f895c6fe	895	/* Enable SMBus alert */
mbed_official	340:28d1f895c6fe	896	hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
mbed_official	340:28d1f895c6fe	897
mbed_official	340:28d1f895c6fe	898	/* Disable Alert Interrupt */
mbed_official	340:28d1f895c6fe	899	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
mbed_official	340:28d1f895c6fe	900
mbed_official	340:28d1f895c6fe	901	return HAL_OK;
mbed_official	340:28d1f895c6fe	902	}
mbed_official	340:28d1f895c6fe	903
mbed_official	340:28d1f895c6fe	904	/**
mbed_official	631:825f75ca301e	905	* @brief Check if target device is ready for communication.
mbed_official	340:28d1f895c6fe	906	* @note This function is used with Memory devices
mbed_official	340:28d1f895c6fe	907	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	908	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	909	* @param DevAddress: Target device address
mbed_official	340:28d1f895c6fe	910	* @param Trials: Number of trials
mbed_official	340:28d1f895c6fe	911	* @param Timeout: Timeout duration
mbed_official	340:28d1f895c6fe	912	* @retval HAL status
mbed_official	340:28d1f895c6fe	913	*/
mbed_official	340:28d1f895c6fe	914	HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
mbed_official	340:28d1f895c6fe	915	{
mbed_official	340:28d1f895c6fe	916	uint32_t tickstart = 0;
mbed_official	340:28d1f895c6fe	917
mbed_official	340:28d1f895c6fe	918	__IO uint32_t SMBUS_Trials = 0;
mbed_official	340:28d1f895c6fe	919
mbed_official	340:28d1f895c6fe	920	if(hsmbus->State == HAL_SMBUS_STATE_READY)
mbed_official	340:28d1f895c6fe	921	{
mbed_official	340:28d1f895c6fe	922	if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
mbed_official	340:28d1f895c6fe	923	{
mbed_official	340:28d1f895c6fe	924	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	925	}
mbed_official	340:28d1f895c6fe	926
mbed_official	340:28d1f895c6fe	927	/* Process Locked */
mbed_official	340:28d1f895c6fe	928	__HAL_LOCK(hsmbus);
mbed_official	340:28d1f895c6fe	929
mbed_official	340:28d1f895c6fe	930	hsmbus->State = HAL_SMBUS_STATE_BUSY;
mbed_official	340:28d1f895c6fe	931	hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
mbed_official	340:28d1f895c6fe	932
mbed_official	340:28d1f895c6fe	933	do
mbed_official	340:28d1f895c6fe	934	{
mbed_official	340:28d1f895c6fe	935	/* Generate Start */
mbed_official	631:825f75ca301e	936	hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
mbed_official	340:28d1f895c6fe	937
mbed_official	340:28d1f895c6fe	938	/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
mbed_official	340:28d1f895c6fe	939	/* Wait until STOPF flag is set or a NACK flag is set*/
mbed_official	340:28d1f895c6fe	940	tickstart = HAL_GetTick();
mbed_official	340:28d1f895c6fe	941	while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
mbed_official	340:28d1f895c6fe	942	{
mbed_official	340:28d1f895c6fe	943	if(Timeout != HAL_MAX_DELAY)
mbed_official	340:28d1f895c6fe	944	{
mbed_official	340:28d1f895c6fe	945	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
mbed_official	340:28d1f895c6fe	946	{
mbed_official	340:28d1f895c6fe	947	/* Device is ready */
mbed_official	340:28d1f895c6fe	948	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	949
mbed_official	340:28d1f895c6fe	950	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	951	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	952	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	953	}
mbed_official	340:28d1f895c6fe	954	}
mbed_official	340:28d1f895c6fe	955	}
mbed_official	340:28d1f895c6fe	956
mbed_official	340:28d1f895c6fe	957	/* Check if the NACKF flag has not been set */
mbed_official	340:28d1f895c6fe	958	if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
mbed_official	340:28d1f895c6fe	959	{
mbed_official	340:28d1f895c6fe	960	/* Wait until STOPF flag is reset */
mbed_official	340:28d1f895c6fe	961	if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	962	{
mbed_official	340:28d1f895c6fe	963	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	964	}
mbed_official	340:28d1f895c6fe	965
mbed_official	340:28d1f895c6fe	966	/* Clear STOP Flag */
mbed_official	340:28d1f895c6fe	967	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
mbed_official	340:28d1f895c6fe	968
mbed_official	340:28d1f895c6fe	969	/* Device is ready */
mbed_official	340:28d1f895c6fe	970	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	971
mbed_official	340:28d1f895c6fe	972	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	973	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	974
mbed_official	340:28d1f895c6fe	975	return HAL_OK;
mbed_official	340:28d1f895c6fe	976	}
mbed_official	340:28d1f895c6fe	977	else
mbed_official	340:28d1f895c6fe	978	{
mbed_official	340:28d1f895c6fe	979	/* Wait until STOPF flag is reset */
mbed_official	340:28d1f895c6fe	980	if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	981	{
mbed_official	340:28d1f895c6fe	982	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	983	}
mbed_official	340:28d1f895c6fe	984
mbed_official	340:28d1f895c6fe	985	/* Clear NACK Flag */
mbed_official	340:28d1f895c6fe	986	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
mbed_official	340:28d1f895c6fe	987
mbed_official	340:28d1f895c6fe	988	/* Clear STOP Flag, auto generated with autoend*/
mbed_official	340:28d1f895c6fe	989	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
mbed_official	340:28d1f895c6fe	990	}
mbed_official	340:28d1f895c6fe	991
mbed_official	340:28d1f895c6fe	992	/* Check if the maximum allowed number of trials has been reached */
mbed_official	340:28d1f895c6fe	993	if (SMBUS_Trials++ == Trials)
mbed_official	340:28d1f895c6fe	994	{
mbed_official	340:28d1f895c6fe	995	/* Generate Stop */
mbed_official	340:28d1f895c6fe	996	hsmbus->Instance->CR2 \|= I2C_CR2_STOP;
mbed_official	340:28d1f895c6fe	997
mbed_official	340:28d1f895c6fe	998	/* Wait until STOPF flag is reset */
mbed_official	340:28d1f895c6fe	999	if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	1000	{
mbed_official	340:28d1f895c6fe	1001	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	1002	}
mbed_official	340:28d1f895c6fe	1003
mbed_official	340:28d1f895c6fe	1004	/* Clear STOP Flag */
mbed_official	340:28d1f895c6fe	1005	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
mbed_official	340:28d1f895c6fe	1006	}
mbed_official	340:28d1f895c6fe	1007	}while(SMBUS_Trials < Trials);
mbed_official	340:28d1f895c6fe	1008
mbed_official	340:28d1f895c6fe	1009	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1010
mbed_official	340:28d1f895c6fe	1011	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1012	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1013
mbed_official	340:28d1f895c6fe	1014	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	1015	}
mbed_official	340:28d1f895c6fe	1016	else
mbed_official	340:28d1f895c6fe	1017	{
mbed_official	340:28d1f895c6fe	1018	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	1019	}
mbed_official	340:28d1f895c6fe	1020	}
mbed_official	631:825f75ca301e	1021	/**
mbed_official	631:825f75ca301e	1022	* @}
mbed_official	631:825f75ca301e	1023	*/
mbed_official	631:825f75ca301e	1024
mbed_official	631:825f75ca301e	1025	/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
mbed_official	631:825f75ca301e	1026	* @{
mbed_official	631:825f75ca301e	1027	*/
mbed_official	340:28d1f895c6fe	1028
mbed_official	340:28d1f895c6fe	1029	/**
mbed_official	631:825f75ca301e	1030	* @brief Handle SMBUS event interrupt request.
mbed_official	340:28d1f895c6fe	1031	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1032	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1033	* @retval None
mbed_official	340:28d1f895c6fe	1034	*/
mbed_official	340:28d1f895c6fe	1035	void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1036	{
mbed_official	340:28d1f895c6fe	1037	uint32_t tmpisrvalue = 0;
mbed_official	340:28d1f895c6fe	1038
mbed_official	340:28d1f895c6fe	1039	/* Use a local variable to store the current ISR flags */
mbed_official	340:28d1f895c6fe	1040	/* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
mbed_official	631:825f75ca301e	1041	tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
mbed_official	340:28d1f895c6fe	1042
mbed_official	340:28d1f895c6fe	1043	/* SMBUS in mode Transmitter ---------------------------------------------------*/
mbed_official	631:825f75ca301e	1044	if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) \|\| (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) \|\| (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) \|\| (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) \|\| (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI\| SMBUS_IT_STOPI\| SMBUS_IT_NACKI \| SMBUS_IT_TXI)) != RESET))
mbed_official	340:28d1f895c6fe	1045	{
mbed_official	340:28d1f895c6fe	1046	/* Slave mode selected */
mbed_official	340:28d1f895c6fe	1047	if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
mbed_official	340:28d1f895c6fe	1048	{
mbed_official	340:28d1f895c6fe	1049	SMBUS_Slave_ISR(hsmbus);
mbed_official	340:28d1f895c6fe	1050	}
mbed_official	340:28d1f895c6fe	1051	/* Master mode selected */
mbed_official	340:28d1f895c6fe	1052	else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
mbed_official	340:28d1f895c6fe	1053	{
mbed_official	340:28d1f895c6fe	1054	SMBUS_Master_ISR(hsmbus);
mbed_official	340:28d1f895c6fe	1055	}
mbed_official	340:28d1f895c6fe	1056	}
mbed_official	340:28d1f895c6fe	1057
mbed_official	340:28d1f895c6fe	1058	/* SMBUS in mode Receiver ----------------------------------------------------*/
mbed_official	631:825f75ca301e	1059	if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) \|\| (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) \|\| (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) \|\| (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) \|\| (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI\| SMBUS_IT_STOPI\| SMBUS_IT_NACKI \| SMBUS_IT_RXI)) != RESET))
mbed_official	340:28d1f895c6fe	1060	{
mbed_official	340:28d1f895c6fe	1061	/* Slave mode selected */
mbed_official	340:28d1f895c6fe	1062	if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
mbed_official	340:28d1f895c6fe	1063	{
mbed_official	340:28d1f895c6fe	1064	SMBUS_Slave_ISR(hsmbus);
mbed_official	340:28d1f895c6fe	1065	}
mbed_official	340:28d1f895c6fe	1066	/* Master mode selected */
mbed_official	340:28d1f895c6fe	1067	else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
mbed_official	340:28d1f895c6fe	1068	{
mbed_official	340:28d1f895c6fe	1069	SMBUS_Master_ISR(hsmbus);
mbed_official	340:28d1f895c6fe	1070	}
mbed_official	340:28d1f895c6fe	1071	}
mbed_official	340:28d1f895c6fe	1072
mbed_official	340:28d1f895c6fe	1073	/* SMBUS in mode Listener Only --------------------------------------------------*/
mbed_official	631:825f75ca301e	1074	if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) \|\| (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) \|\| (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
mbed_official	340:28d1f895c6fe	1075	&& ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) \|\| (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) \|\| (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
mbed_official	340:28d1f895c6fe	1076	{
mbed_official	340:28d1f895c6fe	1077	if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
mbed_official	340:28d1f895c6fe	1078	{
mbed_official	340:28d1f895c6fe	1079	SMBUS_Slave_ISR(hsmbus);
mbed_official	340:28d1f895c6fe	1080	}
mbed_official	340:28d1f895c6fe	1081	}
mbed_official	340:28d1f895c6fe	1082	}
mbed_official	340:28d1f895c6fe	1083
mbed_official	340:28d1f895c6fe	1084	/**
mbed_official	631:825f75ca301e	1085	* @brief Handle SMBUS error interrupt request.
mbed_official	340:28d1f895c6fe	1086	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1087	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1088	* @retval None
mbed_official	340:28d1f895c6fe	1089	*/
mbed_official	340:28d1f895c6fe	1090	void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1091	{
mbed_official	340:28d1f895c6fe	1092	/* SMBUS Bus error interrupt occurred ------------------------------------*/
mbed_official	340:28d1f895c6fe	1093	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
mbed_official	340:28d1f895c6fe	1094	{
mbed_official	340:28d1f895c6fe	1095	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_BERR;
mbed_official	340:28d1f895c6fe	1096
mbed_official	340:28d1f895c6fe	1097	/* Clear BERR flag */
mbed_official	340:28d1f895c6fe	1098	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
mbed_official	340:28d1f895c6fe	1099	}
mbed_official	340:28d1f895c6fe	1100
mbed_official	340:28d1f895c6fe	1101	/* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
mbed_official	340:28d1f895c6fe	1102	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
mbed_official	340:28d1f895c6fe	1103	{
mbed_official	340:28d1f895c6fe	1104	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_OVR;
mbed_official	340:28d1f895c6fe	1105
mbed_official	340:28d1f895c6fe	1106	/* Clear OVR flag */
mbed_official	340:28d1f895c6fe	1107	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
mbed_official	340:28d1f895c6fe	1108	}
mbed_official	340:28d1f895c6fe	1109
mbed_official	340:28d1f895c6fe	1110	/* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
mbed_official	340:28d1f895c6fe	1111	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
mbed_official	340:28d1f895c6fe	1112	{
mbed_official	340:28d1f895c6fe	1113	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_ARLO;
mbed_official	340:28d1f895c6fe	1114
mbed_official	340:28d1f895c6fe	1115	/* Clear ARLO flag */
mbed_official	340:28d1f895c6fe	1116	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
mbed_official	340:28d1f895c6fe	1117	}
mbed_official	340:28d1f895c6fe	1118
mbed_official	340:28d1f895c6fe	1119	/* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
mbed_official	340:28d1f895c6fe	1120	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
mbed_official	340:28d1f895c6fe	1121	{
mbed_official	340:28d1f895c6fe	1122	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_BUSTIMEOUT;
mbed_official	340:28d1f895c6fe	1123
mbed_official	340:28d1f895c6fe	1124	/* Clear TIMEOUT flag */
mbed_official	340:28d1f895c6fe	1125	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
mbed_official	340:28d1f895c6fe	1126	}
mbed_official	340:28d1f895c6fe	1127
mbed_official	340:28d1f895c6fe	1128	/* SMBUS Alert error interrupt occurred -----------------------------------------------*/
mbed_official	340:28d1f895c6fe	1129	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
mbed_official	340:28d1f895c6fe	1130	{
mbed_official	340:28d1f895c6fe	1131	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_ALERT;
mbed_official	340:28d1f895c6fe	1132
mbed_official	340:28d1f895c6fe	1133	/* Clear ALERT flag */
mbed_official	340:28d1f895c6fe	1134	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
mbed_official	340:28d1f895c6fe	1135	}
mbed_official	340:28d1f895c6fe	1136
mbed_official	340:28d1f895c6fe	1137	/* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
mbed_official	340:28d1f895c6fe	1138	if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
mbed_official	340:28d1f895c6fe	1139	{
mbed_official	340:28d1f895c6fe	1140	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_PECERR;
mbed_official	340:28d1f895c6fe	1141
mbed_official	340:28d1f895c6fe	1142	/* Clear PEC error flag */
mbed_official	340:28d1f895c6fe	1143	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
mbed_official	340:28d1f895c6fe	1144	}
mbed_official	340:28d1f895c6fe	1145
mbed_official	631:825f75ca301e	1146	/* Call the Error Callback() in case of Error detected */
mbed_official	340:28d1f895c6fe	1147	if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
mbed_official	340:28d1f895c6fe	1148	{
mbed_official	631:825f75ca301e	1149	/* Do not Reset the HAL state in case of ALERT error */
mbed_official	340:28d1f895c6fe	1150	if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
mbed_official	340:28d1f895c6fe	1151	{
mbed_official	340:28d1f895c6fe	1152	if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
mbed_official	340:28d1f895c6fe	1153	\|\| ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
mbed_official	340:28d1f895c6fe	1154	{
mbed_official	340:28d1f895c6fe	1155	/* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
mbed_official	340:28d1f895c6fe	1156	/* keep HAL_SMBUS_STATE_LISTEN if set */
mbed_official	340:28d1f895c6fe	1157	hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1158	hsmbus->State = HAL_SMBUS_STATE_LISTEN;
mbed_official	340:28d1f895c6fe	1159	}
mbed_official	340:28d1f895c6fe	1160	}
mbed_official	340:28d1f895c6fe	1161
mbed_official	340:28d1f895c6fe	1162	/* Call the Error callback to prevent upper layer */
mbed_official	340:28d1f895c6fe	1163	HAL_SMBUS_ErrorCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1164	}
mbed_official	340:28d1f895c6fe	1165	}
mbed_official	340:28d1f895c6fe	1166
mbed_official	340:28d1f895c6fe	1167	/**
mbed_official	631:825f75ca301e	1168	* @brief Master Tx Transfer completed callback.
mbed_official	340:28d1f895c6fe	1169	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1170	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1171	* @retval None
mbed_official	340:28d1f895c6fe	1172	*/
mbed_official	340:28d1f895c6fe	1173	__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1174	{
mbed_official	631:825f75ca301e	1175	/* NOTE : This function should not be modified, when the callback is needed,
mbed_official	631:825f75ca301e	1176	the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
mbed_official	340:28d1f895c6fe	1177	*/
mbed_official	340:28d1f895c6fe	1178	}
mbed_official	340:28d1f895c6fe	1179
mbed_official	340:28d1f895c6fe	1180	/**
mbed_official	631:825f75ca301e	1181	* @brief Master Rx Transfer completed callback.
mbed_official	340:28d1f895c6fe	1182	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1183	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1184	* @retval None
mbed_official	340:28d1f895c6fe	1185	*/
mbed_official	340:28d1f895c6fe	1186	__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1187	{
mbed_official	631:825f75ca301e	1188	/* NOTE : This function should not be modified, when the callback is needed,
mbed_official	631:825f75ca301e	1189	the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
mbed_official	340:28d1f895c6fe	1190	*/
mbed_official	340:28d1f895c6fe	1191	}
mbed_official	340:28d1f895c6fe	1192
mbed_official	631:825f75ca301e	1193	/** @brief Slave Tx Transfer completed callback.
mbed_official	340:28d1f895c6fe	1194	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1195	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1196	* @retval None
mbed_official	340:28d1f895c6fe	1197	*/
mbed_official	340:28d1f895c6fe	1198	__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1199	{
mbed_official	631:825f75ca301e	1200	/* NOTE : This function should not be modified, when the callback is needed,
mbed_official	631:825f75ca301e	1201	the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
mbed_official	340:28d1f895c6fe	1202	*/
mbed_official	340:28d1f895c6fe	1203	}
mbed_official	340:28d1f895c6fe	1204
mbed_official	340:28d1f895c6fe	1205	/**
mbed_official	631:825f75ca301e	1206	* @brief Slave Rx Transfer completed callback.
mbed_official	340:28d1f895c6fe	1207	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1208	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1209	* @retval None
mbed_official	340:28d1f895c6fe	1210	*/
mbed_official	340:28d1f895c6fe	1211	__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1212	{
mbed_official	631:825f75ca301e	1213	/* NOTE : This function should not be modified, when the callback is needed,
mbed_official	631:825f75ca301e	1214	the HAL_SMBUS_TxCpltCallback() could be implemented in the user file
mbed_official	340:28d1f895c6fe	1215	*/
mbed_official	340:28d1f895c6fe	1216	}
mbed_official	340:28d1f895c6fe	1217
mbed_official	340:28d1f895c6fe	1218	/**
mbed_official	631:825f75ca301e	1219	* @brief Slave Address Match callback.
mbed_official	340:28d1f895c6fe	1220	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1221	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1222	* @param TransferDirection: Master request Transfer Direction (Write/Read)
mbed_official	340:28d1f895c6fe	1223	* @param AddrMatchCode: Address Match Code
mbed_official	340:28d1f895c6fe	1224	* @retval None
mbed_official	340:28d1f895c6fe	1225	*/
mbed_official	631:825f75ca301e	1226	__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
mbed_official	340:28d1f895c6fe	1227	{
mbed_official	631:825f75ca301e	1228	/* NOTE : This function should not be modified, when the callback is needed,
mbed_official	631:825f75ca301e	1229	the HAL_SMBUS_AddrCallback() could be implemented in the user file
mbed_official	340:28d1f895c6fe	1230	*/
mbed_official	340:28d1f895c6fe	1231	}
mbed_official	340:28d1f895c6fe	1232
mbed_official	340:28d1f895c6fe	1233	/**
mbed_official	631:825f75ca301e	1234	* @brief Listen Complete callback.
mbed_official	340:28d1f895c6fe	1235	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1236	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1237	* @retval None
mbed_official	340:28d1f895c6fe	1238	*/
mbed_official	631:825f75ca301e	1239	__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1240	{
mbed_official	631:825f75ca301e	1241	/* NOTE : This function should not be modified, when the callback is needed,
mbed_official	631:825f75ca301e	1242	the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file
mbed_official	340:28d1f895c6fe	1243	*/
mbed_official	340:28d1f895c6fe	1244	}
mbed_official	340:28d1f895c6fe	1245
mbed_official	340:28d1f895c6fe	1246	/**
mbed_official	631:825f75ca301e	1247	* @brief SMBUS error callback.
mbed_official	340:28d1f895c6fe	1248	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1249	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1250	* @retval None
mbed_official	340:28d1f895c6fe	1251	*/
mbed_official	340:28d1f895c6fe	1252	__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1253	{
mbed_official	631:825f75ca301e	1254	/* NOTE : This function should not be modified, when the callback is needed,
mbed_official	631:825f75ca301e	1255	the HAL_SMBUS_ErrorCallback() could be implemented in the user file
mbed_official	340:28d1f895c6fe	1256	*/
mbed_official	340:28d1f895c6fe	1257	}
mbed_official	340:28d1f895c6fe	1258
mbed_official	340:28d1f895c6fe	1259	/**
mbed_official	340:28d1f895c6fe	1260	* @}
mbed_official	340:28d1f895c6fe	1261	*/
mbed_official	340:28d1f895c6fe	1262
mbed_official	340:28d1f895c6fe	1263	/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
mbed_official	340:28d1f895c6fe	1264	* @brief Peripheral State and Errors functions
mbed_official	340:28d1f895c6fe	1265	*
mbed_official	340:28d1f895c6fe	1266	@verbatim
mbed_official	340:28d1f895c6fe	1267	===============================================================================
mbed_official	340:28d1f895c6fe	1268	##### Peripheral State and Errors functions #####
mbed_official	340:28d1f895c6fe	1269	===============================================================================
mbed_official	340:28d1f895c6fe	1270	[..]
mbed_official	631:825f75ca301e	1271	This subsection permits to get in run-time the status of the peripheral
mbed_official	340:28d1f895c6fe	1272	and the data flow.
mbed_official	340:28d1f895c6fe	1273
mbed_official	340:28d1f895c6fe	1274	@endverbatim
mbed_official	340:28d1f895c6fe	1275	* @{
mbed_official	340:28d1f895c6fe	1276	*/
mbed_official	340:28d1f895c6fe	1277
mbed_official	340:28d1f895c6fe	1278	/**
mbed_official	631:825f75ca301e	1279	* @brief Return the SMBUS handle state.
mbed_official	631:825f75ca301e	1280	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	631:825f75ca301e	1281	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1282	* @retval HAL state
mbed_official	340:28d1f895c6fe	1283	*/
mbed_official	442:d2c15dda23c1	1284	uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1285	{
mbed_official	631:825f75ca301e	1286	/* Return SMBUS handle state */
mbed_official	340:28d1f895c6fe	1287	return hsmbus->State;
mbed_official	340:28d1f895c6fe	1288	}
mbed_official	340:28d1f895c6fe	1289
mbed_official	340:28d1f895c6fe	1290	/**
mbed_official	631:825f75ca301e	1291	* @brief Return the SMBUS error code.
mbed_official	340:28d1f895c6fe	1292	* @param hsmbus : pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1293	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1294	* @retval SMBUS Error Code
mbed_official	340:28d1f895c6fe	1295	*/
mbed_official	340:28d1f895c6fe	1296	uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1297	{
mbed_official	340:28d1f895c6fe	1298	return hsmbus->ErrorCode;
mbed_official	340:28d1f895c6fe	1299	}
mbed_official	340:28d1f895c6fe	1300
mbed_official	340:28d1f895c6fe	1301	/**
mbed_official	340:28d1f895c6fe	1302	* @}
mbed_official	340:28d1f895c6fe	1303	*/
mbed_official	340:28d1f895c6fe	1304
mbed_official	340:28d1f895c6fe	1305	/**
mbed_official	340:28d1f895c6fe	1306	* @}
mbed_official	340:28d1f895c6fe	1307	*/
mbed_official	340:28d1f895c6fe	1308
mbed_official	340:28d1f895c6fe	1309	/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
mbed_official	340:28d1f895c6fe	1310	* @brief Data transfers Private functions
mbed_official	340:28d1f895c6fe	1311	* @{
mbed_official	340:28d1f895c6fe	1312	*/
mbed_official	340:28d1f895c6fe	1313
mbed_official	340:28d1f895c6fe	1314	/**
mbed_official	631:825f75ca301e	1315	* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
mbed_official	340:28d1f895c6fe	1316	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1317	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1318	* @retval HAL status
mbed_official	340:28d1f895c6fe	1319	*/
mbed_official	340:28d1f895c6fe	1320	static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1321	{
mbed_official	340:28d1f895c6fe	1322	uint16_t DevAddress;
mbed_official	340:28d1f895c6fe	1323
mbed_official	340:28d1f895c6fe	1324	/* Process Locked */
mbed_official	340:28d1f895c6fe	1325	__HAL_LOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1326
mbed_official	340:28d1f895c6fe	1327	if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
mbed_official	340:28d1f895c6fe	1328	{
mbed_official	340:28d1f895c6fe	1329	/* Clear NACK Flag */
mbed_official	340:28d1f895c6fe	1330	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
mbed_official	340:28d1f895c6fe	1331
mbed_official	340:28d1f895c6fe	1332	/* Set corresponding Error Code */
mbed_official	340:28d1f895c6fe	1333	/* No need to generate STOP, it is automatically done */
mbed_official	340:28d1f895c6fe	1334	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_ACKF;
mbed_official	340:28d1f895c6fe	1335
mbed_official	340:28d1f895c6fe	1336	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1337	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1338
mbed_official	340:28d1f895c6fe	1339	/* Call the Error callback to prevent upper layer */
mbed_official	340:28d1f895c6fe	1340	HAL_SMBUS_ErrorCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1341	}
mbed_official	340:28d1f895c6fe	1342	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
mbed_official	340:28d1f895c6fe	1343	{
mbed_official	340:28d1f895c6fe	1344
mbed_official	340:28d1f895c6fe	1345	/* Call the corresponding callback to inform upper layer of End of Transfer */
mbed_official	340:28d1f895c6fe	1346	if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
mbed_official	340:28d1f895c6fe	1347	{
mbed_official	340:28d1f895c6fe	1348	/* Disable Interrupt */
mbed_official	340:28d1f895c6fe	1349	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
mbed_official	340:28d1f895c6fe	1350
mbed_official	340:28d1f895c6fe	1351	/* Clear STOP Flag */
mbed_official	340:28d1f895c6fe	1352	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
mbed_official	340:28d1f895c6fe	1353
mbed_official	340:28d1f895c6fe	1354	/* Clear Configuration Register 2 */
mbed_official	631:825f75ca301e	1355	SMBUS_RESET_CR2(hsmbus);
mbed_official	340:28d1f895c6fe	1356
mbed_official	340:28d1f895c6fe	1357	/* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
mbed_official	340:28d1f895c6fe	1358	/* Disable the selected SMBUS peripheral */
mbed_official	340:28d1f895c6fe	1359	__HAL_SMBUS_DISABLE(hsmbus);
mbed_official	340:28d1f895c6fe	1360
mbed_official	340:28d1f895c6fe	1361	hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1362	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1363
mbed_official	340:28d1f895c6fe	1364	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1365	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1366
mbed_official	340:28d1f895c6fe	1367	/* REenable the selected SMBUS peripheral */
mbed_official	340:28d1f895c6fe	1368	__HAL_SMBUS_ENABLE(hsmbus);
mbed_official	340:28d1f895c6fe	1369
mbed_official	340:28d1f895c6fe	1370	HAL_SMBUS_MasterTxCpltCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1371	}
mbed_official	340:28d1f895c6fe	1372	else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
mbed_official	340:28d1f895c6fe	1373	{
mbed_official	340:28d1f895c6fe	1374	/* Disable Interrupt */
mbed_official	340:28d1f895c6fe	1375	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
mbed_official	340:28d1f895c6fe	1376
mbed_official	340:28d1f895c6fe	1377	/* Clear STOP Flag */
mbed_official	340:28d1f895c6fe	1378	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
mbed_official	340:28d1f895c6fe	1379
mbed_official	340:28d1f895c6fe	1380	/* Clear Configuration Register 2 */
mbed_official	631:825f75ca301e	1381	SMBUS_RESET_CR2(hsmbus);
mbed_official	340:28d1f895c6fe	1382
mbed_official	340:28d1f895c6fe	1383	hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1384	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1385
mbed_official	340:28d1f895c6fe	1386	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1387	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1388
mbed_official	340:28d1f895c6fe	1389	HAL_SMBUS_MasterRxCpltCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1390	}
mbed_official	340:28d1f895c6fe	1391	}
mbed_official	340:28d1f895c6fe	1392	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
mbed_official	340:28d1f895c6fe	1393	{
mbed_official	340:28d1f895c6fe	1394	/* Read data from RXDR */
mbed_official	340:28d1f895c6fe	1395	(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
mbed_official	340:28d1f895c6fe	1396	hsmbus->XferSize--;
mbed_official	340:28d1f895c6fe	1397	hsmbus->XferCount--;
mbed_official	340:28d1f895c6fe	1398	}
mbed_official	340:28d1f895c6fe	1399	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
mbed_official	340:28d1f895c6fe	1400	{
mbed_official	340:28d1f895c6fe	1401	/* Write data to TXDR */
mbed_official	340:28d1f895c6fe	1402	hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
mbed_official	340:28d1f895c6fe	1403	hsmbus->XferSize--;
mbed_official	340:28d1f895c6fe	1404	hsmbus->XferCount--;
mbed_official	340:28d1f895c6fe	1405	}
mbed_official	340:28d1f895c6fe	1406	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
mbed_official	340:28d1f895c6fe	1407	{
mbed_official	340:28d1f895c6fe	1408	if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
mbed_official	340:28d1f895c6fe	1409	{
mbed_official	340:28d1f895c6fe	1410	DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
mbed_official	340:28d1f895c6fe	1411
mbed_official	340:28d1f895c6fe	1412	if(hsmbus->XferCount > MAX_NBYTE_SIZE)
mbed_official	340:28d1f895c6fe	1413	{
mbed_official	340:28d1f895c6fe	1414	SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE \| (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	1415	hsmbus->XferSize = MAX_NBYTE_SIZE;
mbed_official	340:28d1f895c6fe	1416	}
mbed_official	340:28d1f895c6fe	1417	else
mbed_official	340:28d1f895c6fe	1418	{
mbed_official	340:28d1f895c6fe	1419	hsmbus->XferSize = hsmbus->XferCount;
mbed_official	340:28d1f895c6fe	1420	SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	1421	/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
mbed_official	340:28d1f895c6fe	1422	/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
mbed_official	631:825f75ca301e	1423	if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
mbed_official	340:28d1f895c6fe	1424	{
mbed_official	340:28d1f895c6fe	1425	hsmbus->XferSize--;
mbed_official	340:28d1f895c6fe	1426	hsmbus->XferCount--;
mbed_official	340:28d1f895c6fe	1427	}
mbed_official	340:28d1f895c6fe	1428	}
mbed_official	340:28d1f895c6fe	1429	}
mbed_official	340:28d1f895c6fe	1430	else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0))
mbed_official	340:28d1f895c6fe	1431	{
mbed_official	631:825f75ca301e	1432	/* Call TxCpltCallback() if no stop mode is set */
mbed_official	631:825f75ca301e	1433	if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
mbed_official	340:28d1f895c6fe	1434	{
mbed_official	340:28d1f895c6fe	1435	/* Call the corresponding callback to inform upper layer of End of Transfer */
mbed_official	340:28d1f895c6fe	1436	if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
mbed_official	340:28d1f895c6fe	1437	{
mbed_official	340:28d1f895c6fe	1438	/* Disable Interrupt */
mbed_official	340:28d1f895c6fe	1439	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
mbed_official	340:28d1f895c6fe	1440	hsmbus->PreviousState = hsmbus->State;
mbed_official	340:28d1f895c6fe	1441	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1442
mbed_official	340:28d1f895c6fe	1443	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1444	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1445
mbed_official	340:28d1f895c6fe	1446	HAL_SMBUS_MasterTxCpltCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1447	}
mbed_official	340:28d1f895c6fe	1448	else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
mbed_official	340:28d1f895c6fe	1449	{
mbed_official	340:28d1f895c6fe	1450	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
mbed_official	340:28d1f895c6fe	1451	hsmbus->PreviousState = hsmbus->State;
mbed_official	340:28d1f895c6fe	1452	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1453
mbed_official	340:28d1f895c6fe	1454	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1455	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1456
mbed_official	340:28d1f895c6fe	1457	HAL_SMBUS_MasterRxCpltCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1458	}
mbed_official	340:28d1f895c6fe	1459	}
mbed_official	340:28d1f895c6fe	1460	}
mbed_official	340:28d1f895c6fe	1461	}
mbed_official	340:28d1f895c6fe	1462	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
mbed_official	340:28d1f895c6fe	1463	{
mbed_official	340:28d1f895c6fe	1464	if(hsmbus->XferCount == 0)
mbed_official	340:28d1f895c6fe	1465	{
mbed_official	340:28d1f895c6fe	1466	/* Specific use case for Quick command */
mbed_official	442:d2c15dda23c1	1467	if(hsmbus->pBuffPtr == NULL)
mbed_official	340:28d1f895c6fe	1468	{
mbed_official	340:28d1f895c6fe	1469	/* Generate a Stop command */
mbed_official	340:28d1f895c6fe	1470	hsmbus->Instance->CR2 \|= I2C_CR2_STOP;
mbed_official	340:28d1f895c6fe	1471	}
mbed_official	631:825f75ca301e	1472	/* Call TxCpltCallback() if no stop mode is set */
mbed_official	631:825f75ca301e	1473	else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
mbed_official	340:28d1f895c6fe	1474	{
mbed_official	340:28d1f895c6fe	1475	/* No Generate Stop, to permit restart mode */
mbed_official	340:28d1f895c6fe	1476	/* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
mbed_official	340:28d1f895c6fe	1477
mbed_official	340:28d1f895c6fe	1478	/* Call the corresponding callback to inform upper layer of End of Transfer */
mbed_official	340:28d1f895c6fe	1479	if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
mbed_official	340:28d1f895c6fe	1480	{
mbed_official	340:28d1f895c6fe	1481	/* Disable Interrupt */
mbed_official	340:28d1f895c6fe	1482	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
mbed_official	340:28d1f895c6fe	1483	hsmbus->PreviousState = hsmbus->State;
mbed_official	340:28d1f895c6fe	1484	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1485
mbed_official	340:28d1f895c6fe	1486	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1487	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1488
mbed_official	340:28d1f895c6fe	1489	HAL_SMBUS_MasterTxCpltCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1490	}
mbed_official	340:28d1f895c6fe	1491	else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
mbed_official	340:28d1f895c6fe	1492	{
mbed_official	340:28d1f895c6fe	1493	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
mbed_official	340:28d1f895c6fe	1494	hsmbus->PreviousState = hsmbus->State;
mbed_official	340:28d1f895c6fe	1495	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1496
mbed_official	340:28d1f895c6fe	1497	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1498	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1499
mbed_official	340:28d1f895c6fe	1500	HAL_SMBUS_MasterRxCpltCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1501	}
mbed_official	340:28d1f895c6fe	1502	}
mbed_official	340:28d1f895c6fe	1503	}
mbed_official	340:28d1f895c6fe	1504	}
mbed_official	340:28d1f895c6fe	1505
mbed_official	340:28d1f895c6fe	1506	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1507	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1508
mbed_official	340:28d1f895c6fe	1509	return HAL_OK;
mbed_official	340:28d1f895c6fe	1510	}
mbed_official	340:28d1f895c6fe	1511	/**
mbed_official	631:825f75ca301e	1512	* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
mbed_official	340:28d1f895c6fe	1513	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1514	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1515	* @retval HAL status
mbed_official	340:28d1f895c6fe	1516	*/
mbed_official	340:28d1f895c6fe	1517	static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
mbed_official	340:28d1f895c6fe	1518	{
mbed_official	340:28d1f895c6fe	1519	uint8_t TransferDirection = 0;
mbed_official	340:28d1f895c6fe	1520	uint16_t SlaveAddrCode = 0;
mbed_official	340:28d1f895c6fe	1521
mbed_official	340:28d1f895c6fe	1522	/* Process Locked */
mbed_official	340:28d1f895c6fe	1523	__HAL_LOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1524
mbed_official	340:28d1f895c6fe	1525	if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
mbed_official	340:28d1f895c6fe	1526	{
mbed_official	340:28d1f895c6fe	1527	/* Check that SMBUS transfer finished */
mbed_official	340:28d1f895c6fe	1528	/* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
mbed_official	340:28d1f895c6fe	1529	/* Mean XferCount == 0*/
mbed_official	340:28d1f895c6fe	1530	/* So clear Flag NACKF only */
mbed_official	340:28d1f895c6fe	1531	if(hsmbus->XferCount == 0)
mbed_official	340:28d1f895c6fe	1532	{
mbed_official	340:28d1f895c6fe	1533	/* Clear NACK Flag */
mbed_official	340:28d1f895c6fe	1534	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
mbed_official	340:28d1f895c6fe	1535
mbed_official	340:28d1f895c6fe	1536	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1537	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1538	}
mbed_official	340:28d1f895c6fe	1539	else
mbed_official	340:28d1f895c6fe	1540	{
mbed_official	340:28d1f895c6fe	1541	/* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/
mbed_official	340:28d1f895c6fe	1542	/* Clear NACK Flag */
mbed_official	340:28d1f895c6fe	1543	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
mbed_official	340:28d1f895c6fe	1544
mbed_official	340:28d1f895c6fe	1545	/* Set HAL State to "Idle" State, mean to LISTEN state */
mbed_official	340:28d1f895c6fe	1546	/* So reset Slave Busy state */
mbed_official	340:28d1f895c6fe	1547	hsmbus->PreviousState = hsmbus->State;
mbed_official	340:28d1f895c6fe	1548	hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
mbed_official	340:28d1f895c6fe	1549	hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
mbed_official	340:28d1f895c6fe	1550
mbed_official	340:28d1f895c6fe	1551	/* Disable RX/TX Interrupts, keep only ADDR Interrupt */
mbed_official	340:28d1f895c6fe	1552	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX \| SMBUS_IT_TX);
mbed_official	340:28d1f895c6fe	1553
mbed_official	340:28d1f895c6fe	1554	/* Set ErrorCode corresponding to a Non-Acknowledge */
mbed_official	340:28d1f895c6fe	1555	hsmbus->ErrorCode \|= HAL_SMBUS_ERROR_ACKF;
mbed_official	340:28d1f895c6fe	1556
mbed_official	340:28d1f895c6fe	1557	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1558	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1559
mbed_official	340:28d1f895c6fe	1560	/* Call the Error callback to prevent upper layer */
mbed_official	340:28d1f895c6fe	1561	HAL_SMBUS_ErrorCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1562	}
mbed_official	340:28d1f895c6fe	1563	}
mbed_official	340:28d1f895c6fe	1564	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
mbed_official	340:28d1f895c6fe	1565	{
mbed_official	631:825f75ca301e	1566	TransferDirection = SMBUS_GET_DIR(hsmbus);
mbed_official	631:825f75ca301e	1567	SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
mbed_official	340:28d1f895c6fe	1568
mbed_official	340:28d1f895c6fe	1569	/* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
mbed_official	340:28d1f895c6fe	1570	/* Other ADDRInterrupt will be treat in next Listen usecase */
mbed_official	340:28d1f895c6fe	1571	__HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
mbed_official	340:28d1f895c6fe	1572
mbed_official	340:28d1f895c6fe	1573	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1574	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1575
mbed_official	340:28d1f895c6fe	1576	/* Call Slave Addr callback */
mbed_official	631:825f75ca301e	1577	HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
mbed_official	340:28d1f895c6fe	1578	}
mbed_official	340:28d1f895c6fe	1579	else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) \|\| (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
mbed_official	340:28d1f895c6fe	1580	{
mbed_official	340:28d1f895c6fe	1581	if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
mbed_official	340:28d1f895c6fe	1582	{
mbed_official	340:28d1f895c6fe	1583	/* Read data from RXDR */
mbed_official	340:28d1f895c6fe	1584	(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
mbed_official	340:28d1f895c6fe	1585	hsmbus->XferSize--;
mbed_official	340:28d1f895c6fe	1586	hsmbus->XferCount--;
mbed_official	340:28d1f895c6fe	1587
mbed_official	340:28d1f895c6fe	1588	if(hsmbus->XferCount == 1)
mbed_official	340:28d1f895c6fe	1589	{
mbed_official	340:28d1f895c6fe	1590	/* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
mbed_official	340:28d1f895c6fe	1591	/* or only the last Byte of Transfer */
mbed_official	340:28d1f895c6fe	1592	/* So reset the RELOAD bit mode */
mbed_official	340:28d1f895c6fe	1593	hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
mbed_official	340:28d1f895c6fe	1594	SMBUS_TransferConfig(hsmbus,0 ,1 , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	1595	}
mbed_official	340:28d1f895c6fe	1596	else if(hsmbus->XferCount == 0)
mbed_official	340:28d1f895c6fe	1597	{
mbed_official	340:28d1f895c6fe	1598	/* Last Byte is received, disable Interrupt */
mbed_official	340:28d1f895c6fe	1599	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
mbed_official	340:28d1f895c6fe	1600
mbed_official	340:28d1f895c6fe	1601	/* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
mbed_official	340:28d1f895c6fe	1602	hsmbus->PreviousState = hsmbus->State;
mbed_official	340:28d1f895c6fe	1603	hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
mbed_official	340:28d1f895c6fe	1604
mbed_official	340:28d1f895c6fe	1605	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1606	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1607
mbed_official	340:28d1f895c6fe	1608	/* Call the Rx complete callback to inform upper layer of the end of receive process */
mbed_official	340:28d1f895c6fe	1609	HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1610	}
mbed_official	340:28d1f895c6fe	1611	else
mbed_official	340:28d1f895c6fe	1612	{
mbed_official	340:28d1f895c6fe	1613	/* Set Reload for next Bytes */
mbed_official	340:28d1f895c6fe	1614	SMBUS_TransferConfig(hsmbus,0, 1, SMBUS_RELOAD_MODE \| (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	1615
mbed_official	340:28d1f895c6fe	1616	/* Ack last Byte Read */
mbed_official	340:28d1f895c6fe	1617	hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
mbed_official	340:28d1f895c6fe	1618	}
mbed_official	340:28d1f895c6fe	1619	}
mbed_official	340:28d1f895c6fe	1620	else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
mbed_official	340:28d1f895c6fe	1621	{
mbed_official	340:28d1f895c6fe	1622	if((hsmbus->XferSize == 0)&&(hsmbus->XferCount!=0))
mbed_official	340:28d1f895c6fe	1623	{
mbed_official	340:28d1f895c6fe	1624	if(hsmbus->XferCount > MAX_NBYTE_SIZE)
mbed_official	340:28d1f895c6fe	1625	{
mbed_official	340:28d1f895c6fe	1626	SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE \| (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	1627	hsmbus->XferSize = MAX_NBYTE_SIZE;
mbed_official	340:28d1f895c6fe	1628	}
mbed_official	340:28d1f895c6fe	1629	else
mbed_official	340:28d1f895c6fe	1630	{
mbed_official	340:28d1f895c6fe	1631	hsmbus->XferSize = hsmbus->XferCount;
mbed_official	340:28d1f895c6fe	1632	SMBUS_TransferConfig(hsmbus, 0, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
mbed_official	340:28d1f895c6fe	1633	/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
mbed_official	340:28d1f895c6fe	1634	/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
mbed_official	631:825f75ca301e	1635	if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
mbed_official	340:28d1f895c6fe	1636	{
mbed_official	340:28d1f895c6fe	1637	hsmbus->XferSize--;
mbed_official	340:28d1f895c6fe	1638	hsmbus->XferCount--;
mbed_official	340:28d1f895c6fe	1639	}
mbed_official	340:28d1f895c6fe	1640	}
mbed_official	340:28d1f895c6fe	1641	}
mbed_official	340:28d1f895c6fe	1642	}
mbed_official	340:28d1f895c6fe	1643	}
mbed_official	340:28d1f895c6fe	1644	else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
mbed_official	340:28d1f895c6fe	1645	{
mbed_official	340:28d1f895c6fe	1646	/* Write data to TXDR only if XferCount not reach "0" */
mbed_official	340:28d1f895c6fe	1647	/* A TXIS flag can be set, during STOP treatment */
mbed_official	631:825f75ca301e	1648	/* Check if all Data have already been sent */
mbed_official	340:28d1f895c6fe	1649	/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
mbed_official	340:28d1f895c6fe	1650	if(hsmbus->XferCount > 0)
mbed_official	340:28d1f895c6fe	1651	{
mbed_official	340:28d1f895c6fe	1652	/* Write data to TXDR */
mbed_official	340:28d1f895c6fe	1653	hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
mbed_official	340:28d1f895c6fe	1654	hsmbus->XferCount--;
mbed_official	340:28d1f895c6fe	1655	hsmbus->XferSize--;
mbed_official	340:28d1f895c6fe	1656	}
mbed_official	340:28d1f895c6fe	1657
mbed_official	340:28d1f895c6fe	1658	if(hsmbus->XferCount == 0)
mbed_official	340:28d1f895c6fe	1659	{
mbed_official	340:28d1f895c6fe	1660	/* Last Byte is Transmitted */
mbed_official	340:28d1f895c6fe	1661	/* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
mbed_official	340:28d1f895c6fe	1662	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
mbed_official	340:28d1f895c6fe	1663	hsmbus->PreviousState = hsmbus->State;
mbed_official	340:28d1f895c6fe	1664	hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX);
mbed_official	340:28d1f895c6fe	1665
mbed_official	340:28d1f895c6fe	1666	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1667	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1668
mbed_official	340:28d1f895c6fe	1669	/* Call the Tx complete callback to inform upper layer of the end of transmit process */
mbed_official	340:28d1f895c6fe	1670	HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1671	}
mbed_official	340:28d1f895c6fe	1672	}
mbed_official	340:28d1f895c6fe	1673
mbed_official	340:28d1f895c6fe	1674	/* Check if STOPF is set */
mbed_official	340:28d1f895c6fe	1675	if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
mbed_official	340:28d1f895c6fe	1676	{
mbed_official	340:28d1f895c6fe	1677	if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
mbed_official	340:28d1f895c6fe	1678	{
mbed_official	340:28d1f895c6fe	1679	/* Disable RX and TX Interrupts */
mbed_official	340:28d1f895c6fe	1680	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX \| SMBUS_IT_TX);
mbed_official	340:28d1f895c6fe	1681
mbed_official	340:28d1f895c6fe	1682	/* Disable ADDR Interrupt */
mbed_official	340:28d1f895c6fe	1683	SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
mbed_official	340:28d1f895c6fe	1684
mbed_official	340:28d1f895c6fe	1685	/* Disable Address Acknowledge */
mbed_official	340:28d1f895c6fe	1686	hsmbus->Instance->CR2 \|= I2C_CR2_NACK;
mbed_official	340:28d1f895c6fe	1687
mbed_official	340:28d1f895c6fe	1688	/* Clear Configuration Register 2 */
mbed_official	631:825f75ca301e	1689	SMBUS_RESET_CR2(hsmbus);
mbed_official	340:28d1f895c6fe	1690
mbed_official	340:28d1f895c6fe	1691	/* Clear STOP Flag */
mbed_official	340:28d1f895c6fe	1692	__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
mbed_official	340:28d1f895c6fe	1693
mbed_official	340:28d1f895c6fe	1694	/* Clear ADDR flag */
mbed_official	340:28d1f895c6fe	1695	__HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
mbed_official	340:28d1f895c6fe	1696
mbed_official	340:28d1f895c6fe	1697	hsmbus->XferOptions = 0;
mbed_official	340:28d1f895c6fe	1698	hsmbus->PreviousState = hsmbus->State;
mbed_official	340:28d1f895c6fe	1699	hsmbus->State = HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1700
mbed_official	340:28d1f895c6fe	1701	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1702	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1703
mbed_official	340:28d1f895c6fe	1704	/* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
mbed_official	631:825f75ca301e	1705	HAL_SMBUS_ListenCpltCallback(hsmbus);
mbed_official	340:28d1f895c6fe	1706	}
mbed_official	340:28d1f895c6fe	1707	}
mbed_official	340:28d1f895c6fe	1708
mbed_official	340:28d1f895c6fe	1709	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1710	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1711
mbed_official	340:28d1f895c6fe	1712	return HAL_OK;
mbed_official	340:28d1f895c6fe	1713	}
mbed_official	340:28d1f895c6fe	1714	/**
mbed_official	631:825f75ca301e	1715	* @brief Manage the enabling of Interrupts.
mbed_official	340:28d1f895c6fe	1716	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1717	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1718	* @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
mbed_official	340:28d1f895c6fe	1719	* @retval HAL status
mbed_official	340:28d1f895c6fe	1720	*/
mbed_official	340:28d1f895c6fe	1721	static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
mbed_official	340:28d1f895c6fe	1722	{
mbed_official	340:28d1f895c6fe	1723	uint32_t tmpisr = 0;
mbed_official	340:28d1f895c6fe	1724
mbed_official	340:28d1f895c6fe	1725	if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
mbed_official	340:28d1f895c6fe	1726	{
mbed_official	340:28d1f895c6fe	1727	/* Enable ERR interrupt */
mbed_official	340:28d1f895c6fe	1728	tmpisr \|= SMBUS_IT_ERRI;
mbed_official	340:28d1f895c6fe	1729	}
mbed_official	340:28d1f895c6fe	1730
mbed_official	340:28d1f895c6fe	1731	if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
mbed_official	340:28d1f895c6fe	1732	{
mbed_official	340:28d1f895c6fe	1733	/* Enable ADDR, STOP interrupt */
mbed_official	340:28d1f895c6fe	1734	tmpisr \|= SMBUS_IT_ADDRI \| SMBUS_IT_STOPI \| SMBUS_IT_NACKI \| SMBUS_IT_ERRI;
mbed_official	340:28d1f895c6fe	1735	}
mbed_official	340:28d1f895c6fe	1736
mbed_official	340:28d1f895c6fe	1737	if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
mbed_official	340:28d1f895c6fe	1738	{
mbed_official	340:28d1f895c6fe	1739	/* Enable ERR, TC, STOP, NACK, RXI interrupt */
mbed_official	340:28d1f895c6fe	1740	tmpisr \|= SMBUS_IT_ERRI \| SMBUS_IT_TCI \| SMBUS_IT_STOPI \| SMBUS_IT_NACKI \| SMBUS_IT_TXI;
mbed_official	340:28d1f895c6fe	1741	}
mbed_official	340:28d1f895c6fe	1742
mbed_official	340:28d1f895c6fe	1743	if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
mbed_official	340:28d1f895c6fe	1744	{
mbed_official	340:28d1f895c6fe	1745	/* Enable ERR, TC, STOP, NACK, TXI interrupt */
mbed_official	340:28d1f895c6fe	1746	tmpisr \|= SMBUS_IT_ERRI \| SMBUS_IT_TCI \| SMBUS_IT_STOPI \| SMBUS_IT_NACKI \| SMBUS_IT_RXI;
mbed_official	340:28d1f895c6fe	1747	}
mbed_official	340:28d1f895c6fe	1748
mbed_official	340:28d1f895c6fe	1749	/* Enable interrupts only at the end */
mbed_official	340:28d1f895c6fe	1750	/* to avoid the risk of SMBUS interrupt handle execution before */
mbed_official	340:28d1f895c6fe	1751	/* all interrupts requested done */
mbed_official	340:28d1f895c6fe	1752	__HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
mbed_official	340:28d1f895c6fe	1753
mbed_official	340:28d1f895c6fe	1754	return HAL_OK;
mbed_official	340:28d1f895c6fe	1755	}
mbed_official	340:28d1f895c6fe	1756	/**
mbed_official	631:825f75ca301e	1757	* @brief Manage the disabling of Interrupts.
mbed_official	340:28d1f895c6fe	1758	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1759	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1760	* @param InterruptRequest : Value of @ref SMBUS_Interrupt_configuration_definition.
mbed_official	340:28d1f895c6fe	1761	* @retval HAL status
mbed_official	340:28d1f895c6fe	1762	*/
mbed_official	340:28d1f895c6fe	1763	static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
mbed_official	340:28d1f895c6fe	1764	{
mbed_official	340:28d1f895c6fe	1765	uint32_t tmpisr = 0;
mbed_official	340:28d1f895c6fe	1766
mbed_official	340:28d1f895c6fe	1767	if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
mbed_official	340:28d1f895c6fe	1768	{
mbed_official	340:28d1f895c6fe	1769	/* Disable ERR interrupt */
mbed_official	340:28d1f895c6fe	1770	tmpisr \|= SMBUS_IT_ERRI;
mbed_official	340:28d1f895c6fe	1771	}
mbed_official	340:28d1f895c6fe	1772
mbed_official	340:28d1f895c6fe	1773	if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
mbed_official	340:28d1f895c6fe	1774	{
mbed_official	340:28d1f895c6fe	1775	/* Disable TC, STOP, NACK, TXI interrupt */
mbed_official	340:28d1f895c6fe	1776	tmpisr \|= SMBUS_IT_TCI \| SMBUS_IT_TXI;
mbed_official	340:28d1f895c6fe	1777
mbed_official	631:825f75ca301e	1778	if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
mbed_official	340:28d1f895c6fe	1779	&& ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
mbed_official	340:28d1f895c6fe	1780	{
mbed_official	340:28d1f895c6fe	1781	/* Disable ERR interrupt */
mbed_official	340:28d1f895c6fe	1782	tmpisr \|= SMBUS_IT_ERRI;
mbed_official	340:28d1f895c6fe	1783	}
mbed_official	340:28d1f895c6fe	1784
mbed_official	340:28d1f895c6fe	1785	if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
mbed_official	340:28d1f895c6fe	1786	{
mbed_official	340:28d1f895c6fe	1787	/* Disable STOPI, NACKI */
mbed_official	340:28d1f895c6fe	1788	tmpisr \|= SMBUS_IT_STOPI \| SMBUS_IT_NACKI;
mbed_official	340:28d1f895c6fe	1789	}
mbed_official	340:28d1f895c6fe	1790	}
mbed_official	340:28d1f895c6fe	1791
mbed_official	340:28d1f895c6fe	1792	if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
mbed_official	340:28d1f895c6fe	1793	{
mbed_official	340:28d1f895c6fe	1794	/* Disable TC, STOP, NACK, RXI interrupt */
mbed_official	340:28d1f895c6fe	1795	tmpisr \|= SMBUS_IT_TCI \| SMBUS_IT_RXI;
mbed_official	340:28d1f895c6fe	1796
mbed_official	631:825f75ca301e	1797	if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
mbed_official	340:28d1f895c6fe	1798	&& ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
mbed_official	340:28d1f895c6fe	1799	{
mbed_official	340:28d1f895c6fe	1800	/* Disable ERR interrupt */
mbed_official	340:28d1f895c6fe	1801	tmpisr \|= SMBUS_IT_ERRI;
mbed_official	340:28d1f895c6fe	1802	}
mbed_official	340:28d1f895c6fe	1803
mbed_official	340:28d1f895c6fe	1804	if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
mbed_official	340:28d1f895c6fe	1805	{
mbed_official	340:28d1f895c6fe	1806	/* Disable STOPI, NACKI */
mbed_official	340:28d1f895c6fe	1807	tmpisr \|= SMBUS_IT_STOPI \| SMBUS_IT_NACKI;
mbed_official	340:28d1f895c6fe	1808	}
mbed_official	340:28d1f895c6fe	1809	}
mbed_official	340:28d1f895c6fe	1810
mbed_official	340:28d1f895c6fe	1811	if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
mbed_official	340:28d1f895c6fe	1812	{
mbed_official	340:28d1f895c6fe	1813	/* Enable ADDR, STOP interrupt */
mbed_official	340:28d1f895c6fe	1814	tmpisr \|= SMBUS_IT_ADDRI \| SMBUS_IT_STOPI \| SMBUS_IT_NACKI;
mbed_official	340:28d1f895c6fe	1815
mbed_official	631:825f75ca301e	1816	if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
mbed_official	340:28d1f895c6fe	1817	{
mbed_official	340:28d1f895c6fe	1818	/* Disable ERR interrupt */
mbed_official	340:28d1f895c6fe	1819	tmpisr \|= SMBUS_IT_ERRI;
mbed_official	340:28d1f895c6fe	1820	}
mbed_official	340:28d1f895c6fe	1821	}
mbed_official	340:28d1f895c6fe	1822
mbed_official	340:28d1f895c6fe	1823	/* Disable interrupts only at the end */
mbed_official	340:28d1f895c6fe	1824	/* to avoid a breaking situation like at "t" time */
mbed_official	340:28d1f895c6fe	1825	/* all disable interrupts request are not done */
mbed_official	340:28d1f895c6fe	1826	__HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
mbed_official	340:28d1f895c6fe	1827
mbed_official	340:28d1f895c6fe	1828	return HAL_OK;
mbed_official	340:28d1f895c6fe	1829	}
mbed_official	340:28d1f895c6fe	1830	/**
mbed_official	631:825f75ca301e	1831	* @brief Handle SMBUS Communication Timeout.
mbed_official	340:28d1f895c6fe	1832	* @param hsmbus : Pointer to a SMBUS_HandleTypeDef structure that contains
mbed_official	340:28d1f895c6fe	1833	* the configuration information for the specified SMBUS.
mbed_official	340:28d1f895c6fe	1834	* @param Flag: specifies the SMBUS flag to check.
mbed_official	340:28d1f895c6fe	1835	* @param Status: The new Flag status (SET or RESET).
mbed_official	340:28d1f895c6fe	1836	* @param Timeout: Timeout duration
mbed_official	340:28d1f895c6fe	1837	* @retval HAL status
mbed_official	340:28d1f895c6fe	1838	*/
mbed_official	340:28d1f895c6fe	1839	static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
mbed_official	340:28d1f895c6fe	1840	{
mbed_official	340:28d1f895c6fe	1841	uint32_t tickstart = HAL_GetTick();
mbed_official	340:28d1f895c6fe	1842
mbed_official	340:28d1f895c6fe	1843	/* Wait until flag is set */
mbed_official	340:28d1f895c6fe	1844	if(Status == RESET)
mbed_official	340:28d1f895c6fe	1845	{
mbed_official	340:28d1f895c6fe	1846	while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
mbed_official	340:28d1f895c6fe	1847	{
mbed_official	340:28d1f895c6fe	1848	/* Check for the Timeout */
mbed_official	340:28d1f895c6fe	1849	if(Timeout != HAL_MAX_DELAY)
mbed_official	340:28d1f895c6fe	1850	{
mbed_official	340:28d1f895c6fe	1851	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
mbed_official	340:28d1f895c6fe	1852	{
mbed_official	340:28d1f895c6fe	1853	hsmbus->PreviousState = hsmbus->State;
mbed_official	340:28d1f895c6fe	1854	hsmbus->State= HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1855
mbed_official	340:28d1f895c6fe	1856	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1857	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1858
mbed_official	340:28d1f895c6fe	1859	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	1860	}
mbed_official	340:28d1f895c6fe	1861	}
mbed_official	340:28d1f895c6fe	1862	}
mbed_official	340:28d1f895c6fe	1863	}
mbed_official	340:28d1f895c6fe	1864	else
mbed_official	340:28d1f895c6fe	1865	{
mbed_official	340:28d1f895c6fe	1866	while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
mbed_official	340:28d1f895c6fe	1867	{
mbed_official	340:28d1f895c6fe	1868	/* Check for the Timeout */
mbed_official	340:28d1f895c6fe	1869	if(Timeout != HAL_MAX_DELAY)
mbed_official	340:28d1f895c6fe	1870	{
mbed_official	340:28d1f895c6fe	1871	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
mbed_official	340:28d1f895c6fe	1872	{
mbed_official	340:28d1f895c6fe	1873	hsmbus->PreviousState = hsmbus->State;
mbed_official	340:28d1f895c6fe	1874	hsmbus->State= HAL_SMBUS_STATE_READY;
mbed_official	340:28d1f895c6fe	1875
mbed_official	340:28d1f895c6fe	1876	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1877	__HAL_UNLOCK(hsmbus);
mbed_official	340:28d1f895c6fe	1878
mbed_official	340:28d1f895c6fe	1879	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	1880	}
mbed_official	340:28d1f895c6fe	1881	}
mbed_official	340:28d1f895c6fe	1882	}
mbed_official	340:28d1f895c6fe	1883	}
mbed_official	340:28d1f895c6fe	1884	return HAL_OK;
mbed_official	340:28d1f895c6fe	1885	}
mbed_official	340:28d1f895c6fe	1886
mbed_official	340:28d1f895c6fe	1887	/**
mbed_official	631:825f75ca301e	1888	* @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
mbed_official	340:28d1f895c6fe	1889	* @param hsmbus: SMBUS handle.
mbed_official	340:28d1f895c6fe	1890	* @param DevAddress: specifies the slave address to be programmed.
mbed_official	340:28d1f895c6fe	1891	* @param Size: specifies the number of bytes to be programmed.
mbed_official	340:28d1f895c6fe	1892	* This parameter must be a value between 0 and 255.
mbed_official	340:28d1f895c6fe	1893	* @param Mode: new state of the SMBUS START condition generation.
mbed_official	340:28d1f895c6fe	1894	* This parameter can be one or a combination of the following values:
mbed_official	340:28d1f895c6fe	1895	* @arg SMBUS_NO_MODE: No specific mode enabled.
mbed_official	340:28d1f895c6fe	1896	* @arg SMBUS_RELOAD_MODE: Enable Reload mode.
mbed_official	340:28d1f895c6fe	1897	* @arg SMBUS_AUTOEND_MODE: Enable Automatic end mode.
mbed_official	340:28d1f895c6fe	1898	* @arg SMBUS_SOFTEND_MODE: Enable Software end mode and Reload mode.
mbed_official	340:28d1f895c6fe	1899	* @param Request: new state of the SMBUS START condition generation.
mbed_official	340:28d1f895c6fe	1900	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1901	* @arg SMBUS_NO_STARTSTOP: Don't Generate stop and start condition.
mbed_official	340:28d1f895c6fe	1902	* @arg SMBUS_GENERATE_STOP: Generate stop condition (Size should be set to 0).
mbed_official	340:28d1f895c6fe	1903	* @arg SMBUS_GENERATE_START_READ: Generate Restart for read request.
mbed_official	340:28d1f895c6fe	1904	* @arg SMBUS_GENERATE_START_WRITE: Generate Restart for write request.
mbed_official	340:28d1f895c6fe	1905	* @retval None
mbed_official	340:28d1f895c6fe	1906	*/
mbed_official	340:28d1f895c6fe	1907	static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
mbed_official	340:28d1f895c6fe	1908	{
mbed_official	340:28d1f895c6fe	1909	uint32_t tmpreg = 0;
mbed_official	340:28d1f895c6fe	1910
mbed_official	340:28d1f895c6fe	1911	/* Check the parameters */
mbed_official	340:28d1f895c6fe	1912	assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
mbed_official	340:28d1f895c6fe	1913	assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
mbed_official	340:28d1f895c6fe	1914	assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
mbed_official	340:28d1f895c6fe	1915
mbed_official	340:28d1f895c6fe	1916	/* Get the CR2 register value */
mbed_official	340:28d1f895c6fe	1917	tmpreg = hsmbus->Instance->CR2;
mbed_official	340:28d1f895c6fe	1918
mbed_official	340:28d1f895c6fe	1919	/* clear tmpreg specific bits */
mbed_official	340:28d1f895c6fe	1920	tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD \| I2C_CR2_NBYTES \| I2C_CR2_RELOAD \| I2C_CR2_AUTOEND \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP \| I2C_CR2_PECBYTE));
mbed_official	340:28d1f895c6fe	1921
mbed_official	340:28d1f895c6fe	1922	/* update tmpreg */
mbed_official	340:28d1f895c6fe	1923	tmpreg \|= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) \| (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) \| \
mbed_official	340:28d1f895c6fe	1924	(uint32_t)Mode \| (uint32_t)Request);
mbed_official	340:28d1f895c6fe	1925
mbed_official	340:28d1f895c6fe	1926	/* update CR2 register */
mbed_official	340:28d1f895c6fe	1927	hsmbus->Instance->CR2 = tmpreg;
mbed_official	340:28d1f895c6fe	1928	}
mbed_official	340:28d1f895c6fe	1929	/**
mbed_official	340:28d1f895c6fe	1930	* @}
mbed_official	340:28d1f895c6fe	1931	*/
mbed_official	340:28d1f895c6fe	1932
mbed_official	340:28d1f895c6fe	1933	#endif /* HAL_SMBUS_MODULE_ENABLED */
mbed_official	340:28d1f895c6fe	1934	/**
mbed_official	340:28d1f895c6fe	1935	* @}
mbed_official	340:28d1f895c6fe	1936	*/
mbed_official	340:28d1f895c6fe	1937
mbed_official	340:28d1f895c6fe	1938	/**
mbed_official	340:28d1f895c6fe	1939	* @}
mbed_official	340:28d1f895c6fe	1940	*/
mbed_official	340:28d1f895c6fe	1941
mbed_official	340:28d1f895c6fe	1942	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	23 Nov 2016
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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_smbus.c@636:a11c0372f0ba, 2015-09-30 (annotated)

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