Yihui Xiong / Mbed 2 deprecated Seeed_nRF51822_Motion

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Dependencies:   mbed

mbed-src/targets/cmsis/core_cm0.h@0:638edba3adf6, 2016-01-11 (annotated)

Committer:
yihui
Date:
Mon Jan 11 02:32:24 2016 +0000
Revision:
0:638edba3adf6
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yihui 0:638edba3adf6 1 /**************************************************************************//**
yihui 0:638edba3adf6 2 * @file core_cm0.h
yihui 0:638edba3adf6 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
yihui 0:638edba3adf6 4 * @version V3.20
yihui 0:638edba3adf6 5 * @date 25. February 2013
yihui 0:638edba3adf6 6 *
yihui 0:638edba3adf6 7 * @note
yihui 0:638edba3adf6 8 *
yihui 0:638edba3adf6 9 ******************************************************************************/
yihui 0:638edba3adf6 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
yihui 0:638edba3adf6 11
yihui 0:638edba3adf6 12 All rights reserved.
yihui 0:638edba3adf6 13 Redistribution and use in source and binary forms, with or without
yihui 0:638edba3adf6 14 modification, are permitted provided that the following conditions are met:
yihui 0:638edba3adf6 15 - Redistributions of source code must retain the above copyright
yihui 0:638edba3adf6 16 notice, this list of conditions and the following disclaimer.
yihui 0:638edba3adf6 17 - Redistributions in binary form must reproduce the above copyright
yihui 0:638edba3adf6 18 notice, this list of conditions and the following disclaimer in the
yihui 0:638edba3adf6 19 documentation and/or other materials provided with the distribution.
yihui 0:638edba3adf6 20 - Neither the name of ARM nor the names of its contributors may be used
yihui 0:638edba3adf6 21 to endorse or promote products derived from this software without
yihui 0:638edba3adf6 22 specific prior written permission.
yihui 0:638edba3adf6 23 *
yihui 0:638edba3adf6 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
yihui 0:638edba3adf6 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
yihui 0:638edba3adf6 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
yihui 0:638edba3adf6 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
yihui 0:638edba3adf6 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
yihui 0:638edba3adf6 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
yihui 0:638edba3adf6 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
yihui 0:638edba3adf6 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
yihui 0:638edba3adf6 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
yihui 0:638edba3adf6 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
yihui 0:638edba3adf6 34 POSSIBILITY OF SUCH DAMAGE.
yihui 0:638edba3adf6 35 ---------------------------------------------------------------------------*/
yihui 0:638edba3adf6 36
yihui 0:638edba3adf6 37
yihui 0:638edba3adf6 38 #if defined ( __ICCARM__ )
yihui 0:638edba3adf6 39 #pragma system_include /* treat file as system include file for MISRA check */
yihui 0:638edba3adf6 40 #endif
yihui 0:638edba3adf6 41
yihui 0:638edba3adf6 42 #ifdef __cplusplus
yihui 0:638edba3adf6 43 extern "C" {
yihui 0:638edba3adf6 44 #endif
yihui 0:638edba3adf6 45
yihui 0:638edba3adf6 46 #ifndef __CORE_CM0_H_GENERIC
yihui 0:638edba3adf6 47 #define __CORE_CM0_H_GENERIC
yihui 0:638edba3adf6 48
yihui 0:638edba3adf6 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
yihui 0:638edba3adf6 50 CMSIS violates the following MISRA-C:2004 rules:
yihui 0:638edba3adf6 51
yihui 0:638edba3adf6 52 \li Required Rule 8.5, object/function definition in header file.<br>
yihui 0:638edba3adf6 53 Function definitions in header files are used to allow 'inlining'.
yihui 0:638edba3adf6 54
yihui 0:638edba3adf6 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
yihui 0:638edba3adf6 56 Unions are used for effective representation of core registers.
yihui 0:638edba3adf6 57
yihui 0:638edba3adf6 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
yihui 0:638edba3adf6 59 Function-like macros are used to allow more efficient code.
yihui 0:638edba3adf6 60 */
yihui 0:638edba3adf6 61
yihui 0:638edba3adf6 62
yihui 0:638edba3adf6 63 /*******************************************************************************
yihui 0:638edba3adf6 64 * CMSIS definitions
yihui 0:638edba3adf6 65 ******************************************************************************/
yihui 0:638edba3adf6 66 /** \ingroup Cortex_M0
yihui 0:638edba3adf6 67 @{
yihui 0:638edba3adf6 68 */
yihui 0:638edba3adf6 69
yihui 0:638edba3adf6 70 /* CMSIS CM0 definitions */
yihui 0:638edba3adf6 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
yihui 0:638edba3adf6 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
yihui 0:638edba3adf6 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
yihui 0:638edba3adf6 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
yihui 0:638edba3adf6 75
yihui 0:638edba3adf6 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
yihui 0:638edba3adf6 77
yihui 0:638edba3adf6 78
yihui 0:638edba3adf6 79 #if defined ( __CC_ARM )
yihui 0:638edba3adf6 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
yihui 0:638edba3adf6 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
yihui 0:638edba3adf6 82 #define __STATIC_INLINE static __inline
yihui 0:638edba3adf6 83
yihui 0:638edba3adf6 84 #elif defined ( __ICCARM__ )
yihui 0:638edba3adf6 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
yihui 0:638edba3adf6 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
yihui 0:638edba3adf6 87 #define __STATIC_INLINE static inline
yihui 0:638edba3adf6 88
yihui 0:638edba3adf6 89 #elif defined ( __GNUC__ )
yihui 0:638edba3adf6 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
yihui 0:638edba3adf6 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
yihui 0:638edba3adf6 92 #define __STATIC_INLINE static inline
yihui 0:638edba3adf6 93
yihui 0:638edba3adf6 94 #elif defined ( __TASKING__ )
yihui 0:638edba3adf6 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
yihui 0:638edba3adf6 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
yihui 0:638edba3adf6 97 #define __STATIC_INLINE static inline
yihui 0:638edba3adf6 98
yihui 0:638edba3adf6 99 #endif
yihui 0:638edba3adf6 100
yihui 0:638edba3adf6 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
yihui 0:638edba3adf6 102 */
yihui 0:638edba3adf6 103 #define __FPU_USED 0
yihui 0:638edba3adf6 104
yihui 0:638edba3adf6 105 #if defined ( __CC_ARM )
yihui 0:638edba3adf6 106 #if defined __TARGET_FPU_VFP
yihui 0:638edba3adf6 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 0:638edba3adf6 108 #endif
yihui 0:638edba3adf6 109
yihui 0:638edba3adf6 110 #elif defined ( __ICCARM__ )
yihui 0:638edba3adf6 111 #if defined __ARMVFP__
yihui 0:638edba3adf6 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 0:638edba3adf6 113 #endif
yihui 0:638edba3adf6 114
yihui 0:638edba3adf6 115 #elif defined ( __GNUC__ )
yihui 0:638edba3adf6 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
yihui 0:638edba3adf6 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 0:638edba3adf6 118 #endif
yihui 0:638edba3adf6 119
yihui 0:638edba3adf6 120 #elif defined ( __TASKING__ )
yihui 0:638edba3adf6 121 #if defined __FPU_VFP__
yihui 0:638edba3adf6 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui 0:638edba3adf6 123 #endif
yihui 0:638edba3adf6 124 #endif
yihui 0:638edba3adf6 125
yihui 0:638edba3adf6 126 #include <stdint.h> /* standard types definitions */
yihui 0:638edba3adf6 127 #include <core_cmInstr.h> /* Core Instruction Access */
yihui 0:638edba3adf6 128 #include <core_cmFunc.h> /* Core Function Access */
yihui 0:638edba3adf6 129
yihui 0:638edba3adf6 130 #endif /* __CORE_CM0_H_GENERIC */
yihui 0:638edba3adf6 131
yihui 0:638edba3adf6 132 #ifndef __CMSIS_GENERIC
yihui 0:638edba3adf6 133
yihui 0:638edba3adf6 134 #ifndef __CORE_CM0_H_DEPENDANT
yihui 0:638edba3adf6 135 #define __CORE_CM0_H_DEPENDANT
yihui 0:638edba3adf6 136
yihui 0:638edba3adf6 137 /* check device defines and use defaults */
yihui 0:638edba3adf6 138 #if defined __CHECK_DEVICE_DEFINES
yihui 0:638edba3adf6 139 #ifndef __CM0_REV
yihui 0:638edba3adf6 140 #define __CM0_REV 0x0000
yihui 0:638edba3adf6 141 #warning "__CM0_REV not defined in device header file; using default!"
yihui 0:638edba3adf6 142 #endif
yihui 0:638edba3adf6 143
yihui 0:638edba3adf6 144 #ifndef __NVIC_PRIO_BITS
yihui 0:638edba3adf6 145 #define __NVIC_PRIO_BITS 2
yihui 0:638edba3adf6 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
yihui 0:638edba3adf6 147 #endif
yihui 0:638edba3adf6 148
yihui 0:638edba3adf6 149 #ifndef __Vendor_SysTickConfig
yihui 0:638edba3adf6 150 #define __Vendor_SysTickConfig 0
yihui 0:638edba3adf6 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
yihui 0:638edba3adf6 152 #endif
yihui 0:638edba3adf6 153 #endif
yihui 0:638edba3adf6 154
yihui 0:638edba3adf6 155 /* IO definitions (access restrictions to peripheral registers) */
yihui 0:638edba3adf6 156 /**
yihui 0:638edba3adf6 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
yihui 0:638edba3adf6 158
yihui 0:638edba3adf6 159 <strong>IO Type Qualifiers</strong> are used
yihui 0:638edba3adf6 160 \li to specify the access to peripheral variables.
yihui 0:638edba3adf6 161 \li for automatic generation of peripheral register debug information.
yihui 0:638edba3adf6 162 */
yihui 0:638edba3adf6 163 #ifdef __cplusplus
yihui 0:638edba3adf6 164 #define __I volatile /*!< Defines 'read only' permissions */
yihui 0:638edba3adf6 165 #else
yihui 0:638edba3adf6 166 #define __I volatile const /*!< Defines 'read only' permissions */
yihui 0:638edba3adf6 167 #endif
yihui 0:638edba3adf6 168 #define __O volatile /*!< Defines 'write only' permissions */
yihui 0:638edba3adf6 169 #define __IO volatile /*!< Defines 'read / write' permissions */
yihui 0:638edba3adf6 170
yihui 0:638edba3adf6 171 /*@} end of group Cortex_M0 */
yihui 0:638edba3adf6 172
yihui 0:638edba3adf6 173
yihui 0:638edba3adf6 174
yihui 0:638edba3adf6 175 /*******************************************************************************
yihui 0:638edba3adf6 176 * Register Abstraction
yihui 0:638edba3adf6 177 Core Register contain:
yihui 0:638edba3adf6 178 - Core Register
yihui 0:638edba3adf6 179 - Core NVIC Register
yihui 0:638edba3adf6 180 - Core SCB Register
yihui 0:638edba3adf6 181 - Core SysTick Register
yihui 0:638edba3adf6 182 ******************************************************************************/
yihui 0:638edba3adf6 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
yihui 0:638edba3adf6 184 \brief Type definitions and defines for Cortex-M processor based devices.
yihui 0:638edba3adf6 185 */
yihui 0:638edba3adf6 186
yihui 0:638edba3adf6 187 /** \ingroup CMSIS_core_register
yihui 0:638edba3adf6 188 \defgroup CMSIS_CORE Status and Control Registers
yihui 0:638edba3adf6 189 \brief Core Register type definitions.
yihui 0:638edba3adf6 190 @{
yihui 0:638edba3adf6 191 */
yihui 0:638edba3adf6 192
yihui 0:638edba3adf6 193 /** \brief Union type to access the Application Program Status Register (APSR).
yihui 0:638edba3adf6 194 */
yihui 0:638edba3adf6 195 typedef union
yihui 0:638edba3adf6 196 {
yihui 0:638edba3adf6 197 struct
yihui 0:638edba3adf6 198 {
yihui 0:638edba3adf6 199 #if (__CORTEX_M != 0x04)
yihui 0:638edba3adf6 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
yihui 0:638edba3adf6 201 #else
yihui 0:638edba3adf6 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
yihui 0:638edba3adf6 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
yihui 0:638edba3adf6 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
yihui 0:638edba3adf6 205 #endif
yihui 0:638edba3adf6 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
yihui 0:638edba3adf6 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
yihui 0:638edba3adf6 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
yihui 0:638edba3adf6 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
yihui 0:638edba3adf6 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
yihui 0:638edba3adf6 211 } b; /*!< Structure used for bit access */
yihui 0:638edba3adf6 212 uint32_t w; /*!< Type used for word access */
yihui 0:638edba3adf6 213 } APSR_Type;
yihui 0:638edba3adf6 214
yihui 0:638edba3adf6 215
yihui 0:638edba3adf6 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
yihui 0:638edba3adf6 217 */
yihui 0:638edba3adf6 218 typedef union
yihui 0:638edba3adf6 219 {
yihui 0:638edba3adf6 220 struct
yihui 0:638edba3adf6 221 {
yihui 0:638edba3adf6 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
yihui 0:638edba3adf6 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
yihui 0:638edba3adf6 224 } b; /*!< Structure used for bit access */
yihui 0:638edba3adf6 225 uint32_t w; /*!< Type used for word access */
yihui 0:638edba3adf6 226 } IPSR_Type;
yihui 0:638edba3adf6 227
yihui 0:638edba3adf6 228
yihui 0:638edba3adf6 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
yihui 0:638edba3adf6 230 */
yihui 0:638edba3adf6 231 typedef union
yihui 0:638edba3adf6 232 {
yihui 0:638edba3adf6 233 struct
yihui 0:638edba3adf6 234 {
yihui 0:638edba3adf6 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
yihui 0:638edba3adf6 236 #if (__CORTEX_M != 0x04)
yihui 0:638edba3adf6 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
yihui 0:638edba3adf6 238 #else
yihui 0:638edba3adf6 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
yihui 0:638edba3adf6 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
yihui 0:638edba3adf6 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
yihui 0:638edba3adf6 242 #endif
yihui 0:638edba3adf6 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
yihui 0:638edba3adf6 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
yihui 0:638edba3adf6 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
yihui 0:638edba3adf6 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
yihui 0:638edba3adf6 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
yihui 0:638edba3adf6 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
yihui 0:638edba3adf6 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
yihui 0:638edba3adf6 250 } b; /*!< Structure used for bit access */
yihui 0:638edba3adf6 251 uint32_t w; /*!< Type used for word access */
yihui 0:638edba3adf6 252 } xPSR_Type;
yihui 0:638edba3adf6 253
yihui 0:638edba3adf6 254
yihui 0:638edba3adf6 255 /** \brief Union type to access the Control Registers (CONTROL).
yihui 0:638edba3adf6 256 */
yihui 0:638edba3adf6 257 typedef union
yihui 0:638edba3adf6 258 {
yihui 0:638edba3adf6 259 struct
yihui 0:638edba3adf6 260 {
yihui 0:638edba3adf6 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
yihui 0:638edba3adf6 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
yihui 0:638edba3adf6 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
yihui 0:638edba3adf6 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
yihui 0:638edba3adf6 265 } b; /*!< Structure used for bit access */
yihui 0:638edba3adf6 266 uint32_t w; /*!< Type used for word access */
yihui 0:638edba3adf6 267 } CONTROL_Type;
yihui 0:638edba3adf6 268
yihui 0:638edba3adf6 269 /*@} end of group CMSIS_CORE */
yihui 0:638edba3adf6 270
yihui 0:638edba3adf6 271
yihui 0:638edba3adf6 272 /** \ingroup CMSIS_core_register
yihui 0:638edba3adf6 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
yihui 0:638edba3adf6 274 \brief Type definitions for the NVIC Registers
yihui 0:638edba3adf6 275 @{
yihui 0:638edba3adf6 276 */
yihui 0:638edba3adf6 277
yihui 0:638edba3adf6 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
yihui 0:638edba3adf6 279 */
yihui 0:638edba3adf6 280 typedef struct
yihui 0:638edba3adf6 281 {
yihui 0:638edba3adf6 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
yihui 0:638edba3adf6 283 uint32_t RESERVED0[31];
yihui 0:638edba3adf6 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
yihui 0:638edba3adf6 285 uint32_t RSERVED1[31];
yihui 0:638edba3adf6 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
yihui 0:638edba3adf6 287 uint32_t RESERVED2[31];
yihui 0:638edba3adf6 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
yihui 0:638edba3adf6 289 uint32_t RESERVED3[31];
yihui 0:638edba3adf6 290 uint32_t RESERVED4[64];
yihui 0:638edba3adf6 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
yihui 0:638edba3adf6 292 } NVIC_Type;
yihui 0:638edba3adf6 293
yihui 0:638edba3adf6 294 /*@} end of group CMSIS_NVIC */
yihui 0:638edba3adf6 295
yihui 0:638edba3adf6 296
yihui 0:638edba3adf6 297 /** \ingroup CMSIS_core_register
yihui 0:638edba3adf6 298 \defgroup CMSIS_SCB System Control Block (SCB)
yihui 0:638edba3adf6 299 \brief Type definitions for the System Control Block Registers
yihui 0:638edba3adf6 300 @{
yihui 0:638edba3adf6 301 */
yihui 0:638edba3adf6 302
yihui 0:638edba3adf6 303 /** \brief Structure type to access the System Control Block (SCB).
yihui 0:638edba3adf6 304 */
yihui 0:638edba3adf6 305 typedef struct
yihui 0:638edba3adf6 306 {
yihui 0:638edba3adf6 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
yihui 0:638edba3adf6 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
yihui 0:638edba3adf6 309 uint32_t RESERVED0;
yihui 0:638edba3adf6 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
yihui 0:638edba3adf6 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
yihui 0:638edba3adf6 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
yihui 0:638edba3adf6 313 uint32_t RESERVED1;
yihui 0:638edba3adf6 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
yihui 0:638edba3adf6 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
yihui 0:638edba3adf6 316 } SCB_Type;
yihui 0:638edba3adf6 317
yihui 0:638edba3adf6 318 /* SCB CPUID Register Definitions */
yihui 0:638edba3adf6 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
yihui 0:638edba3adf6 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
yihui 0:638edba3adf6 321
yihui 0:638edba3adf6 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
yihui 0:638edba3adf6 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
yihui 0:638edba3adf6 324
yihui 0:638edba3adf6 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
yihui 0:638edba3adf6 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
yihui 0:638edba3adf6 327
yihui 0:638edba3adf6 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
yihui 0:638edba3adf6 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
yihui 0:638edba3adf6 330
yihui 0:638edba3adf6 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
yihui 0:638edba3adf6 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
yihui 0:638edba3adf6 333
yihui 0:638edba3adf6 334 /* SCB Interrupt Control State Register Definitions */
yihui 0:638edba3adf6 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
yihui 0:638edba3adf6 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
yihui 0:638edba3adf6 337
yihui 0:638edba3adf6 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
yihui 0:638edba3adf6 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
yihui 0:638edba3adf6 340
yihui 0:638edba3adf6 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
yihui 0:638edba3adf6 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
yihui 0:638edba3adf6 343
yihui 0:638edba3adf6 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
yihui 0:638edba3adf6 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
yihui 0:638edba3adf6 346
yihui 0:638edba3adf6 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
yihui 0:638edba3adf6 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
yihui 0:638edba3adf6 349
yihui 0:638edba3adf6 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
yihui 0:638edba3adf6 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
yihui 0:638edba3adf6 352
yihui 0:638edba3adf6 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
yihui 0:638edba3adf6 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
yihui 0:638edba3adf6 355
yihui 0:638edba3adf6 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
yihui 0:638edba3adf6 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
yihui 0:638edba3adf6 358
yihui 0:638edba3adf6 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
yihui 0:638edba3adf6 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
yihui 0:638edba3adf6 361
yihui 0:638edba3adf6 362 /* SCB Application Interrupt and Reset Control Register Definitions */
yihui 0:638edba3adf6 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
yihui 0:638edba3adf6 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
yihui 0:638edba3adf6 365
yihui 0:638edba3adf6 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
yihui 0:638edba3adf6 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
yihui 0:638edba3adf6 368
yihui 0:638edba3adf6 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
yihui 0:638edba3adf6 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
yihui 0:638edba3adf6 371
yihui 0:638edba3adf6 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
yihui 0:638edba3adf6 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
yihui 0:638edba3adf6 374
yihui 0:638edba3adf6 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
yihui 0:638edba3adf6 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
yihui 0:638edba3adf6 377
yihui 0:638edba3adf6 378 /* SCB System Control Register Definitions */
yihui 0:638edba3adf6 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
yihui 0:638edba3adf6 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
yihui 0:638edba3adf6 381
yihui 0:638edba3adf6 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
yihui 0:638edba3adf6 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
yihui 0:638edba3adf6 384
yihui 0:638edba3adf6 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
yihui 0:638edba3adf6 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
yihui 0:638edba3adf6 387
yihui 0:638edba3adf6 388 /* SCB Configuration Control Register Definitions */
yihui 0:638edba3adf6 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
yihui 0:638edba3adf6 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
yihui 0:638edba3adf6 391
yihui 0:638edba3adf6 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
yihui 0:638edba3adf6 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
yihui 0:638edba3adf6 394
yihui 0:638edba3adf6 395 /* SCB System Handler Control and State Register Definitions */
yihui 0:638edba3adf6 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
yihui 0:638edba3adf6 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
yihui 0:638edba3adf6 398
yihui 0:638edba3adf6 399 /*@} end of group CMSIS_SCB */
yihui 0:638edba3adf6 400
yihui 0:638edba3adf6 401
yihui 0:638edba3adf6 402 /** \ingroup CMSIS_core_register
yihui 0:638edba3adf6 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
yihui 0:638edba3adf6 404 \brief Type definitions for the System Timer Registers.
yihui 0:638edba3adf6 405 @{
yihui 0:638edba3adf6 406 */
yihui 0:638edba3adf6 407
yihui 0:638edba3adf6 408 /** \brief Structure type to access the System Timer (SysTick).
yihui 0:638edba3adf6 409 */
yihui 0:638edba3adf6 410 typedef struct
yihui 0:638edba3adf6 411 {
yihui 0:638edba3adf6 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
yihui 0:638edba3adf6 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
yihui 0:638edba3adf6 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
yihui 0:638edba3adf6 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
yihui 0:638edba3adf6 416 } SysTick_Type;
yihui 0:638edba3adf6 417
yihui 0:638edba3adf6 418 /* SysTick Control / Status Register Definitions */
yihui 0:638edba3adf6 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
yihui 0:638edba3adf6 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
yihui 0:638edba3adf6 421
yihui 0:638edba3adf6 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
yihui 0:638edba3adf6 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
yihui 0:638edba3adf6 424
yihui 0:638edba3adf6 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
yihui 0:638edba3adf6 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
yihui 0:638edba3adf6 427
yihui 0:638edba3adf6 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
yihui 0:638edba3adf6 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
yihui 0:638edba3adf6 430
yihui 0:638edba3adf6 431 /* SysTick Reload Register Definitions */
yihui 0:638edba3adf6 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
yihui 0:638edba3adf6 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
yihui 0:638edba3adf6 434
yihui 0:638edba3adf6 435 /* SysTick Current Register Definitions */
yihui 0:638edba3adf6 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
yihui 0:638edba3adf6 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
yihui 0:638edba3adf6 438
yihui 0:638edba3adf6 439 /* SysTick Calibration Register Definitions */
yihui 0:638edba3adf6 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
yihui 0:638edba3adf6 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
yihui 0:638edba3adf6 442
yihui 0:638edba3adf6 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
yihui 0:638edba3adf6 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
yihui 0:638edba3adf6 445
yihui 0:638edba3adf6 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
yihui 0:638edba3adf6 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
yihui 0:638edba3adf6 448
yihui 0:638edba3adf6 449 /*@} end of group CMSIS_SysTick */
yihui 0:638edba3adf6 450
yihui 0:638edba3adf6 451
yihui 0:638edba3adf6 452 /** \ingroup CMSIS_core_register
yihui 0:638edba3adf6 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
yihui 0:638edba3adf6 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
yihui 0:638edba3adf6 455 are only accessible over DAP and not via processor. Therefore
yihui 0:638edba3adf6 456 they are not covered by the Cortex-M0 header file.
yihui 0:638edba3adf6 457 @{
yihui 0:638edba3adf6 458 */
yihui 0:638edba3adf6 459 /*@} end of group CMSIS_CoreDebug */
yihui 0:638edba3adf6 460
yihui 0:638edba3adf6 461
yihui 0:638edba3adf6 462 /** \ingroup CMSIS_core_register
yihui 0:638edba3adf6 463 \defgroup CMSIS_core_base Core Definitions
yihui 0:638edba3adf6 464 \brief Definitions for base addresses, unions, and structures.
yihui 0:638edba3adf6 465 @{
yihui 0:638edba3adf6 466 */
yihui 0:638edba3adf6 467
yihui 0:638edba3adf6 468 /* Memory mapping of Cortex-M0 Hardware */
yihui 0:638edba3adf6 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
yihui 0:638edba3adf6 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
yihui 0:638edba3adf6 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
yihui 0:638edba3adf6 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
yihui 0:638edba3adf6 473
yihui 0:638edba3adf6 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
yihui 0:638edba3adf6 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
yihui 0:638edba3adf6 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
yihui 0:638edba3adf6 477
yihui 0:638edba3adf6 478
yihui 0:638edba3adf6 479 /*@} */
yihui 0:638edba3adf6 480
yihui 0:638edba3adf6 481
yihui 0:638edba3adf6 482
yihui 0:638edba3adf6 483 /*******************************************************************************
yihui 0:638edba3adf6 484 * Hardware Abstraction Layer
yihui 0:638edba3adf6 485 Core Function Interface contains:
yihui 0:638edba3adf6 486 - Core NVIC Functions
yihui 0:638edba3adf6 487 - Core SysTick Functions
yihui 0:638edba3adf6 488 - Core Register Access Functions
yihui 0:638edba3adf6 489 ******************************************************************************/
yihui 0:638edba3adf6 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
yihui 0:638edba3adf6 491 */
yihui 0:638edba3adf6 492
yihui 0:638edba3adf6 493
yihui 0:638edba3adf6 494
yihui 0:638edba3adf6 495 /* ########################## NVIC functions #################################### */
yihui 0:638edba3adf6 496 /** \ingroup CMSIS_Core_FunctionInterface
yihui 0:638edba3adf6 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
yihui 0:638edba3adf6 498 \brief Functions that manage interrupts and exceptions via the NVIC.
yihui 0:638edba3adf6 499 @{
yihui 0:638edba3adf6 500 */
yihui 0:638edba3adf6 501
yihui 0:638edba3adf6 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
yihui 0:638edba3adf6 503 /* The following MACROS handle generation of the register offset and byte masks */
yihui 0:638edba3adf6 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
yihui 0:638edba3adf6 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
yihui 0:638edba3adf6 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
yihui 0:638edba3adf6 507
yihui 0:638edba3adf6 508
yihui 0:638edba3adf6 509 /** \brief Enable External Interrupt
yihui 0:638edba3adf6 510
yihui 0:638edba3adf6 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
yihui 0:638edba3adf6 512
yihui 0:638edba3adf6 513 \param [in] IRQn External interrupt number. Value cannot be negative.
yihui 0:638edba3adf6 514 */
yihui 0:638edba3adf6 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
yihui 0:638edba3adf6 516 {
yihui 0:638edba3adf6 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
yihui 0:638edba3adf6 518 }
yihui 0:638edba3adf6 519
yihui 0:638edba3adf6 520
yihui 0:638edba3adf6 521 /** \brief Disable External Interrupt
yihui 0:638edba3adf6 522
yihui 0:638edba3adf6 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
yihui 0:638edba3adf6 524
yihui 0:638edba3adf6 525 \param [in] IRQn External interrupt number. Value cannot be negative.
yihui 0:638edba3adf6 526 */
yihui 0:638edba3adf6 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
yihui 0:638edba3adf6 528 {
yihui 0:638edba3adf6 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
yihui 0:638edba3adf6 530 }
yihui 0:638edba3adf6 531
yihui 0:638edba3adf6 532
yihui 0:638edba3adf6 533 /** \brief Get Pending Interrupt
yihui 0:638edba3adf6 534
yihui 0:638edba3adf6 535 The function reads the pending register in the NVIC and returns the pending bit
yihui 0:638edba3adf6 536 for the specified interrupt.
yihui 0:638edba3adf6 537
yihui 0:638edba3adf6 538 \param [in] IRQn Interrupt number.
yihui 0:638edba3adf6 539
yihui 0:638edba3adf6 540 \return 0 Interrupt status is not pending.
yihui 0:638edba3adf6 541 \return 1 Interrupt status is pending.
yihui 0:638edba3adf6 542 */
yihui 0:638edba3adf6 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
yihui 0:638edba3adf6 544 {
yihui 0:638edba3adf6 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
yihui 0:638edba3adf6 546 }
yihui 0:638edba3adf6 547
yihui 0:638edba3adf6 548
yihui 0:638edba3adf6 549 /** \brief Set Pending Interrupt
yihui 0:638edba3adf6 550
yihui 0:638edba3adf6 551 The function sets the pending bit of an external interrupt.
yihui 0:638edba3adf6 552
yihui 0:638edba3adf6 553 \param [in] IRQn Interrupt number. Value cannot be negative.
yihui 0:638edba3adf6 554 */
yihui 0:638edba3adf6 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
yihui 0:638edba3adf6 556 {
yihui 0:638edba3adf6 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
yihui 0:638edba3adf6 558 }
yihui 0:638edba3adf6 559
yihui 0:638edba3adf6 560
yihui 0:638edba3adf6 561 /** \brief Clear Pending Interrupt
yihui 0:638edba3adf6 562
yihui 0:638edba3adf6 563 The function clears the pending bit of an external interrupt.
yihui 0:638edba3adf6 564
yihui 0:638edba3adf6 565 \param [in] IRQn External interrupt number. Value cannot be negative.
yihui 0:638edba3adf6 566 */
yihui 0:638edba3adf6 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
yihui 0:638edba3adf6 568 {
yihui 0:638edba3adf6 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
yihui 0:638edba3adf6 570 }
yihui 0:638edba3adf6 571
yihui 0:638edba3adf6 572
yihui 0:638edba3adf6 573 /** \brief Set Interrupt Priority
yihui 0:638edba3adf6 574
yihui 0:638edba3adf6 575 The function sets the priority of an interrupt.
yihui 0:638edba3adf6 576
yihui 0:638edba3adf6 577 \note The priority cannot be set for every core interrupt.
yihui 0:638edba3adf6 578
yihui 0:638edba3adf6 579 \param [in] IRQn Interrupt number.
yihui 0:638edba3adf6 580 \param [in] priority Priority to set.
yihui 0:638edba3adf6 581 */
yihui 0:638edba3adf6 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
yihui 0:638edba3adf6 583 {
yihui 0:638edba3adf6 584 if(IRQn < 0) {
yihui 0:638edba3adf6 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
yihui 0:638edba3adf6 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
yihui 0:638edba3adf6 587 else {
yihui 0:638edba3adf6 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
yihui 0:638edba3adf6 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
yihui 0:638edba3adf6 590 }
yihui 0:638edba3adf6 591
yihui 0:638edba3adf6 592
yihui 0:638edba3adf6 593 /** \brief Get Interrupt Priority
yihui 0:638edba3adf6 594
yihui 0:638edba3adf6 595 The function reads the priority of an interrupt. The interrupt
yihui 0:638edba3adf6 596 number can be positive to specify an external (device specific)
yihui 0:638edba3adf6 597 interrupt, or negative to specify an internal (core) interrupt.
yihui 0:638edba3adf6 598
yihui 0:638edba3adf6 599
yihui 0:638edba3adf6 600 \param [in] IRQn Interrupt number.
yihui 0:638edba3adf6 601 \return Interrupt Priority. Value is aligned automatically to the implemented
yihui 0:638edba3adf6 602 priority bits of the microcontroller.
yihui 0:638edba3adf6 603 */
yihui 0:638edba3adf6 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
yihui 0:638edba3adf6 605 {
yihui 0:638edba3adf6 606
yihui 0:638edba3adf6 607 if(IRQn < 0) {
yihui 0:638edba3adf6 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
yihui 0:638edba3adf6 609 else {
yihui 0:638edba3adf6 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
yihui 0:638edba3adf6 611 }
yihui 0:638edba3adf6 612
yihui 0:638edba3adf6 613
yihui 0:638edba3adf6 614 /** \brief System Reset
yihui 0:638edba3adf6 615
yihui 0:638edba3adf6 616 The function initiates a system reset request to reset the MCU.
yihui 0:638edba3adf6 617 */
yihui 0:638edba3adf6 618 __STATIC_INLINE void NVIC_SystemReset(void)
yihui 0:638edba3adf6 619 {
yihui 0:638edba3adf6 620 __DSB(); /* Ensure all outstanding memory accesses included
yihui 0:638edba3adf6 621 buffered write are completed before reset */
yihui 0:638edba3adf6 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
yihui 0:638edba3adf6 623 SCB_AIRCR_SYSRESETREQ_Msk);
yihui 0:638edba3adf6 624 __DSB(); /* Ensure completion of memory access */
yihui 0:638edba3adf6 625 while(1); /* wait until reset */
yihui 0:638edba3adf6 626 }
yihui 0:638edba3adf6 627
yihui 0:638edba3adf6 628 /*@} end of CMSIS_Core_NVICFunctions */
yihui 0:638edba3adf6 629
yihui 0:638edba3adf6 630
yihui 0:638edba3adf6 631
yihui 0:638edba3adf6 632 /* ################################## SysTick function ############################################ */
yihui 0:638edba3adf6 633 /** \ingroup CMSIS_Core_FunctionInterface
yihui 0:638edba3adf6 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
yihui 0:638edba3adf6 635 \brief Functions that configure the System.
yihui 0:638edba3adf6 636 @{
yihui 0:638edba3adf6 637 */
yihui 0:638edba3adf6 638
yihui 0:638edba3adf6 639 #if (__Vendor_SysTickConfig == 0)
yihui 0:638edba3adf6 640
yihui 0:638edba3adf6 641 /** \brief System Tick Configuration
yihui 0:638edba3adf6 642
yihui 0:638edba3adf6 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
yihui 0:638edba3adf6 644 Counter is in free running mode to generate periodic interrupts.
yihui 0:638edba3adf6 645
yihui 0:638edba3adf6 646 \param [in] ticks Number of ticks between two interrupts.
yihui 0:638edba3adf6 647
yihui 0:638edba3adf6 648 \return 0 Function succeeded.
yihui 0:638edba3adf6 649 \return 1 Function failed.
yihui 0:638edba3adf6 650
yihui 0:638edba3adf6 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
yihui 0:638edba3adf6 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
yihui 0:638edba3adf6 653 must contain a vendor-specific implementation of this function.
yihui 0:638edba3adf6 654
yihui 0:638edba3adf6 655 */
yihui 0:638edba3adf6 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
yihui 0:638edba3adf6 657 {
yihui 0:638edba3adf6 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
yihui 0:638edba3adf6 659
yihui 0:638edba3adf6 660 SysTick->LOAD = ticks - 1; /* set reload register */
yihui 0:638edba3adf6 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
yihui 0:638edba3adf6 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
yihui 0:638edba3adf6 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
yihui 0:638edba3adf6 664 SysTick_CTRL_TICKINT_Msk |
yihui 0:638edba3adf6 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
yihui 0:638edba3adf6 666 return (0); /* Function successful */
yihui 0:638edba3adf6 667 }
yihui 0:638edba3adf6 668
yihui 0:638edba3adf6 669 #endif
yihui 0:638edba3adf6 670
yihui 0:638edba3adf6 671 /*@} end of CMSIS_Core_SysTickFunctions */
yihui 0:638edba3adf6 672
yihui 0:638edba3adf6 673
yihui 0:638edba3adf6 674
yihui 0:638edba3adf6 675
yihui 0:638edba3adf6 676 #endif /* __CORE_CM0_H_DEPENDANT */
yihui 0:638edba3adf6 677
yihui 0:638edba3adf6 678 #endif /* __CMSIS_GENERIC */
yihui 0:638edba3adf6 679
yihui 0:638edba3adf6 680 #ifdef __cplusplus
yihui 0:638edba3adf6 681 }
yihui 0:638edba3adf6 682 #endif