Seeed_nRF51822_MPU9250 - Use MPU9250 with nRF51822

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Use MPU9250 with nRF51822

Fork of Seeed_Tiny_BLE_Flash by Darren Huang

mbed-src/targets/cmsis/core_cm7.h@5:9b240c1d5251, 2015-12-10 (annotated)

Committer:: yihui
Date:: Thu Dec 10 08:00:18 2015 +0000
Revision:: 5:9b240c1d5251

get 9dof data from mpu9250

Who changed what in which revision?

User	Revision	Line number	New contents of line
yihui	5:9b240c1d5251	1	/************************************************************************//
yihui	5:9b240c1d5251	2	* @file core_cm7.h
yihui	5:9b240c1d5251	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
yihui	5:9b240c1d5251	4	* @version V4.10
yihui	5:9b240c1d5251	5	* @date 18. March 2015
yihui	5:9b240c1d5251	6	*
yihui	5:9b240c1d5251	7	* @note
yihui	5:9b240c1d5251	8	*
yihui	5:9b240c1d5251	9	******************************************************************************/
yihui	5:9b240c1d5251	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
yihui	5:9b240c1d5251	11
yihui	5:9b240c1d5251	12	All rights reserved.
yihui	5:9b240c1d5251	13	Redistribution and use in source and binary forms, with or without
yihui	5:9b240c1d5251	14	modification, are permitted provided that the following conditions are met:
yihui	5:9b240c1d5251	15	- Redistributions of source code must retain the above copyright
yihui	5:9b240c1d5251	16	notice, this list of conditions and the following disclaimer.
yihui	5:9b240c1d5251	17	- Redistributions in binary form must reproduce the above copyright
yihui	5:9b240c1d5251	18	notice, this list of conditions and the following disclaimer in the
yihui	5:9b240c1d5251	19	documentation and/or other materials provided with the distribution.
yihui	5:9b240c1d5251	20	- Neither the name of ARM nor the names of its contributors may be used
yihui	5:9b240c1d5251	21	to endorse or promote products derived from this software without
yihui	5:9b240c1d5251	22	specific prior written permission.
yihui	5:9b240c1d5251	23	*
yihui	5:9b240c1d5251	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
yihui	5:9b240c1d5251	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
yihui	5:9b240c1d5251	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
yihui	5:9b240c1d5251	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
yihui	5:9b240c1d5251	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
yihui	5:9b240c1d5251	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
yihui	5:9b240c1d5251	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
yihui	5:9b240c1d5251	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
yihui	5:9b240c1d5251	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
yihui	5:9b240c1d5251	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
yihui	5:9b240c1d5251	34	POSSIBILITY OF SUCH DAMAGE.
yihui	5:9b240c1d5251	35	---------------------------------------------------------------------------*/
yihui	5:9b240c1d5251	36
yihui	5:9b240c1d5251	37
yihui	5:9b240c1d5251	38	#if defined ( __ICCARM__ )
yihui	5:9b240c1d5251	39	#pragma system_include /* treat file as system include file for MISRA check */
yihui	5:9b240c1d5251	40	#endif
yihui	5:9b240c1d5251	41
yihui	5:9b240c1d5251	42	#ifndef __CORE_CM7_H_GENERIC
yihui	5:9b240c1d5251	43	#define __CORE_CM7_H_GENERIC
yihui	5:9b240c1d5251	44
yihui	5:9b240c1d5251	45	#ifdef __cplusplus
yihui	5:9b240c1d5251	46	extern "C" {
yihui	5:9b240c1d5251	47	#endif
yihui	5:9b240c1d5251	48
yihui	5:9b240c1d5251	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
yihui	5:9b240c1d5251	50	CMSIS violates the following MISRA-C:2004 rules:
yihui	5:9b240c1d5251	51
yihui	5:9b240c1d5251	52	\li Required Rule 8.5, object/function definition in header file.<br>
yihui	5:9b240c1d5251	53	Function definitions in header files are used to allow 'inlining'.
yihui	5:9b240c1d5251	54
yihui	5:9b240c1d5251	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
yihui	5:9b240c1d5251	56	Unions are used for effective representation of core registers.
yihui	5:9b240c1d5251	57
yihui	5:9b240c1d5251	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
yihui	5:9b240c1d5251	59	Function-like macros are used to allow more efficient code.
yihui	5:9b240c1d5251	60	*/
yihui	5:9b240c1d5251	61
yihui	5:9b240c1d5251	62
yihui	5:9b240c1d5251	63	/*******************************************************************************
yihui	5:9b240c1d5251	64	* CMSIS definitions
yihui	5:9b240c1d5251	65	******************************************************************************/
yihui	5:9b240c1d5251	66	/** \ingroup Cortex_M7
yihui	5:9b240c1d5251	67	@{
yihui	5:9b240c1d5251	68	*/
yihui	5:9b240c1d5251	69
yihui	5:9b240c1d5251	70	/* CMSIS CM7 definitions */
yihui	5:9b240c1d5251	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
yihui	5:9b240c1d5251	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
yihui	5:9b240c1d5251	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
yihui	5:9b240c1d5251	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
yihui	5:9b240c1d5251	75
yihui	5:9b240c1d5251	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
yihui	5:9b240c1d5251	77
yihui	5:9b240c1d5251	78
yihui	5:9b240c1d5251	79	#if defined ( __CC_ARM )
yihui	5:9b240c1d5251	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
yihui	5:9b240c1d5251	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
yihui	5:9b240c1d5251	82	#define __STATIC_INLINE static __inline
yihui	5:9b240c1d5251	83
yihui	5:9b240c1d5251	84	#elif defined ( __GNUC__ )
yihui	5:9b240c1d5251	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
yihui	5:9b240c1d5251	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
yihui	5:9b240c1d5251	87	#define __STATIC_INLINE static inline
yihui	5:9b240c1d5251	88
yihui	5:9b240c1d5251	89	#elif defined ( __ICCARM__ )
yihui	5:9b240c1d5251	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
yihui	5:9b240c1d5251	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
yihui	5:9b240c1d5251	92	#define __STATIC_INLINE static inline
yihui	5:9b240c1d5251	93
yihui	5:9b240c1d5251	94	#elif defined ( __TMS470__ )
yihui	5:9b240c1d5251	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
yihui	5:9b240c1d5251	96	#define __STATIC_INLINE static inline
yihui	5:9b240c1d5251	97
yihui	5:9b240c1d5251	98	#elif defined ( __TASKING__ )
yihui	5:9b240c1d5251	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
yihui	5:9b240c1d5251	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
yihui	5:9b240c1d5251	101	#define __STATIC_INLINE static inline
yihui	5:9b240c1d5251	102
yihui	5:9b240c1d5251	103	#elif defined ( __CSMC__ )
yihui	5:9b240c1d5251	104	#define __packed
yihui	5:9b240c1d5251	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
yihui	5:9b240c1d5251	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
yihui	5:9b240c1d5251	107	#define __STATIC_INLINE static inline
yihui	5:9b240c1d5251	108
yihui	5:9b240c1d5251	109	#endif
yihui	5:9b240c1d5251	110
yihui	5:9b240c1d5251	111	/** __FPU_USED indicates whether an FPU is used or not.
yihui	5:9b240c1d5251	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
yihui	5:9b240c1d5251	113	*/
yihui	5:9b240c1d5251	114	#if defined ( __CC_ARM )
yihui	5:9b240c1d5251	115	#if defined __TARGET_FPU_VFP
yihui	5:9b240c1d5251	116	#if (__FPU_PRESENT == 1)
yihui	5:9b240c1d5251	117	#define __FPU_USED 1
yihui	5:9b240c1d5251	118	#else
yihui	5:9b240c1d5251	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui	5:9b240c1d5251	120	#define __FPU_USED 0
yihui	5:9b240c1d5251	121	#endif
yihui	5:9b240c1d5251	122	#else
yihui	5:9b240c1d5251	123	#define __FPU_USED 0
yihui	5:9b240c1d5251	124	#endif
yihui	5:9b240c1d5251	125
yihui	5:9b240c1d5251	126	#elif defined ( __GNUC__ )
yihui	5:9b240c1d5251	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
yihui	5:9b240c1d5251	128	#if (__FPU_PRESENT == 1)
yihui	5:9b240c1d5251	129	#define __FPU_USED 1
yihui	5:9b240c1d5251	130	#else
yihui	5:9b240c1d5251	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui	5:9b240c1d5251	132	#define __FPU_USED 0
yihui	5:9b240c1d5251	133	#endif
yihui	5:9b240c1d5251	134	#else
yihui	5:9b240c1d5251	135	#define __FPU_USED 0
yihui	5:9b240c1d5251	136	#endif
yihui	5:9b240c1d5251	137
yihui	5:9b240c1d5251	138	#elif defined ( __ICCARM__ )
yihui	5:9b240c1d5251	139	#if defined __ARMVFP__
yihui	5:9b240c1d5251	140	#if (__FPU_PRESENT == 1)
yihui	5:9b240c1d5251	141	#define __FPU_USED 1
yihui	5:9b240c1d5251	142	#else
yihui	5:9b240c1d5251	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui	5:9b240c1d5251	144	#define __FPU_USED 0
yihui	5:9b240c1d5251	145	#endif
yihui	5:9b240c1d5251	146	#else
yihui	5:9b240c1d5251	147	#define __FPU_USED 0
yihui	5:9b240c1d5251	148	#endif
yihui	5:9b240c1d5251	149
yihui	5:9b240c1d5251	150	#elif defined ( __TMS470__ )
yihui	5:9b240c1d5251	151	#if defined __TI_VFP_SUPPORT__
yihui	5:9b240c1d5251	152	#if (__FPU_PRESENT == 1)
yihui	5:9b240c1d5251	153	#define __FPU_USED 1
yihui	5:9b240c1d5251	154	#else
yihui	5:9b240c1d5251	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui	5:9b240c1d5251	156	#define __FPU_USED 0
yihui	5:9b240c1d5251	157	#endif
yihui	5:9b240c1d5251	158	#else
yihui	5:9b240c1d5251	159	#define __FPU_USED 0
yihui	5:9b240c1d5251	160	#endif
yihui	5:9b240c1d5251	161
yihui	5:9b240c1d5251	162	#elif defined ( __TASKING__ )
yihui	5:9b240c1d5251	163	#if defined __FPU_VFP__
yihui	5:9b240c1d5251	164	#if (__FPU_PRESENT == 1)
yihui	5:9b240c1d5251	165	#define __FPU_USED 1
yihui	5:9b240c1d5251	166	#else
yihui	5:9b240c1d5251	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui	5:9b240c1d5251	168	#define __FPU_USED 0
yihui	5:9b240c1d5251	169	#endif
yihui	5:9b240c1d5251	170	#else
yihui	5:9b240c1d5251	171	#define __FPU_USED 0
yihui	5:9b240c1d5251	172	#endif
yihui	5:9b240c1d5251	173
yihui	5:9b240c1d5251	174	#elif defined ( __CSMC__ ) /* Cosmic */
yihui	5:9b240c1d5251	175	#if ( __CSMC__ & 0x400) // FPU present for parser
yihui	5:9b240c1d5251	176	#if (__FPU_PRESENT == 1)
yihui	5:9b240c1d5251	177	#define __FPU_USED 1
yihui	5:9b240c1d5251	178	#else
yihui	5:9b240c1d5251	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
yihui	5:9b240c1d5251	180	#define __FPU_USED 0
yihui	5:9b240c1d5251	181	#endif
yihui	5:9b240c1d5251	182	#else
yihui	5:9b240c1d5251	183	#define __FPU_USED 0
yihui	5:9b240c1d5251	184	#endif
yihui	5:9b240c1d5251	185	#endif
yihui	5:9b240c1d5251	186
yihui	5:9b240c1d5251	187	#include <stdint.h> /* standard types definitions */
yihui	5:9b240c1d5251	188	#include <core_cmInstr.h> /* Core Instruction Access */
yihui	5:9b240c1d5251	189	#include <core_cmFunc.h> /* Core Function Access */
yihui	5:9b240c1d5251	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
yihui	5:9b240c1d5251	191
yihui	5:9b240c1d5251	192	#ifdef __cplusplus
yihui	5:9b240c1d5251	193	}
yihui	5:9b240c1d5251	194	#endif
yihui	5:9b240c1d5251	195
yihui	5:9b240c1d5251	196	#endif /* __CORE_CM7_H_GENERIC */
yihui	5:9b240c1d5251	197
yihui	5:9b240c1d5251	198	#ifndef __CMSIS_GENERIC
yihui	5:9b240c1d5251	199
yihui	5:9b240c1d5251	200	#ifndef __CORE_CM7_H_DEPENDANT
yihui	5:9b240c1d5251	201	#define __CORE_CM7_H_DEPENDANT
yihui	5:9b240c1d5251	202
yihui	5:9b240c1d5251	203	#ifdef __cplusplus
yihui	5:9b240c1d5251	204	extern "C" {
yihui	5:9b240c1d5251	205	#endif
yihui	5:9b240c1d5251	206
yihui	5:9b240c1d5251	207	/* check device defines and use defaults */
yihui	5:9b240c1d5251	208	#if defined __CHECK_DEVICE_DEFINES
yihui	5:9b240c1d5251	209	#ifndef __CM7_REV
yihui	5:9b240c1d5251	210	#define __CM7_REV 0x0000
yihui	5:9b240c1d5251	211	#warning "__CM7_REV not defined in device header file; using default!"
yihui	5:9b240c1d5251	212	#endif
yihui	5:9b240c1d5251	213
yihui	5:9b240c1d5251	214	#ifndef __FPU_PRESENT
yihui	5:9b240c1d5251	215	#define __FPU_PRESENT 0
yihui	5:9b240c1d5251	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
yihui	5:9b240c1d5251	217	#endif
yihui	5:9b240c1d5251	218
yihui	5:9b240c1d5251	219	#ifndef __MPU_PRESENT
yihui	5:9b240c1d5251	220	#define __MPU_PRESENT 0
yihui	5:9b240c1d5251	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
yihui	5:9b240c1d5251	222	#endif
yihui	5:9b240c1d5251	223
yihui	5:9b240c1d5251	224	#ifndef __ICACHE_PRESENT
yihui	5:9b240c1d5251	225	#define __ICACHE_PRESENT 0
yihui	5:9b240c1d5251	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
yihui	5:9b240c1d5251	227	#endif
yihui	5:9b240c1d5251	228
yihui	5:9b240c1d5251	229	#ifndef __DCACHE_PRESENT
yihui	5:9b240c1d5251	230	#define __DCACHE_PRESENT 0
yihui	5:9b240c1d5251	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
yihui	5:9b240c1d5251	232	#endif
yihui	5:9b240c1d5251	233
yihui	5:9b240c1d5251	234	#ifndef __DTCM_PRESENT
yihui	5:9b240c1d5251	235	#define __DTCM_PRESENT 0
yihui	5:9b240c1d5251	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
yihui	5:9b240c1d5251	237	#endif
yihui	5:9b240c1d5251	238
yihui	5:9b240c1d5251	239	#ifndef __NVIC_PRIO_BITS
yihui	5:9b240c1d5251	240	#define __NVIC_PRIO_BITS 3
yihui	5:9b240c1d5251	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
yihui	5:9b240c1d5251	242	#endif
yihui	5:9b240c1d5251	243
yihui	5:9b240c1d5251	244	#ifndef __Vendor_SysTickConfig
yihui	5:9b240c1d5251	245	#define __Vendor_SysTickConfig 0
yihui	5:9b240c1d5251	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
yihui	5:9b240c1d5251	247	#endif
yihui	5:9b240c1d5251	248	#endif
yihui	5:9b240c1d5251	249
yihui	5:9b240c1d5251	250	/* IO definitions (access restrictions to peripheral registers) */
yihui	5:9b240c1d5251	251	/**
yihui	5:9b240c1d5251	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
yihui	5:9b240c1d5251	253
yihui	5:9b240c1d5251	254	<strong>IO Type Qualifiers</strong> are used
yihui	5:9b240c1d5251	255	\li to specify the access to peripheral variables.
yihui	5:9b240c1d5251	256	\li for automatic generation of peripheral register debug information.
yihui	5:9b240c1d5251	257	*/
yihui	5:9b240c1d5251	258	#ifdef __cplusplus
yihui	5:9b240c1d5251	259	#define __I volatile /!< Defines 'read only' permissions /
yihui	5:9b240c1d5251	260	#else
yihui	5:9b240c1d5251	261	#define __I volatile const /!< Defines 'read only' permissions /
yihui	5:9b240c1d5251	262	#endif
yihui	5:9b240c1d5251	263	#define __O volatile /!< Defines 'write only' permissions /
yihui	5:9b240c1d5251	264	#define __IO volatile /!< Defines 'read / write' permissions /
yihui	5:9b240c1d5251	265
yihui	5:9b240c1d5251	266	/@} end of group Cortex_M7 /
yihui	5:9b240c1d5251	267
yihui	5:9b240c1d5251	268
yihui	5:9b240c1d5251	269
yihui	5:9b240c1d5251	270	/*******************************************************************************
yihui	5:9b240c1d5251	271	* Register Abstraction
yihui	5:9b240c1d5251	272	Core Register contain:
yihui	5:9b240c1d5251	273	- Core Register
yihui	5:9b240c1d5251	274	- Core NVIC Register
yihui	5:9b240c1d5251	275	- Core SCB Register
yihui	5:9b240c1d5251	276	- Core SysTick Register
yihui	5:9b240c1d5251	277	- Core Debug Register
yihui	5:9b240c1d5251	278	- Core MPU Register
yihui	5:9b240c1d5251	279	- Core FPU Register
yihui	5:9b240c1d5251	280	******************************************************************************/
yihui	5:9b240c1d5251	281	/** \defgroup CMSIS_core_register Defines and Type Definitions
yihui	5:9b240c1d5251	282	\brief Type definitions and defines for Cortex-M processor based devices.
yihui	5:9b240c1d5251	283	*/
yihui	5:9b240c1d5251	284
yihui	5:9b240c1d5251	285	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	286	\defgroup CMSIS_CORE Status and Control Registers
yihui	5:9b240c1d5251	287	\brief Core Register type definitions.
yihui	5:9b240c1d5251	288	@{
yihui	5:9b240c1d5251	289	*/
yihui	5:9b240c1d5251	290
yihui	5:9b240c1d5251	291	/** \brief Union type to access the Application Program Status Register (APSR).
yihui	5:9b240c1d5251	292	*/
yihui	5:9b240c1d5251	293	typedef union
yihui	5:9b240c1d5251	294	{
yihui	5:9b240c1d5251	295	struct
yihui	5:9b240c1d5251	296	{
yihui	5:9b240c1d5251	297	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
yihui	5:9b240c1d5251	298	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
yihui	5:9b240c1d5251	299	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
yihui	5:9b240c1d5251	300	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
yihui	5:9b240c1d5251	301	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
yihui	5:9b240c1d5251	302	uint32_t C:1; /!< bit: 29 Carry condition code flag /
yihui	5:9b240c1d5251	303	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
yihui	5:9b240c1d5251	304	uint32_t N:1; /!< bit: 31 Negative condition code flag /
yihui	5:9b240c1d5251	305	} b; /!< Structure used for bit access /
yihui	5:9b240c1d5251	306	uint32_t w; /!< Type used for word access /
yihui	5:9b240c1d5251	307	} APSR_Type;
yihui	5:9b240c1d5251	308
yihui	5:9b240c1d5251	309	/* APSR Register Definitions */
yihui	5:9b240c1d5251	310	#define APSR_N_Pos 31 /!< APSR: N Position /
yihui	5:9b240c1d5251	311	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
yihui	5:9b240c1d5251	312
yihui	5:9b240c1d5251	313	#define APSR_Z_Pos 30 /!< APSR: Z Position /
yihui	5:9b240c1d5251	314	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
yihui	5:9b240c1d5251	315
yihui	5:9b240c1d5251	316	#define APSR_C_Pos 29 /!< APSR: C Position /
yihui	5:9b240c1d5251	317	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
yihui	5:9b240c1d5251	318
yihui	5:9b240c1d5251	319	#define APSR_V_Pos 28 /!< APSR: V Position /
yihui	5:9b240c1d5251	320	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
yihui	5:9b240c1d5251	321
yihui	5:9b240c1d5251	322	#define APSR_Q_Pos 27 /!< APSR: Q Position /
yihui	5:9b240c1d5251	323	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
yihui	5:9b240c1d5251	324
yihui	5:9b240c1d5251	325	#define APSR_GE_Pos 16 /!< APSR: GE Position /
yihui	5:9b240c1d5251	326	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
yihui	5:9b240c1d5251	327
yihui	5:9b240c1d5251	328
yihui	5:9b240c1d5251	329	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
yihui	5:9b240c1d5251	330	*/
yihui	5:9b240c1d5251	331	typedef union
yihui	5:9b240c1d5251	332	{
yihui	5:9b240c1d5251	333	struct
yihui	5:9b240c1d5251	334	{
yihui	5:9b240c1d5251	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
yihui	5:9b240c1d5251	336	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
yihui	5:9b240c1d5251	337	} b; /!< Structure used for bit access /
yihui	5:9b240c1d5251	338	uint32_t w; /!< Type used for word access /
yihui	5:9b240c1d5251	339	} IPSR_Type;
yihui	5:9b240c1d5251	340
yihui	5:9b240c1d5251	341	/* IPSR Register Definitions */
yihui	5:9b240c1d5251	342	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
yihui	5:9b240c1d5251	343	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
yihui	5:9b240c1d5251	344
yihui	5:9b240c1d5251	345
yihui	5:9b240c1d5251	346	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
yihui	5:9b240c1d5251	347	*/
yihui	5:9b240c1d5251	348	typedef union
yihui	5:9b240c1d5251	349	{
yihui	5:9b240c1d5251	350	struct
yihui	5:9b240c1d5251	351	{
yihui	5:9b240c1d5251	352	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
yihui	5:9b240c1d5251	353	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
yihui	5:9b240c1d5251	354	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
yihui	5:9b240c1d5251	355	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
yihui	5:9b240c1d5251	356	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
yihui	5:9b240c1d5251	357	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
yihui	5:9b240c1d5251	358	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
yihui	5:9b240c1d5251	359	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
yihui	5:9b240c1d5251	360	uint32_t C:1; /!< bit: 29 Carry condition code flag /
yihui	5:9b240c1d5251	361	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
yihui	5:9b240c1d5251	362	uint32_t N:1; /!< bit: 31 Negative condition code flag /
yihui	5:9b240c1d5251	363	} b; /!< Structure used for bit access /
yihui	5:9b240c1d5251	364	uint32_t w; /!< Type used for word access /
yihui	5:9b240c1d5251	365	} xPSR_Type;
yihui	5:9b240c1d5251	366
yihui	5:9b240c1d5251	367	/* xPSR Register Definitions */
yihui	5:9b240c1d5251	368	#define xPSR_N_Pos 31 /!< xPSR: N Position /
yihui	5:9b240c1d5251	369	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
yihui	5:9b240c1d5251	370
yihui	5:9b240c1d5251	371	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
yihui	5:9b240c1d5251	372	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
yihui	5:9b240c1d5251	373
yihui	5:9b240c1d5251	374	#define xPSR_C_Pos 29 /!< xPSR: C Position /
yihui	5:9b240c1d5251	375	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
yihui	5:9b240c1d5251	376
yihui	5:9b240c1d5251	377	#define xPSR_V_Pos 28 /!< xPSR: V Position /
yihui	5:9b240c1d5251	378	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
yihui	5:9b240c1d5251	379
yihui	5:9b240c1d5251	380	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
yihui	5:9b240c1d5251	381	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
yihui	5:9b240c1d5251	382
yihui	5:9b240c1d5251	383	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
yihui	5:9b240c1d5251	384	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
yihui	5:9b240c1d5251	385
yihui	5:9b240c1d5251	386	#define xPSR_T_Pos 24 /!< xPSR: T Position /
yihui	5:9b240c1d5251	387	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
yihui	5:9b240c1d5251	388
yihui	5:9b240c1d5251	389	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
yihui	5:9b240c1d5251	390	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
yihui	5:9b240c1d5251	391
yihui	5:9b240c1d5251	392	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
yihui	5:9b240c1d5251	393	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
yihui	5:9b240c1d5251	394
yihui	5:9b240c1d5251	395
yihui	5:9b240c1d5251	396	/** \brief Union type to access the Control Registers (CONTROL).
yihui	5:9b240c1d5251	397	*/
yihui	5:9b240c1d5251	398	typedef union
yihui	5:9b240c1d5251	399	{
yihui	5:9b240c1d5251	400	struct
yihui	5:9b240c1d5251	401	{
yihui	5:9b240c1d5251	402	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
yihui	5:9b240c1d5251	403	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
yihui	5:9b240c1d5251	404	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
yihui	5:9b240c1d5251	405	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
yihui	5:9b240c1d5251	406	} b; /!< Structure used for bit access /
yihui	5:9b240c1d5251	407	uint32_t w; /!< Type used for word access /
yihui	5:9b240c1d5251	408	} CONTROL_Type;
yihui	5:9b240c1d5251	409
yihui	5:9b240c1d5251	410	/* CONTROL Register Definitions */
yihui	5:9b240c1d5251	411	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
yihui	5:9b240c1d5251	412	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
yihui	5:9b240c1d5251	413
yihui	5:9b240c1d5251	414	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
yihui	5:9b240c1d5251	415	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
yihui	5:9b240c1d5251	416
yihui	5:9b240c1d5251	417	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
yihui	5:9b240c1d5251	418	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
yihui	5:9b240c1d5251	419
yihui	5:9b240c1d5251	420	/@} end of group CMSIS_CORE /
yihui	5:9b240c1d5251	421
yihui	5:9b240c1d5251	422
yihui	5:9b240c1d5251	423	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	424	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
yihui	5:9b240c1d5251	425	\brief Type definitions for the NVIC Registers
yihui	5:9b240c1d5251	426	@{
yihui	5:9b240c1d5251	427	*/
yihui	5:9b240c1d5251	428
yihui	5:9b240c1d5251	429	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
yihui	5:9b240c1d5251	430	*/
yihui	5:9b240c1d5251	431	typedef struct
yihui	5:9b240c1d5251	432	{
yihui	5:9b240c1d5251	433	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
yihui	5:9b240c1d5251	434	uint32_t RESERVED0[24];
yihui	5:9b240c1d5251	435	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
yihui	5:9b240c1d5251	436	uint32_t RSERVED1[24];
yihui	5:9b240c1d5251	437	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
yihui	5:9b240c1d5251	438	uint32_t RESERVED2[24];
yihui	5:9b240c1d5251	439	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
yihui	5:9b240c1d5251	440	uint32_t RESERVED3[24];
yihui	5:9b240c1d5251	441	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
yihui	5:9b240c1d5251	442	uint32_t RESERVED4[56];
yihui	5:9b240c1d5251	443	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
yihui	5:9b240c1d5251	444	uint32_t RESERVED5[644];
yihui	5:9b240c1d5251	445	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
yihui	5:9b240c1d5251	446	} NVIC_Type;
yihui	5:9b240c1d5251	447
yihui	5:9b240c1d5251	448	/* Software Triggered Interrupt Register Definitions */
yihui	5:9b240c1d5251	449	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
yihui	5:9b240c1d5251	450	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
yihui	5:9b240c1d5251	451
yihui	5:9b240c1d5251	452	/@} end of group CMSIS_NVIC /
yihui	5:9b240c1d5251	453
yihui	5:9b240c1d5251	454
yihui	5:9b240c1d5251	455	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	456	\defgroup CMSIS_SCB System Control Block (SCB)
yihui	5:9b240c1d5251	457	\brief Type definitions for the System Control Block Registers
yihui	5:9b240c1d5251	458	@{
yihui	5:9b240c1d5251	459	*/
yihui	5:9b240c1d5251	460
yihui	5:9b240c1d5251	461	/** \brief Structure type to access the System Control Block (SCB).
yihui	5:9b240c1d5251	462	*/
yihui	5:9b240c1d5251	463	typedef struct
yihui	5:9b240c1d5251	464	{
yihui	5:9b240c1d5251	465	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
yihui	5:9b240c1d5251	466	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
yihui	5:9b240c1d5251	467	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
yihui	5:9b240c1d5251	468	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
yihui	5:9b240c1d5251	469	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
yihui	5:9b240c1d5251	470	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
yihui	5:9b240c1d5251	471	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
yihui	5:9b240c1d5251	472	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
yihui	5:9b240c1d5251	473	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
yihui	5:9b240c1d5251	474	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
yihui	5:9b240c1d5251	475	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
yihui	5:9b240c1d5251	476	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
yihui	5:9b240c1d5251	477	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
yihui	5:9b240c1d5251	478	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
yihui	5:9b240c1d5251	479	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
yihui	5:9b240c1d5251	480	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
yihui	5:9b240c1d5251	481	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
yihui	5:9b240c1d5251	482	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
yihui	5:9b240c1d5251	483	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
yihui	5:9b240c1d5251	484	uint32_t RESERVED0[1];
yihui	5:9b240c1d5251	485	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
yihui	5:9b240c1d5251	486	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
yihui	5:9b240c1d5251	487	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
yihui	5:9b240c1d5251	488	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
yihui	5:9b240c1d5251	489	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
yihui	5:9b240c1d5251	490	uint32_t RESERVED3[93];
yihui	5:9b240c1d5251	491	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
yihui	5:9b240c1d5251	492	uint32_t RESERVED4[15];
yihui	5:9b240c1d5251	493	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
yihui	5:9b240c1d5251	494	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
yihui	5:9b240c1d5251	495	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
yihui	5:9b240c1d5251	496	uint32_t RESERVED5[1];
yihui	5:9b240c1d5251	497	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
yihui	5:9b240c1d5251	498	uint32_t RESERVED6[1];
yihui	5:9b240c1d5251	499	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
yihui	5:9b240c1d5251	500	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
yihui	5:9b240c1d5251	501	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
yihui	5:9b240c1d5251	502	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
yihui	5:9b240c1d5251	503	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
yihui	5:9b240c1d5251	504	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
yihui	5:9b240c1d5251	505	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
yihui	5:9b240c1d5251	506	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
yihui	5:9b240c1d5251	507	uint32_t RESERVED7[6];
yihui	5:9b240c1d5251	508	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
yihui	5:9b240c1d5251	509	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
yihui	5:9b240c1d5251	510	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
yihui	5:9b240c1d5251	511	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
yihui	5:9b240c1d5251	512	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
yihui	5:9b240c1d5251	513	uint32_t RESERVED8[1];
yihui	5:9b240c1d5251	514	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
yihui	5:9b240c1d5251	515	} SCB_Type;
yihui	5:9b240c1d5251	516
yihui	5:9b240c1d5251	517	/* SCB CPUID Register Definitions */
yihui	5:9b240c1d5251	518	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
yihui	5:9b240c1d5251	519	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
yihui	5:9b240c1d5251	520
yihui	5:9b240c1d5251	521	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
yihui	5:9b240c1d5251	522	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
yihui	5:9b240c1d5251	523
yihui	5:9b240c1d5251	524	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
yihui	5:9b240c1d5251	525	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
yihui	5:9b240c1d5251	526
yihui	5:9b240c1d5251	527	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
yihui	5:9b240c1d5251	528	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
yihui	5:9b240c1d5251	529
yihui	5:9b240c1d5251	530	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
yihui	5:9b240c1d5251	531	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
yihui	5:9b240c1d5251	532
yihui	5:9b240c1d5251	533	/* SCB Interrupt Control State Register Definitions */
yihui	5:9b240c1d5251	534	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
yihui	5:9b240c1d5251	535	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
yihui	5:9b240c1d5251	536
yihui	5:9b240c1d5251	537	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
yihui	5:9b240c1d5251	538	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
yihui	5:9b240c1d5251	539
yihui	5:9b240c1d5251	540	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
yihui	5:9b240c1d5251	541	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
yihui	5:9b240c1d5251	542
yihui	5:9b240c1d5251	543	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
yihui	5:9b240c1d5251	544	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
yihui	5:9b240c1d5251	545
yihui	5:9b240c1d5251	546	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
yihui	5:9b240c1d5251	547	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
yihui	5:9b240c1d5251	548
yihui	5:9b240c1d5251	549	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
yihui	5:9b240c1d5251	550	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
yihui	5:9b240c1d5251	551
yihui	5:9b240c1d5251	552	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
yihui	5:9b240c1d5251	553	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
yihui	5:9b240c1d5251	554
yihui	5:9b240c1d5251	555	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
yihui	5:9b240c1d5251	556	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
yihui	5:9b240c1d5251	557
yihui	5:9b240c1d5251	558	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
yihui	5:9b240c1d5251	559	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
yihui	5:9b240c1d5251	560
yihui	5:9b240c1d5251	561	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
yihui	5:9b240c1d5251	562	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
yihui	5:9b240c1d5251	563
yihui	5:9b240c1d5251	564	/* SCB Vector Table Offset Register Definitions */
yihui	5:9b240c1d5251	565	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
yihui	5:9b240c1d5251	566	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
yihui	5:9b240c1d5251	567
yihui	5:9b240c1d5251	568	/* SCB Application Interrupt and Reset Control Register Definitions */
yihui	5:9b240c1d5251	569	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
yihui	5:9b240c1d5251	570	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
yihui	5:9b240c1d5251	571
yihui	5:9b240c1d5251	572	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
yihui	5:9b240c1d5251	573	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
yihui	5:9b240c1d5251	574
yihui	5:9b240c1d5251	575	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
yihui	5:9b240c1d5251	576	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
yihui	5:9b240c1d5251	577
yihui	5:9b240c1d5251	578	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
yihui	5:9b240c1d5251	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
yihui	5:9b240c1d5251	580
yihui	5:9b240c1d5251	581	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
yihui	5:9b240c1d5251	582	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
yihui	5:9b240c1d5251	583
yihui	5:9b240c1d5251	584	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
yihui	5:9b240c1d5251	585	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
yihui	5:9b240c1d5251	586
yihui	5:9b240c1d5251	587	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
yihui	5:9b240c1d5251	588	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
yihui	5:9b240c1d5251	589
yihui	5:9b240c1d5251	590	/* SCB System Control Register Definitions */
yihui	5:9b240c1d5251	591	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
yihui	5:9b240c1d5251	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
yihui	5:9b240c1d5251	593
yihui	5:9b240c1d5251	594	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
yihui	5:9b240c1d5251	595	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
yihui	5:9b240c1d5251	596
yihui	5:9b240c1d5251	597	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
yihui	5:9b240c1d5251	598	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
yihui	5:9b240c1d5251	599
yihui	5:9b240c1d5251	600	/* SCB Configuration Control Register Definitions */
yihui	5:9b240c1d5251	601	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
yihui	5:9b240c1d5251	602	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
yihui	5:9b240c1d5251	603
yihui	5:9b240c1d5251	604	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
yihui	5:9b240c1d5251	605	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
yihui	5:9b240c1d5251	606
yihui	5:9b240c1d5251	607	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
yihui	5:9b240c1d5251	608	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
yihui	5:9b240c1d5251	609
yihui	5:9b240c1d5251	610	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
yihui	5:9b240c1d5251	611	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
yihui	5:9b240c1d5251	612
yihui	5:9b240c1d5251	613	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
yihui	5:9b240c1d5251	614	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
yihui	5:9b240c1d5251	615
yihui	5:9b240c1d5251	616	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
yihui	5:9b240c1d5251	617	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
yihui	5:9b240c1d5251	618
yihui	5:9b240c1d5251	619	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
yihui	5:9b240c1d5251	620	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
yihui	5:9b240c1d5251	621
yihui	5:9b240c1d5251	622	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
yihui	5:9b240c1d5251	623	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
yihui	5:9b240c1d5251	624
yihui	5:9b240c1d5251	625	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
yihui	5:9b240c1d5251	626	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
yihui	5:9b240c1d5251	627
yihui	5:9b240c1d5251	628	/* SCB System Handler Control and State Register Definitions */
yihui	5:9b240c1d5251	629	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
yihui	5:9b240c1d5251	630	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
yihui	5:9b240c1d5251	631
yihui	5:9b240c1d5251	632	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
yihui	5:9b240c1d5251	633	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
yihui	5:9b240c1d5251	634
yihui	5:9b240c1d5251	635	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
yihui	5:9b240c1d5251	636	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
yihui	5:9b240c1d5251	637
yihui	5:9b240c1d5251	638	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
yihui	5:9b240c1d5251	639	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
yihui	5:9b240c1d5251	640
yihui	5:9b240c1d5251	641	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
yihui	5:9b240c1d5251	642	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
yihui	5:9b240c1d5251	643
yihui	5:9b240c1d5251	644	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
yihui	5:9b240c1d5251	645	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
yihui	5:9b240c1d5251	646
yihui	5:9b240c1d5251	647	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
yihui	5:9b240c1d5251	648	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
yihui	5:9b240c1d5251	649
yihui	5:9b240c1d5251	650	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
yihui	5:9b240c1d5251	651	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
yihui	5:9b240c1d5251	652
yihui	5:9b240c1d5251	653	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
yihui	5:9b240c1d5251	654	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
yihui	5:9b240c1d5251	655
yihui	5:9b240c1d5251	656	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
yihui	5:9b240c1d5251	657	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
yihui	5:9b240c1d5251	658
yihui	5:9b240c1d5251	659	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
yihui	5:9b240c1d5251	660	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
yihui	5:9b240c1d5251	661
yihui	5:9b240c1d5251	662	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
yihui	5:9b240c1d5251	663	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
yihui	5:9b240c1d5251	664
yihui	5:9b240c1d5251	665	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
yihui	5:9b240c1d5251	666	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
yihui	5:9b240c1d5251	667
yihui	5:9b240c1d5251	668	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
yihui	5:9b240c1d5251	669	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
yihui	5:9b240c1d5251	670
yihui	5:9b240c1d5251	671	/* SCB Configurable Fault Status Registers Definitions */
yihui	5:9b240c1d5251	672	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
yihui	5:9b240c1d5251	673	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
yihui	5:9b240c1d5251	674
yihui	5:9b240c1d5251	675	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
yihui	5:9b240c1d5251	676	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
yihui	5:9b240c1d5251	677
yihui	5:9b240c1d5251	678	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
yihui	5:9b240c1d5251	679	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
yihui	5:9b240c1d5251	680
yihui	5:9b240c1d5251	681	/* SCB Hard Fault Status Registers Definitions */
yihui	5:9b240c1d5251	682	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
yihui	5:9b240c1d5251	683	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
yihui	5:9b240c1d5251	684
yihui	5:9b240c1d5251	685	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
yihui	5:9b240c1d5251	686	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
yihui	5:9b240c1d5251	687
yihui	5:9b240c1d5251	688	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
yihui	5:9b240c1d5251	689	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
yihui	5:9b240c1d5251	690
yihui	5:9b240c1d5251	691	/* SCB Debug Fault Status Register Definitions */
yihui	5:9b240c1d5251	692	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
yihui	5:9b240c1d5251	693	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
yihui	5:9b240c1d5251	694
yihui	5:9b240c1d5251	695	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
yihui	5:9b240c1d5251	696	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
yihui	5:9b240c1d5251	697
yihui	5:9b240c1d5251	698	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
yihui	5:9b240c1d5251	699	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
yihui	5:9b240c1d5251	700
yihui	5:9b240c1d5251	701	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
yihui	5:9b240c1d5251	702	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
yihui	5:9b240c1d5251	703
yihui	5:9b240c1d5251	704	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
yihui	5:9b240c1d5251	705	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
yihui	5:9b240c1d5251	706
yihui	5:9b240c1d5251	707	/* Cache Level ID register */
yihui	5:9b240c1d5251	708	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
yihui	5:9b240c1d5251	709	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
yihui	5:9b240c1d5251	710
yihui	5:9b240c1d5251	711	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
yihui	5:9b240c1d5251	712	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
yihui	5:9b240c1d5251	713
yihui	5:9b240c1d5251	714	/* Cache Type register */
yihui	5:9b240c1d5251	715	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
yihui	5:9b240c1d5251	716	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
yihui	5:9b240c1d5251	717
yihui	5:9b240c1d5251	718	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
yihui	5:9b240c1d5251	719	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
yihui	5:9b240c1d5251	720
yihui	5:9b240c1d5251	721	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
yihui	5:9b240c1d5251	722	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
yihui	5:9b240c1d5251	723
yihui	5:9b240c1d5251	724	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
yihui	5:9b240c1d5251	725	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
yihui	5:9b240c1d5251	726
yihui	5:9b240c1d5251	727	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
yihui	5:9b240c1d5251	728	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
yihui	5:9b240c1d5251	729
yihui	5:9b240c1d5251	730	/* Cache Size ID Register */
yihui	5:9b240c1d5251	731	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
yihui	5:9b240c1d5251	732	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
yihui	5:9b240c1d5251	733
yihui	5:9b240c1d5251	734	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
yihui	5:9b240c1d5251	735	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
yihui	5:9b240c1d5251	736
yihui	5:9b240c1d5251	737	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
yihui	5:9b240c1d5251	738	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
yihui	5:9b240c1d5251	739
yihui	5:9b240c1d5251	740	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
yihui	5:9b240c1d5251	741	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
yihui	5:9b240c1d5251	742
yihui	5:9b240c1d5251	743	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
yihui	5:9b240c1d5251	744	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
yihui	5:9b240c1d5251	745
yihui	5:9b240c1d5251	746	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
yihui	5:9b240c1d5251	747	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
yihui	5:9b240c1d5251	748
yihui	5:9b240c1d5251	749	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
yihui	5:9b240c1d5251	750	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
yihui	5:9b240c1d5251	751
yihui	5:9b240c1d5251	752	/* Cache Size Selection Register */
yihui	5:9b240c1d5251	753	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
yihui	5:9b240c1d5251	754	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
yihui	5:9b240c1d5251	755
yihui	5:9b240c1d5251	756	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
yihui	5:9b240c1d5251	757	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
yihui	5:9b240c1d5251	758
yihui	5:9b240c1d5251	759	/* SCB Software Triggered Interrupt Register */
yihui	5:9b240c1d5251	760	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
yihui	5:9b240c1d5251	761	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
yihui	5:9b240c1d5251	762
yihui	5:9b240c1d5251	763	/* Instruction Tightly-Coupled Memory Control Register*/
yihui	5:9b240c1d5251	764	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
yihui	5:9b240c1d5251	765	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
yihui	5:9b240c1d5251	766
yihui	5:9b240c1d5251	767	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
yihui	5:9b240c1d5251	768	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
yihui	5:9b240c1d5251	769
yihui	5:9b240c1d5251	770	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
yihui	5:9b240c1d5251	771	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
yihui	5:9b240c1d5251	772
yihui	5:9b240c1d5251	773	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
yihui	5:9b240c1d5251	774	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
yihui	5:9b240c1d5251	775
yihui	5:9b240c1d5251	776	/* Data Tightly-Coupled Memory Control Registers */
yihui	5:9b240c1d5251	777	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
yihui	5:9b240c1d5251	778	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
yihui	5:9b240c1d5251	779
yihui	5:9b240c1d5251	780	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
yihui	5:9b240c1d5251	781	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
yihui	5:9b240c1d5251	782
yihui	5:9b240c1d5251	783	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
yihui	5:9b240c1d5251	784	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
yihui	5:9b240c1d5251	785
yihui	5:9b240c1d5251	786	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
yihui	5:9b240c1d5251	787	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
yihui	5:9b240c1d5251	788
yihui	5:9b240c1d5251	789	/* AHBP Control Register */
yihui	5:9b240c1d5251	790	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
yihui	5:9b240c1d5251	791	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
yihui	5:9b240c1d5251	792
yihui	5:9b240c1d5251	793	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
yihui	5:9b240c1d5251	794	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
yihui	5:9b240c1d5251	795
yihui	5:9b240c1d5251	796	/* L1 Cache Control Register */
yihui	5:9b240c1d5251	797	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
yihui	5:9b240c1d5251	798	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
yihui	5:9b240c1d5251	799
yihui	5:9b240c1d5251	800	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
yihui	5:9b240c1d5251	801	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
yihui	5:9b240c1d5251	802
yihui	5:9b240c1d5251	803	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
yihui	5:9b240c1d5251	804	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
yihui	5:9b240c1d5251	805
yihui	5:9b240c1d5251	806	/* AHBS control register */
yihui	5:9b240c1d5251	807	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
yihui	5:9b240c1d5251	808	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
yihui	5:9b240c1d5251	809
yihui	5:9b240c1d5251	810	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
yihui	5:9b240c1d5251	811	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
yihui	5:9b240c1d5251	812
yihui	5:9b240c1d5251	813	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
yihui	5:9b240c1d5251	814	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
yihui	5:9b240c1d5251	815
yihui	5:9b240c1d5251	816	/* Auxiliary Bus Fault Status Register */
yihui	5:9b240c1d5251	817	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
yihui	5:9b240c1d5251	818	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
yihui	5:9b240c1d5251	819
yihui	5:9b240c1d5251	820	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
yihui	5:9b240c1d5251	821	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
yihui	5:9b240c1d5251	822
yihui	5:9b240c1d5251	823	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
yihui	5:9b240c1d5251	824	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
yihui	5:9b240c1d5251	825
yihui	5:9b240c1d5251	826	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
yihui	5:9b240c1d5251	827	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
yihui	5:9b240c1d5251	828
yihui	5:9b240c1d5251	829	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
yihui	5:9b240c1d5251	830	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
yihui	5:9b240c1d5251	831
yihui	5:9b240c1d5251	832	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
yihui	5:9b240c1d5251	833	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
yihui	5:9b240c1d5251	834
yihui	5:9b240c1d5251	835	/@} end of group CMSIS_SCB /
yihui	5:9b240c1d5251	836
yihui	5:9b240c1d5251	837
yihui	5:9b240c1d5251	838	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	839	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
yihui	5:9b240c1d5251	840	\brief Type definitions for the System Control and ID Register not in the SCB
yihui	5:9b240c1d5251	841	@{
yihui	5:9b240c1d5251	842	*/
yihui	5:9b240c1d5251	843
yihui	5:9b240c1d5251	844	/** \brief Structure type to access the System Control and ID Register not in the SCB.
yihui	5:9b240c1d5251	845	*/
yihui	5:9b240c1d5251	846	typedef struct
yihui	5:9b240c1d5251	847	{
yihui	5:9b240c1d5251	848	uint32_t RESERVED0[1];
yihui	5:9b240c1d5251	849	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
yihui	5:9b240c1d5251	850	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
yihui	5:9b240c1d5251	851	} SCnSCB_Type;
yihui	5:9b240c1d5251	852
yihui	5:9b240c1d5251	853	/* Interrupt Controller Type Register Definitions */
yihui	5:9b240c1d5251	854	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
yihui	5:9b240c1d5251	855	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
yihui	5:9b240c1d5251	856
yihui	5:9b240c1d5251	857	/* Auxiliary Control Register Definitions */
yihui	5:9b240c1d5251	858	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
yihui	5:9b240c1d5251	859	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
yihui	5:9b240c1d5251	860
yihui	5:9b240c1d5251	861	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
yihui	5:9b240c1d5251	862	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
yihui	5:9b240c1d5251	863
yihui	5:9b240c1d5251	864	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
yihui	5:9b240c1d5251	865	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
yihui	5:9b240c1d5251	866
yihui	5:9b240c1d5251	867	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
yihui	5:9b240c1d5251	868	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
yihui	5:9b240c1d5251	869
yihui	5:9b240c1d5251	870	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
yihui	5:9b240c1d5251	871	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
yihui	5:9b240c1d5251	872
yihui	5:9b240c1d5251	873	/@} end of group CMSIS_SCnotSCB /
yihui	5:9b240c1d5251	874
yihui	5:9b240c1d5251	875
yihui	5:9b240c1d5251	876	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	877	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
yihui	5:9b240c1d5251	878	\brief Type definitions for the System Timer Registers.
yihui	5:9b240c1d5251	879	@{
yihui	5:9b240c1d5251	880	*/
yihui	5:9b240c1d5251	881
yihui	5:9b240c1d5251	882	/** \brief Structure type to access the System Timer (SysTick).
yihui	5:9b240c1d5251	883	*/
yihui	5:9b240c1d5251	884	typedef struct
yihui	5:9b240c1d5251	885	{
yihui	5:9b240c1d5251	886	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
yihui	5:9b240c1d5251	887	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
yihui	5:9b240c1d5251	888	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
yihui	5:9b240c1d5251	889	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
yihui	5:9b240c1d5251	890	} SysTick_Type;
yihui	5:9b240c1d5251	891
yihui	5:9b240c1d5251	892	/* SysTick Control / Status Register Definitions */
yihui	5:9b240c1d5251	893	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
yihui	5:9b240c1d5251	894	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
yihui	5:9b240c1d5251	895
yihui	5:9b240c1d5251	896	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
yihui	5:9b240c1d5251	897	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
yihui	5:9b240c1d5251	898
yihui	5:9b240c1d5251	899	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
yihui	5:9b240c1d5251	900	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
yihui	5:9b240c1d5251	901
yihui	5:9b240c1d5251	902	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
yihui	5:9b240c1d5251	903	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
yihui	5:9b240c1d5251	904
yihui	5:9b240c1d5251	905	/* SysTick Reload Register Definitions */
yihui	5:9b240c1d5251	906	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
yihui	5:9b240c1d5251	907	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
yihui	5:9b240c1d5251	908
yihui	5:9b240c1d5251	909	/* SysTick Current Register Definitions */
yihui	5:9b240c1d5251	910	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
yihui	5:9b240c1d5251	911	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
yihui	5:9b240c1d5251	912
yihui	5:9b240c1d5251	913	/* SysTick Calibration Register Definitions */
yihui	5:9b240c1d5251	914	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
yihui	5:9b240c1d5251	915	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
yihui	5:9b240c1d5251	916
yihui	5:9b240c1d5251	917	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
yihui	5:9b240c1d5251	918	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
yihui	5:9b240c1d5251	919
yihui	5:9b240c1d5251	920	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
yihui	5:9b240c1d5251	921	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
yihui	5:9b240c1d5251	922
yihui	5:9b240c1d5251	923	/@} end of group CMSIS_SysTick /
yihui	5:9b240c1d5251	924
yihui	5:9b240c1d5251	925
yihui	5:9b240c1d5251	926	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	927	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
yihui	5:9b240c1d5251	928	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
yihui	5:9b240c1d5251	929	@{
yihui	5:9b240c1d5251	930	*/
yihui	5:9b240c1d5251	931
yihui	5:9b240c1d5251	932	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
yihui	5:9b240c1d5251	933	*/
yihui	5:9b240c1d5251	934	typedef struct
yihui	5:9b240c1d5251	935	{
yihui	5:9b240c1d5251	936	__O union
yihui	5:9b240c1d5251	937	{
yihui	5:9b240c1d5251	938	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
yihui	5:9b240c1d5251	939	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
yihui	5:9b240c1d5251	940	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
yihui	5:9b240c1d5251	941	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
yihui	5:9b240c1d5251	942	uint32_t RESERVED0[864];
yihui	5:9b240c1d5251	943	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
yihui	5:9b240c1d5251	944	uint32_t RESERVED1[15];
yihui	5:9b240c1d5251	945	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
yihui	5:9b240c1d5251	946	uint32_t RESERVED2[15];
yihui	5:9b240c1d5251	947	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
yihui	5:9b240c1d5251	948	uint32_t RESERVED3[29];
yihui	5:9b240c1d5251	949	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
yihui	5:9b240c1d5251	950	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
yihui	5:9b240c1d5251	951	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
yihui	5:9b240c1d5251	952	uint32_t RESERVED4[43];
yihui	5:9b240c1d5251	953	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
yihui	5:9b240c1d5251	954	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
yihui	5:9b240c1d5251	955	uint32_t RESERVED5[6];
yihui	5:9b240c1d5251	956	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
yihui	5:9b240c1d5251	957	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
yihui	5:9b240c1d5251	958	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
yihui	5:9b240c1d5251	959	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
yihui	5:9b240c1d5251	960	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
yihui	5:9b240c1d5251	961	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
yihui	5:9b240c1d5251	962	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
yihui	5:9b240c1d5251	963	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
yihui	5:9b240c1d5251	964	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
yihui	5:9b240c1d5251	965	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
yihui	5:9b240c1d5251	966	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
yihui	5:9b240c1d5251	967	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
yihui	5:9b240c1d5251	968	} ITM_Type;
yihui	5:9b240c1d5251	969
yihui	5:9b240c1d5251	970	/* ITM Trace Privilege Register Definitions */
yihui	5:9b240c1d5251	971	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
yihui	5:9b240c1d5251	972	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
yihui	5:9b240c1d5251	973
yihui	5:9b240c1d5251	974	/* ITM Trace Control Register Definitions */
yihui	5:9b240c1d5251	975	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
yihui	5:9b240c1d5251	976	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
yihui	5:9b240c1d5251	977
yihui	5:9b240c1d5251	978	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
yihui	5:9b240c1d5251	979	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
yihui	5:9b240c1d5251	980
yihui	5:9b240c1d5251	981	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
yihui	5:9b240c1d5251	982	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
yihui	5:9b240c1d5251	983
yihui	5:9b240c1d5251	984	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
yihui	5:9b240c1d5251	985	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
yihui	5:9b240c1d5251	986
yihui	5:9b240c1d5251	987	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
yihui	5:9b240c1d5251	988	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
yihui	5:9b240c1d5251	989
yihui	5:9b240c1d5251	990	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
yihui	5:9b240c1d5251	991	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
yihui	5:9b240c1d5251	992
yihui	5:9b240c1d5251	993	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
yihui	5:9b240c1d5251	994	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
yihui	5:9b240c1d5251	995
yihui	5:9b240c1d5251	996	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
yihui	5:9b240c1d5251	997	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
yihui	5:9b240c1d5251	998
yihui	5:9b240c1d5251	999	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
yihui	5:9b240c1d5251	1000	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
yihui	5:9b240c1d5251	1001
yihui	5:9b240c1d5251	1002	/* ITM Integration Write Register Definitions */
yihui	5:9b240c1d5251	1003	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
yihui	5:9b240c1d5251	1004	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
yihui	5:9b240c1d5251	1005
yihui	5:9b240c1d5251	1006	/* ITM Integration Read Register Definitions */
yihui	5:9b240c1d5251	1007	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
yihui	5:9b240c1d5251	1008	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
yihui	5:9b240c1d5251	1009
yihui	5:9b240c1d5251	1010	/* ITM Integration Mode Control Register Definitions */
yihui	5:9b240c1d5251	1011	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
yihui	5:9b240c1d5251	1012	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
yihui	5:9b240c1d5251	1013
yihui	5:9b240c1d5251	1014	/* ITM Lock Status Register Definitions */
yihui	5:9b240c1d5251	1015	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
yihui	5:9b240c1d5251	1016	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
yihui	5:9b240c1d5251	1017
yihui	5:9b240c1d5251	1018	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
yihui	5:9b240c1d5251	1019	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
yihui	5:9b240c1d5251	1020
yihui	5:9b240c1d5251	1021	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
yihui	5:9b240c1d5251	1022	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
yihui	5:9b240c1d5251	1023
yihui	5:9b240c1d5251	1024	/@}/ /* end of group CMSIS_ITM */
yihui	5:9b240c1d5251	1025
yihui	5:9b240c1d5251	1026
yihui	5:9b240c1d5251	1027	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	1028	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
yihui	5:9b240c1d5251	1029	\brief Type definitions for the Data Watchpoint and Trace (DWT)
yihui	5:9b240c1d5251	1030	@{
yihui	5:9b240c1d5251	1031	*/
yihui	5:9b240c1d5251	1032
yihui	5:9b240c1d5251	1033	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
yihui	5:9b240c1d5251	1034	*/
yihui	5:9b240c1d5251	1035	typedef struct
yihui	5:9b240c1d5251	1036	{
yihui	5:9b240c1d5251	1037	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
yihui	5:9b240c1d5251	1038	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
yihui	5:9b240c1d5251	1039	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
yihui	5:9b240c1d5251	1040	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
yihui	5:9b240c1d5251	1041	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
yihui	5:9b240c1d5251	1042	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
yihui	5:9b240c1d5251	1043	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
yihui	5:9b240c1d5251	1044	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
yihui	5:9b240c1d5251	1045	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
yihui	5:9b240c1d5251	1046	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
yihui	5:9b240c1d5251	1047	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
yihui	5:9b240c1d5251	1048	uint32_t RESERVED0[1];
yihui	5:9b240c1d5251	1049	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
yihui	5:9b240c1d5251	1050	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
yihui	5:9b240c1d5251	1051	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
yihui	5:9b240c1d5251	1052	uint32_t RESERVED1[1];
yihui	5:9b240c1d5251	1053	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
yihui	5:9b240c1d5251	1054	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
yihui	5:9b240c1d5251	1055	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
yihui	5:9b240c1d5251	1056	uint32_t RESERVED2[1];
yihui	5:9b240c1d5251	1057	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
yihui	5:9b240c1d5251	1058	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
yihui	5:9b240c1d5251	1059	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
yihui	5:9b240c1d5251	1060	uint32_t RESERVED3[981];
yihui	5:9b240c1d5251	1061	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
yihui	5:9b240c1d5251	1062	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
yihui	5:9b240c1d5251	1063	} DWT_Type;
yihui	5:9b240c1d5251	1064
yihui	5:9b240c1d5251	1065	/* DWT Control Register Definitions */
yihui	5:9b240c1d5251	1066	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
yihui	5:9b240c1d5251	1067	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
yihui	5:9b240c1d5251	1068
yihui	5:9b240c1d5251	1069	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
yihui	5:9b240c1d5251	1070	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
yihui	5:9b240c1d5251	1071
yihui	5:9b240c1d5251	1072	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
yihui	5:9b240c1d5251	1073	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
yihui	5:9b240c1d5251	1074
yihui	5:9b240c1d5251	1075	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
yihui	5:9b240c1d5251	1076	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
yihui	5:9b240c1d5251	1077
yihui	5:9b240c1d5251	1078	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
yihui	5:9b240c1d5251	1079	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
yihui	5:9b240c1d5251	1080
yihui	5:9b240c1d5251	1081	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
yihui	5:9b240c1d5251	1082	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
yihui	5:9b240c1d5251	1083
yihui	5:9b240c1d5251	1084	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
yihui	5:9b240c1d5251	1085	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
yihui	5:9b240c1d5251	1086
yihui	5:9b240c1d5251	1087	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
yihui	5:9b240c1d5251	1088	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
yihui	5:9b240c1d5251	1089
yihui	5:9b240c1d5251	1090	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
yihui	5:9b240c1d5251	1091	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
yihui	5:9b240c1d5251	1092
yihui	5:9b240c1d5251	1093	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
yihui	5:9b240c1d5251	1094	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
yihui	5:9b240c1d5251	1095
yihui	5:9b240c1d5251	1096	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
yihui	5:9b240c1d5251	1097	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
yihui	5:9b240c1d5251	1098
yihui	5:9b240c1d5251	1099	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
yihui	5:9b240c1d5251	1100	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
yihui	5:9b240c1d5251	1101
yihui	5:9b240c1d5251	1102	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
yihui	5:9b240c1d5251	1103	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
yihui	5:9b240c1d5251	1104
yihui	5:9b240c1d5251	1105	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
yihui	5:9b240c1d5251	1106	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
yihui	5:9b240c1d5251	1107
yihui	5:9b240c1d5251	1108	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
yihui	5:9b240c1d5251	1109	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
yihui	5:9b240c1d5251	1110
yihui	5:9b240c1d5251	1111	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
yihui	5:9b240c1d5251	1112	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
yihui	5:9b240c1d5251	1113
yihui	5:9b240c1d5251	1114	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
yihui	5:9b240c1d5251	1115	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
yihui	5:9b240c1d5251	1116
yihui	5:9b240c1d5251	1117	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
yihui	5:9b240c1d5251	1118	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
yihui	5:9b240c1d5251	1119
yihui	5:9b240c1d5251	1120	/* DWT CPI Count Register Definitions */
yihui	5:9b240c1d5251	1121	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
yihui	5:9b240c1d5251	1122	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
yihui	5:9b240c1d5251	1123
yihui	5:9b240c1d5251	1124	/* DWT Exception Overhead Count Register Definitions */
yihui	5:9b240c1d5251	1125	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
yihui	5:9b240c1d5251	1126	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
yihui	5:9b240c1d5251	1127
yihui	5:9b240c1d5251	1128	/* DWT Sleep Count Register Definitions */
yihui	5:9b240c1d5251	1129	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
yihui	5:9b240c1d5251	1130	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
yihui	5:9b240c1d5251	1131
yihui	5:9b240c1d5251	1132	/* DWT LSU Count Register Definitions */
yihui	5:9b240c1d5251	1133	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
yihui	5:9b240c1d5251	1134	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
yihui	5:9b240c1d5251	1135
yihui	5:9b240c1d5251	1136	/* DWT Folded-instruction Count Register Definitions */
yihui	5:9b240c1d5251	1137	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
yihui	5:9b240c1d5251	1138	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
yihui	5:9b240c1d5251	1139
yihui	5:9b240c1d5251	1140	/* DWT Comparator Mask Register Definitions */
yihui	5:9b240c1d5251	1141	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
yihui	5:9b240c1d5251	1142	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
yihui	5:9b240c1d5251	1143
yihui	5:9b240c1d5251	1144	/* DWT Comparator Function Register Definitions */
yihui	5:9b240c1d5251	1145	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
yihui	5:9b240c1d5251	1146	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
yihui	5:9b240c1d5251	1147
yihui	5:9b240c1d5251	1148	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
yihui	5:9b240c1d5251	1149	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
yihui	5:9b240c1d5251	1150
yihui	5:9b240c1d5251	1151	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
yihui	5:9b240c1d5251	1152	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
yihui	5:9b240c1d5251	1153
yihui	5:9b240c1d5251	1154	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
yihui	5:9b240c1d5251	1155	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
yihui	5:9b240c1d5251	1156
yihui	5:9b240c1d5251	1157	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
yihui	5:9b240c1d5251	1158	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
yihui	5:9b240c1d5251	1159
yihui	5:9b240c1d5251	1160	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
yihui	5:9b240c1d5251	1161	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
yihui	5:9b240c1d5251	1162
yihui	5:9b240c1d5251	1163	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
yihui	5:9b240c1d5251	1164	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
yihui	5:9b240c1d5251	1165
yihui	5:9b240c1d5251	1166	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
yihui	5:9b240c1d5251	1167	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
yihui	5:9b240c1d5251	1168
yihui	5:9b240c1d5251	1169	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
yihui	5:9b240c1d5251	1170	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
yihui	5:9b240c1d5251	1171
yihui	5:9b240c1d5251	1172	/@}/ /* end of group CMSIS_DWT */
yihui	5:9b240c1d5251	1173
yihui	5:9b240c1d5251	1174
yihui	5:9b240c1d5251	1175	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	1176	\defgroup CMSIS_TPI Trace Port Interface (TPI)
yihui	5:9b240c1d5251	1177	\brief Type definitions for the Trace Port Interface (TPI)
yihui	5:9b240c1d5251	1178	@{
yihui	5:9b240c1d5251	1179	*/
yihui	5:9b240c1d5251	1180
yihui	5:9b240c1d5251	1181	/** \brief Structure type to access the Trace Port Interface Register (TPI).
yihui	5:9b240c1d5251	1182	*/
yihui	5:9b240c1d5251	1183	typedef struct
yihui	5:9b240c1d5251	1184	{
yihui	5:9b240c1d5251	1185	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
yihui	5:9b240c1d5251	1186	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
yihui	5:9b240c1d5251	1187	uint32_t RESERVED0[2];
yihui	5:9b240c1d5251	1188	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
yihui	5:9b240c1d5251	1189	uint32_t RESERVED1[55];
yihui	5:9b240c1d5251	1190	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
yihui	5:9b240c1d5251	1191	uint32_t RESERVED2[131];
yihui	5:9b240c1d5251	1192	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
yihui	5:9b240c1d5251	1193	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
yihui	5:9b240c1d5251	1194	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
yihui	5:9b240c1d5251	1195	uint32_t RESERVED3[759];
yihui	5:9b240c1d5251	1196	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
yihui	5:9b240c1d5251	1197	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
yihui	5:9b240c1d5251	1198	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
yihui	5:9b240c1d5251	1199	uint32_t RESERVED4[1];
yihui	5:9b240c1d5251	1200	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
yihui	5:9b240c1d5251	1201	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
yihui	5:9b240c1d5251	1202	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
yihui	5:9b240c1d5251	1203	uint32_t RESERVED5[39];
yihui	5:9b240c1d5251	1204	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
yihui	5:9b240c1d5251	1205	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
yihui	5:9b240c1d5251	1206	uint32_t RESERVED7[8];
yihui	5:9b240c1d5251	1207	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
yihui	5:9b240c1d5251	1208	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
yihui	5:9b240c1d5251	1209	} TPI_Type;
yihui	5:9b240c1d5251	1210
yihui	5:9b240c1d5251	1211	/* TPI Asynchronous Clock Prescaler Register Definitions */
yihui	5:9b240c1d5251	1212	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
yihui	5:9b240c1d5251	1213	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
yihui	5:9b240c1d5251	1214
yihui	5:9b240c1d5251	1215	/* TPI Selected Pin Protocol Register Definitions */
yihui	5:9b240c1d5251	1216	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
yihui	5:9b240c1d5251	1217	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
yihui	5:9b240c1d5251	1218
yihui	5:9b240c1d5251	1219	/* TPI Formatter and Flush Status Register Definitions */
yihui	5:9b240c1d5251	1220	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
yihui	5:9b240c1d5251	1221	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
yihui	5:9b240c1d5251	1222
yihui	5:9b240c1d5251	1223	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
yihui	5:9b240c1d5251	1224	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
yihui	5:9b240c1d5251	1225
yihui	5:9b240c1d5251	1226	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
yihui	5:9b240c1d5251	1227	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
yihui	5:9b240c1d5251	1228
yihui	5:9b240c1d5251	1229	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
yihui	5:9b240c1d5251	1230	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
yihui	5:9b240c1d5251	1231
yihui	5:9b240c1d5251	1232	/* TPI Formatter and Flush Control Register Definitions */
yihui	5:9b240c1d5251	1233	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
yihui	5:9b240c1d5251	1234	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
yihui	5:9b240c1d5251	1235
yihui	5:9b240c1d5251	1236	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
yihui	5:9b240c1d5251	1237	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
yihui	5:9b240c1d5251	1238
yihui	5:9b240c1d5251	1239	/* TPI TRIGGER Register Definitions */
yihui	5:9b240c1d5251	1240	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
yihui	5:9b240c1d5251	1241	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
yihui	5:9b240c1d5251	1242
yihui	5:9b240c1d5251	1243	/* TPI Integration ETM Data Register Definitions (FIFO0) */
yihui	5:9b240c1d5251	1244	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
yihui	5:9b240c1d5251	1245	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
yihui	5:9b240c1d5251	1246
yihui	5:9b240c1d5251	1247	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
yihui	5:9b240c1d5251	1248	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
yihui	5:9b240c1d5251	1249
yihui	5:9b240c1d5251	1250	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
yihui	5:9b240c1d5251	1251	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
yihui	5:9b240c1d5251	1252
yihui	5:9b240c1d5251	1253	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
yihui	5:9b240c1d5251	1254	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
yihui	5:9b240c1d5251	1255
yihui	5:9b240c1d5251	1256	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
yihui	5:9b240c1d5251	1257	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
yihui	5:9b240c1d5251	1258
yihui	5:9b240c1d5251	1259	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
yihui	5:9b240c1d5251	1260	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
yihui	5:9b240c1d5251	1261
yihui	5:9b240c1d5251	1262	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
yihui	5:9b240c1d5251	1263	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
yihui	5:9b240c1d5251	1264
yihui	5:9b240c1d5251	1265	/* TPI ITATBCTR2 Register Definitions */
yihui	5:9b240c1d5251	1266	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
yihui	5:9b240c1d5251	1267	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
yihui	5:9b240c1d5251	1268
yihui	5:9b240c1d5251	1269	/* TPI Integration ITM Data Register Definitions (FIFO1) */
yihui	5:9b240c1d5251	1270	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
yihui	5:9b240c1d5251	1271	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
yihui	5:9b240c1d5251	1272
yihui	5:9b240c1d5251	1273	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
yihui	5:9b240c1d5251	1274	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
yihui	5:9b240c1d5251	1275
yihui	5:9b240c1d5251	1276	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
yihui	5:9b240c1d5251	1277	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
yihui	5:9b240c1d5251	1278
yihui	5:9b240c1d5251	1279	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
yihui	5:9b240c1d5251	1280	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
yihui	5:9b240c1d5251	1281
yihui	5:9b240c1d5251	1282	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
yihui	5:9b240c1d5251	1283	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
yihui	5:9b240c1d5251	1284
yihui	5:9b240c1d5251	1285	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
yihui	5:9b240c1d5251	1286	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
yihui	5:9b240c1d5251	1287
yihui	5:9b240c1d5251	1288	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
yihui	5:9b240c1d5251	1289	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
yihui	5:9b240c1d5251	1290
yihui	5:9b240c1d5251	1291	/* TPI ITATBCTR0 Register Definitions */
yihui	5:9b240c1d5251	1292	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
yihui	5:9b240c1d5251	1293	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
yihui	5:9b240c1d5251	1294
yihui	5:9b240c1d5251	1295	/* TPI Integration Mode Control Register Definitions */
yihui	5:9b240c1d5251	1296	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
yihui	5:9b240c1d5251	1297	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
yihui	5:9b240c1d5251	1298
yihui	5:9b240c1d5251	1299	/* TPI DEVID Register Definitions */
yihui	5:9b240c1d5251	1300	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
yihui	5:9b240c1d5251	1301	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
yihui	5:9b240c1d5251	1302
yihui	5:9b240c1d5251	1303	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
yihui	5:9b240c1d5251	1304	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
yihui	5:9b240c1d5251	1305
yihui	5:9b240c1d5251	1306	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
yihui	5:9b240c1d5251	1307	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
yihui	5:9b240c1d5251	1308
yihui	5:9b240c1d5251	1309	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
yihui	5:9b240c1d5251	1310	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
yihui	5:9b240c1d5251	1311
yihui	5:9b240c1d5251	1312	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
yihui	5:9b240c1d5251	1313	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
yihui	5:9b240c1d5251	1314
yihui	5:9b240c1d5251	1315	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
yihui	5:9b240c1d5251	1316	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
yihui	5:9b240c1d5251	1317
yihui	5:9b240c1d5251	1318	/* TPI DEVTYPE Register Definitions */
yihui	5:9b240c1d5251	1319	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
yihui	5:9b240c1d5251	1320	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
yihui	5:9b240c1d5251	1321
yihui	5:9b240c1d5251	1322	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
yihui	5:9b240c1d5251	1323	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
yihui	5:9b240c1d5251	1324
yihui	5:9b240c1d5251	1325	/@}/ /* end of group CMSIS_TPI */
yihui	5:9b240c1d5251	1326
yihui	5:9b240c1d5251	1327
yihui	5:9b240c1d5251	1328	#if (__MPU_PRESENT == 1)
yihui	5:9b240c1d5251	1329	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	1330	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
yihui	5:9b240c1d5251	1331	\brief Type definitions for the Memory Protection Unit (MPU)
yihui	5:9b240c1d5251	1332	@{
yihui	5:9b240c1d5251	1333	*/
yihui	5:9b240c1d5251	1334
yihui	5:9b240c1d5251	1335	/** \brief Structure type to access the Memory Protection Unit (MPU).
yihui	5:9b240c1d5251	1336	*/
yihui	5:9b240c1d5251	1337	typedef struct
yihui	5:9b240c1d5251	1338	{
yihui	5:9b240c1d5251	1339	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
yihui	5:9b240c1d5251	1340	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
yihui	5:9b240c1d5251	1341	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
yihui	5:9b240c1d5251	1342	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
yihui	5:9b240c1d5251	1343	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
yihui	5:9b240c1d5251	1344	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
yihui	5:9b240c1d5251	1345	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
yihui	5:9b240c1d5251	1346	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
yihui	5:9b240c1d5251	1347	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
yihui	5:9b240c1d5251	1348	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
yihui	5:9b240c1d5251	1349	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
yihui	5:9b240c1d5251	1350	} MPU_Type;
yihui	5:9b240c1d5251	1351
yihui	5:9b240c1d5251	1352	/* MPU Type Register */
yihui	5:9b240c1d5251	1353	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
yihui	5:9b240c1d5251	1354	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
yihui	5:9b240c1d5251	1355
yihui	5:9b240c1d5251	1356	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
yihui	5:9b240c1d5251	1357	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
yihui	5:9b240c1d5251	1358
yihui	5:9b240c1d5251	1359	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
yihui	5:9b240c1d5251	1360	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
yihui	5:9b240c1d5251	1361
yihui	5:9b240c1d5251	1362	/* MPU Control Register */
yihui	5:9b240c1d5251	1363	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
yihui	5:9b240c1d5251	1364	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
yihui	5:9b240c1d5251	1365
yihui	5:9b240c1d5251	1366	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
yihui	5:9b240c1d5251	1367	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
yihui	5:9b240c1d5251	1368
yihui	5:9b240c1d5251	1369	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
yihui	5:9b240c1d5251	1370	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
yihui	5:9b240c1d5251	1371
yihui	5:9b240c1d5251	1372	/* MPU Region Number Register */
yihui	5:9b240c1d5251	1373	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
yihui	5:9b240c1d5251	1374	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
yihui	5:9b240c1d5251	1375
yihui	5:9b240c1d5251	1376	/* MPU Region Base Address Register */
yihui	5:9b240c1d5251	1377	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
yihui	5:9b240c1d5251	1378	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
yihui	5:9b240c1d5251	1379
yihui	5:9b240c1d5251	1380	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
yihui	5:9b240c1d5251	1381	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
yihui	5:9b240c1d5251	1382
yihui	5:9b240c1d5251	1383	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
yihui	5:9b240c1d5251	1384	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
yihui	5:9b240c1d5251	1385
yihui	5:9b240c1d5251	1386	/* MPU Region Attribute and Size Register */
yihui	5:9b240c1d5251	1387	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
yihui	5:9b240c1d5251	1388	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
yihui	5:9b240c1d5251	1389
yihui	5:9b240c1d5251	1390	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
yihui	5:9b240c1d5251	1391	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
yihui	5:9b240c1d5251	1392
yihui	5:9b240c1d5251	1393	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
yihui	5:9b240c1d5251	1394	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
yihui	5:9b240c1d5251	1395
yihui	5:9b240c1d5251	1396	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
yihui	5:9b240c1d5251	1397	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
yihui	5:9b240c1d5251	1398
yihui	5:9b240c1d5251	1399	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
yihui	5:9b240c1d5251	1400	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
yihui	5:9b240c1d5251	1401
yihui	5:9b240c1d5251	1402	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
yihui	5:9b240c1d5251	1403	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
yihui	5:9b240c1d5251	1404
yihui	5:9b240c1d5251	1405	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
yihui	5:9b240c1d5251	1406	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
yihui	5:9b240c1d5251	1407
yihui	5:9b240c1d5251	1408	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
yihui	5:9b240c1d5251	1409	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
yihui	5:9b240c1d5251	1410
yihui	5:9b240c1d5251	1411	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
yihui	5:9b240c1d5251	1412	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
yihui	5:9b240c1d5251	1413
yihui	5:9b240c1d5251	1414	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
yihui	5:9b240c1d5251	1415	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
yihui	5:9b240c1d5251	1416
yihui	5:9b240c1d5251	1417	/@} end of group CMSIS_MPU /
yihui	5:9b240c1d5251	1418	#endif
yihui	5:9b240c1d5251	1419
yihui	5:9b240c1d5251	1420
yihui	5:9b240c1d5251	1421	#if (__FPU_PRESENT == 1)
yihui	5:9b240c1d5251	1422	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	1423	\defgroup CMSIS_FPU Floating Point Unit (FPU)
yihui	5:9b240c1d5251	1424	\brief Type definitions for the Floating Point Unit (FPU)
yihui	5:9b240c1d5251	1425	@{
yihui	5:9b240c1d5251	1426	*/
yihui	5:9b240c1d5251	1427
yihui	5:9b240c1d5251	1428	/** \brief Structure type to access the Floating Point Unit (FPU).
yihui	5:9b240c1d5251	1429	*/
yihui	5:9b240c1d5251	1430	typedef struct
yihui	5:9b240c1d5251	1431	{
yihui	5:9b240c1d5251	1432	uint32_t RESERVED0[1];
yihui	5:9b240c1d5251	1433	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
yihui	5:9b240c1d5251	1434	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
yihui	5:9b240c1d5251	1435	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
yihui	5:9b240c1d5251	1436	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
yihui	5:9b240c1d5251	1437	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
yihui	5:9b240c1d5251	1438	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
yihui	5:9b240c1d5251	1439	} FPU_Type;
yihui	5:9b240c1d5251	1440
yihui	5:9b240c1d5251	1441	/* Floating-Point Context Control Register */
yihui	5:9b240c1d5251	1442	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
yihui	5:9b240c1d5251	1443	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
yihui	5:9b240c1d5251	1444
yihui	5:9b240c1d5251	1445	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
yihui	5:9b240c1d5251	1446	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
yihui	5:9b240c1d5251	1447
yihui	5:9b240c1d5251	1448	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
yihui	5:9b240c1d5251	1449	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
yihui	5:9b240c1d5251	1450
yihui	5:9b240c1d5251	1451	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
yihui	5:9b240c1d5251	1452	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
yihui	5:9b240c1d5251	1453
yihui	5:9b240c1d5251	1454	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
yihui	5:9b240c1d5251	1455	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
yihui	5:9b240c1d5251	1456
yihui	5:9b240c1d5251	1457	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
yihui	5:9b240c1d5251	1458	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
yihui	5:9b240c1d5251	1459
yihui	5:9b240c1d5251	1460	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
yihui	5:9b240c1d5251	1461	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
yihui	5:9b240c1d5251	1462
yihui	5:9b240c1d5251	1463	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
yihui	5:9b240c1d5251	1464	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
yihui	5:9b240c1d5251	1465
yihui	5:9b240c1d5251	1466	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
yihui	5:9b240c1d5251	1467	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
yihui	5:9b240c1d5251	1468
yihui	5:9b240c1d5251	1469	/* Floating-Point Context Address Register */
yihui	5:9b240c1d5251	1470	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
yihui	5:9b240c1d5251	1471	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
yihui	5:9b240c1d5251	1472
yihui	5:9b240c1d5251	1473	/* Floating-Point Default Status Control Register */
yihui	5:9b240c1d5251	1474	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
yihui	5:9b240c1d5251	1475	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
yihui	5:9b240c1d5251	1476
yihui	5:9b240c1d5251	1477	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
yihui	5:9b240c1d5251	1478	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
yihui	5:9b240c1d5251	1479
yihui	5:9b240c1d5251	1480	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
yihui	5:9b240c1d5251	1481	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
yihui	5:9b240c1d5251	1482
yihui	5:9b240c1d5251	1483	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
yihui	5:9b240c1d5251	1484	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
yihui	5:9b240c1d5251	1485
yihui	5:9b240c1d5251	1486	/* Media and FP Feature Register 0 */
yihui	5:9b240c1d5251	1487	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
yihui	5:9b240c1d5251	1488	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
yihui	5:9b240c1d5251	1489
yihui	5:9b240c1d5251	1490	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
yihui	5:9b240c1d5251	1491	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
yihui	5:9b240c1d5251	1492
yihui	5:9b240c1d5251	1493	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
yihui	5:9b240c1d5251	1494	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
yihui	5:9b240c1d5251	1495
yihui	5:9b240c1d5251	1496	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
yihui	5:9b240c1d5251	1497	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
yihui	5:9b240c1d5251	1498
yihui	5:9b240c1d5251	1499	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
yihui	5:9b240c1d5251	1500	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
yihui	5:9b240c1d5251	1501
yihui	5:9b240c1d5251	1502	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
yihui	5:9b240c1d5251	1503	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
yihui	5:9b240c1d5251	1504
yihui	5:9b240c1d5251	1505	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
yihui	5:9b240c1d5251	1506	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
yihui	5:9b240c1d5251	1507
yihui	5:9b240c1d5251	1508	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
yihui	5:9b240c1d5251	1509	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
yihui	5:9b240c1d5251	1510
yihui	5:9b240c1d5251	1511	/* Media and FP Feature Register 1 */
yihui	5:9b240c1d5251	1512	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
yihui	5:9b240c1d5251	1513	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
yihui	5:9b240c1d5251	1514
yihui	5:9b240c1d5251	1515	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
yihui	5:9b240c1d5251	1516	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
yihui	5:9b240c1d5251	1517
yihui	5:9b240c1d5251	1518	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
yihui	5:9b240c1d5251	1519	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
yihui	5:9b240c1d5251	1520
yihui	5:9b240c1d5251	1521	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
yihui	5:9b240c1d5251	1522	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
yihui	5:9b240c1d5251	1523
yihui	5:9b240c1d5251	1524	/* Media and FP Feature Register 2 */
yihui	5:9b240c1d5251	1525
yihui	5:9b240c1d5251	1526	/@} end of group CMSIS_FPU /
yihui	5:9b240c1d5251	1527	#endif
yihui	5:9b240c1d5251	1528
yihui	5:9b240c1d5251	1529
yihui	5:9b240c1d5251	1530	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	1531	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
yihui	5:9b240c1d5251	1532	\brief Type definitions for the Core Debug Registers
yihui	5:9b240c1d5251	1533	@{
yihui	5:9b240c1d5251	1534	*/
yihui	5:9b240c1d5251	1535
yihui	5:9b240c1d5251	1536	/** \brief Structure type to access the Core Debug Register (CoreDebug).
yihui	5:9b240c1d5251	1537	*/
yihui	5:9b240c1d5251	1538	typedef struct
yihui	5:9b240c1d5251	1539	{
yihui	5:9b240c1d5251	1540	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
yihui	5:9b240c1d5251	1541	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
yihui	5:9b240c1d5251	1542	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
yihui	5:9b240c1d5251	1543	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
yihui	5:9b240c1d5251	1544	} CoreDebug_Type;
yihui	5:9b240c1d5251	1545
yihui	5:9b240c1d5251	1546	/* Debug Halting Control and Status Register */
yihui	5:9b240c1d5251	1547	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
yihui	5:9b240c1d5251	1548	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
yihui	5:9b240c1d5251	1549
yihui	5:9b240c1d5251	1550	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
yihui	5:9b240c1d5251	1551	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
yihui	5:9b240c1d5251	1552
yihui	5:9b240c1d5251	1553	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
yihui	5:9b240c1d5251	1554	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
yihui	5:9b240c1d5251	1555
yihui	5:9b240c1d5251	1556	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
yihui	5:9b240c1d5251	1557	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
yihui	5:9b240c1d5251	1558
yihui	5:9b240c1d5251	1559	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
yihui	5:9b240c1d5251	1560	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
yihui	5:9b240c1d5251	1561
yihui	5:9b240c1d5251	1562	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
yihui	5:9b240c1d5251	1563	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
yihui	5:9b240c1d5251	1564
yihui	5:9b240c1d5251	1565	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
yihui	5:9b240c1d5251	1566	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
yihui	5:9b240c1d5251	1567
yihui	5:9b240c1d5251	1568	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
yihui	5:9b240c1d5251	1569	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
yihui	5:9b240c1d5251	1570
yihui	5:9b240c1d5251	1571	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
yihui	5:9b240c1d5251	1572	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
yihui	5:9b240c1d5251	1573
yihui	5:9b240c1d5251	1574	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
yihui	5:9b240c1d5251	1575	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
yihui	5:9b240c1d5251	1576
yihui	5:9b240c1d5251	1577	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
yihui	5:9b240c1d5251	1578	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
yihui	5:9b240c1d5251	1579
yihui	5:9b240c1d5251	1580	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
yihui	5:9b240c1d5251	1581	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
yihui	5:9b240c1d5251	1582
yihui	5:9b240c1d5251	1583	/* Debug Core Register Selector Register */
yihui	5:9b240c1d5251	1584	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
yihui	5:9b240c1d5251	1585	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
yihui	5:9b240c1d5251	1586
yihui	5:9b240c1d5251	1587	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
yihui	5:9b240c1d5251	1588	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
yihui	5:9b240c1d5251	1589
yihui	5:9b240c1d5251	1590	/* Debug Exception and Monitor Control Register */
yihui	5:9b240c1d5251	1591	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
yihui	5:9b240c1d5251	1592	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
yihui	5:9b240c1d5251	1593
yihui	5:9b240c1d5251	1594	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
yihui	5:9b240c1d5251	1595	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
yihui	5:9b240c1d5251	1596
yihui	5:9b240c1d5251	1597	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
yihui	5:9b240c1d5251	1598	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
yihui	5:9b240c1d5251	1599
yihui	5:9b240c1d5251	1600	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
yihui	5:9b240c1d5251	1601	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
yihui	5:9b240c1d5251	1602
yihui	5:9b240c1d5251	1603	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
yihui	5:9b240c1d5251	1604	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
yihui	5:9b240c1d5251	1605
yihui	5:9b240c1d5251	1606	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
yihui	5:9b240c1d5251	1607	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
yihui	5:9b240c1d5251	1608
yihui	5:9b240c1d5251	1609	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
yihui	5:9b240c1d5251	1610	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
yihui	5:9b240c1d5251	1611
yihui	5:9b240c1d5251	1612	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
yihui	5:9b240c1d5251	1613	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
yihui	5:9b240c1d5251	1614
yihui	5:9b240c1d5251	1615	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
yihui	5:9b240c1d5251	1616	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
yihui	5:9b240c1d5251	1617
yihui	5:9b240c1d5251	1618	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
yihui	5:9b240c1d5251	1619	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
yihui	5:9b240c1d5251	1620
yihui	5:9b240c1d5251	1621	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
yihui	5:9b240c1d5251	1622	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
yihui	5:9b240c1d5251	1623
yihui	5:9b240c1d5251	1624	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
yihui	5:9b240c1d5251	1625	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
yihui	5:9b240c1d5251	1626
yihui	5:9b240c1d5251	1627	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
yihui	5:9b240c1d5251	1628	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
yihui	5:9b240c1d5251	1629
yihui	5:9b240c1d5251	1630	/@} end of group CMSIS_CoreDebug /
yihui	5:9b240c1d5251	1631
yihui	5:9b240c1d5251	1632
yihui	5:9b240c1d5251	1633	/** \ingroup CMSIS_core_register
yihui	5:9b240c1d5251	1634	\defgroup CMSIS_core_base Core Definitions
yihui	5:9b240c1d5251	1635	\brief Definitions for base addresses, unions, and structures.
yihui	5:9b240c1d5251	1636	@{
yihui	5:9b240c1d5251	1637	*/
yihui	5:9b240c1d5251	1638
yihui	5:9b240c1d5251	1639	/* Memory mapping of Cortex-M4 Hardware */
yihui	5:9b240c1d5251	1640	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
yihui	5:9b240c1d5251	1641	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
yihui	5:9b240c1d5251	1642	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
yihui	5:9b240c1d5251	1643	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
yihui	5:9b240c1d5251	1644	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
yihui	5:9b240c1d5251	1645	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
yihui	5:9b240c1d5251	1646	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
yihui	5:9b240c1d5251	1647	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
yihui	5:9b240c1d5251	1648
yihui	5:9b240c1d5251	1649	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
yihui	5:9b240c1d5251	1650	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
yihui	5:9b240c1d5251	1651	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
yihui	5:9b240c1d5251	1652	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
yihui	5:9b240c1d5251	1653	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
yihui	5:9b240c1d5251	1654	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
yihui	5:9b240c1d5251	1655	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
yihui	5:9b240c1d5251	1656	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
yihui	5:9b240c1d5251	1657
yihui	5:9b240c1d5251	1658	#if (__MPU_PRESENT == 1)
yihui	5:9b240c1d5251	1659	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
yihui	5:9b240c1d5251	1660	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
yihui	5:9b240c1d5251	1661	#endif
yihui	5:9b240c1d5251	1662
yihui	5:9b240c1d5251	1663	#if (__FPU_PRESENT == 1)
yihui	5:9b240c1d5251	1664	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
yihui	5:9b240c1d5251	1665	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
yihui	5:9b240c1d5251	1666	#endif
yihui	5:9b240c1d5251	1667
yihui	5:9b240c1d5251	1668	/@} /
yihui	5:9b240c1d5251	1669
yihui	5:9b240c1d5251	1670
yihui	5:9b240c1d5251	1671
yihui	5:9b240c1d5251	1672	/*******************************************************************************
yihui	5:9b240c1d5251	1673	* Hardware Abstraction Layer
yihui	5:9b240c1d5251	1674	Core Function Interface contains:
yihui	5:9b240c1d5251	1675	- Core NVIC Functions
yihui	5:9b240c1d5251	1676	- Core SysTick Functions
yihui	5:9b240c1d5251	1677	- Core Debug Functions
yihui	5:9b240c1d5251	1678	- Core Register Access Functions
yihui	5:9b240c1d5251	1679	******************************************************************************/
yihui	5:9b240c1d5251	1680	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
yihui	5:9b240c1d5251	1681	*/
yihui	5:9b240c1d5251	1682
yihui	5:9b240c1d5251	1683
yihui	5:9b240c1d5251	1684
yihui	5:9b240c1d5251	1685	/* ########################## NVIC functions #################################### */
yihui	5:9b240c1d5251	1686	/** \ingroup CMSIS_Core_FunctionInterface
yihui	5:9b240c1d5251	1687	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
yihui	5:9b240c1d5251	1688	\brief Functions that manage interrupts and exceptions via the NVIC.
yihui	5:9b240c1d5251	1689	@{
yihui	5:9b240c1d5251	1690	*/
yihui	5:9b240c1d5251	1691
yihui	5:9b240c1d5251	1692	/** \brief Set Priority Grouping
yihui	5:9b240c1d5251	1693
yihui	5:9b240c1d5251	1694	The function sets the priority grouping field using the required unlock sequence.
yihui	5:9b240c1d5251	1695	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
yihui	5:9b240c1d5251	1696	Only values from 0..7 are used.
yihui	5:9b240c1d5251	1697	In case of a conflict between priority grouping and available
yihui	5:9b240c1d5251	1698	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
yihui	5:9b240c1d5251	1699
yihui	5:9b240c1d5251	1700	\param [in] PriorityGroup Priority grouping field.
yihui	5:9b240c1d5251	1701	*/
yihui	5:9b240c1d5251	1702	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
yihui	5:9b240c1d5251	1703	{
yihui	5:9b240c1d5251	1704	uint32_t reg_value;
yihui	5:9b240c1d5251	1705	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
yihui	5:9b240c1d5251	1706
yihui	5:9b240c1d5251	1707	reg_value = SCB->AIRCR; /* read old register configuration */
yihui	5:9b240c1d5251	1708	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
yihui	5:9b240c1d5251	1709	reg_value = (reg_value \|
yihui	5:9b240c1d5251	1710	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
yihui	5:9b240c1d5251	1711	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
yihui	5:9b240c1d5251	1712	SCB->AIRCR = reg_value;
yihui	5:9b240c1d5251	1713	}
yihui	5:9b240c1d5251	1714
yihui	5:9b240c1d5251	1715
yihui	5:9b240c1d5251	1716	/** \brief Get Priority Grouping
yihui	5:9b240c1d5251	1717
yihui	5:9b240c1d5251	1718	The function reads the priority grouping field from the NVIC Interrupt Controller.
yihui	5:9b240c1d5251	1719
yihui	5:9b240c1d5251	1720	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
yihui	5:9b240c1d5251	1721	*/
yihui	5:9b240c1d5251	1722	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
yihui	5:9b240c1d5251	1723	{
yihui	5:9b240c1d5251	1724	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
yihui	5:9b240c1d5251	1725	}
yihui	5:9b240c1d5251	1726
yihui	5:9b240c1d5251	1727
yihui	5:9b240c1d5251	1728	/** \brief Enable External Interrupt
yihui	5:9b240c1d5251	1729
yihui	5:9b240c1d5251	1730	The function enables a device-specific interrupt in the NVIC interrupt controller.
yihui	5:9b240c1d5251	1731
yihui	5:9b240c1d5251	1732	\param [in] IRQn External interrupt number. Value cannot be negative.
yihui	5:9b240c1d5251	1733	*/
yihui	5:9b240c1d5251	1734	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
yihui	5:9b240c1d5251	1735	{
yihui	5:9b240c1d5251	1736	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
yihui	5:9b240c1d5251	1737	}
yihui	5:9b240c1d5251	1738
yihui	5:9b240c1d5251	1739
yihui	5:9b240c1d5251	1740	/** \brief Disable External Interrupt
yihui	5:9b240c1d5251	1741
yihui	5:9b240c1d5251	1742	The function disables a device-specific interrupt in the NVIC interrupt controller.
yihui	5:9b240c1d5251	1743
yihui	5:9b240c1d5251	1744	\param [in] IRQn External interrupt number. Value cannot be negative.
yihui	5:9b240c1d5251	1745	*/
yihui	5:9b240c1d5251	1746	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
yihui	5:9b240c1d5251	1747	{
yihui	5:9b240c1d5251	1748	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
yihui	5:9b240c1d5251	1749	}
yihui	5:9b240c1d5251	1750
yihui	5:9b240c1d5251	1751
yihui	5:9b240c1d5251	1752	/** \brief Get Pending Interrupt
yihui	5:9b240c1d5251	1753
yihui	5:9b240c1d5251	1754	The function reads the pending register in the NVIC and returns the pending bit
yihui	5:9b240c1d5251	1755	for the specified interrupt.
yihui	5:9b240c1d5251	1756
yihui	5:9b240c1d5251	1757	\param [in] IRQn Interrupt number.
yihui	5:9b240c1d5251	1758
yihui	5:9b240c1d5251	1759	\return 0 Interrupt status is not pending.
yihui	5:9b240c1d5251	1760	\return 1 Interrupt status is pending.
yihui	5:9b240c1d5251	1761	*/
yihui	5:9b240c1d5251	1762	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
yihui	5:9b240c1d5251	1763	{
yihui	5:9b240c1d5251	1764	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
yihui	5:9b240c1d5251	1765	}
yihui	5:9b240c1d5251	1766
yihui	5:9b240c1d5251	1767
yihui	5:9b240c1d5251	1768	/** \brief Set Pending Interrupt
yihui	5:9b240c1d5251	1769
yihui	5:9b240c1d5251	1770	The function sets the pending bit of an external interrupt.
yihui	5:9b240c1d5251	1771
yihui	5:9b240c1d5251	1772	\param [in] IRQn Interrupt number. Value cannot be negative.
yihui	5:9b240c1d5251	1773	*/
yihui	5:9b240c1d5251	1774	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
yihui	5:9b240c1d5251	1775	{
yihui	5:9b240c1d5251	1776	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
yihui	5:9b240c1d5251	1777	}
yihui	5:9b240c1d5251	1778
yihui	5:9b240c1d5251	1779
yihui	5:9b240c1d5251	1780	/** \brief Clear Pending Interrupt
yihui	5:9b240c1d5251	1781
yihui	5:9b240c1d5251	1782	The function clears the pending bit of an external interrupt.
yihui	5:9b240c1d5251	1783
yihui	5:9b240c1d5251	1784	\param [in] IRQn External interrupt number. Value cannot be negative.
yihui	5:9b240c1d5251	1785	*/
yihui	5:9b240c1d5251	1786	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
yihui	5:9b240c1d5251	1787	{
yihui	5:9b240c1d5251	1788	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
yihui	5:9b240c1d5251	1789	}
yihui	5:9b240c1d5251	1790
yihui	5:9b240c1d5251	1791
yihui	5:9b240c1d5251	1792	/** \brief Get Active Interrupt
yihui	5:9b240c1d5251	1793
yihui	5:9b240c1d5251	1794	The function reads the active register in NVIC and returns the active bit.
yihui	5:9b240c1d5251	1795
yihui	5:9b240c1d5251	1796	\param [in] IRQn Interrupt number.
yihui	5:9b240c1d5251	1797
yihui	5:9b240c1d5251	1798	\return 0 Interrupt status is not active.
yihui	5:9b240c1d5251	1799	\return 1 Interrupt status is active.
yihui	5:9b240c1d5251	1800	*/
yihui	5:9b240c1d5251	1801	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
yihui	5:9b240c1d5251	1802	{
yihui	5:9b240c1d5251	1803	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
yihui	5:9b240c1d5251	1804	}
yihui	5:9b240c1d5251	1805
yihui	5:9b240c1d5251	1806
yihui	5:9b240c1d5251	1807	/** \brief Set Interrupt Priority
yihui	5:9b240c1d5251	1808
yihui	5:9b240c1d5251	1809	The function sets the priority of an interrupt.
yihui	5:9b240c1d5251	1810
yihui	5:9b240c1d5251	1811	\note The priority cannot be set for every core interrupt.
yihui	5:9b240c1d5251	1812
yihui	5:9b240c1d5251	1813	\param [in] IRQn Interrupt number.
yihui	5:9b240c1d5251	1814	\param [in] priority Priority to set.
yihui	5:9b240c1d5251	1815	*/
yihui	5:9b240c1d5251	1816	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
yihui	5:9b240c1d5251	1817	{
yihui	5:9b240c1d5251	1818	if((int32_t)IRQn < 0) {
yihui	5:9b240c1d5251	1819	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
yihui	5:9b240c1d5251	1820	}
yihui	5:9b240c1d5251	1821	else {
yihui	5:9b240c1d5251	1822	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
yihui	5:9b240c1d5251	1823	}
yihui	5:9b240c1d5251	1824	}
yihui	5:9b240c1d5251	1825
yihui	5:9b240c1d5251	1826
yihui	5:9b240c1d5251	1827	/** \brief Get Interrupt Priority
yihui	5:9b240c1d5251	1828
yihui	5:9b240c1d5251	1829	The function reads the priority of an interrupt. The interrupt
yihui	5:9b240c1d5251	1830	number can be positive to specify an external (device specific)
yihui	5:9b240c1d5251	1831	interrupt, or negative to specify an internal (core) interrupt.
yihui	5:9b240c1d5251	1832
yihui	5:9b240c1d5251	1833
yihui	5:9b240c1d5251	1834	\param [in] IRQn Interrupt number.
yihui	5:9b240c1d5251	1835	\return Interrupt Priority. Value is aligned automatically to the implemented
yihui	5:9b240c1d5251	1836	priority bits of the microcontroller.
yihui	5:9b240c1d5251	1837	*/
yihui	5:9b240c1d5251	1838	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
yihui	5:9b240c1d5251	1839	{
yihui	5:9b240c1d5251	1840
yihui	5:9b240c1d5251	1841	if((int32_t)IRQn < 0) {
yihui	5:9b240c1d5251	1842	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
yihui	5:9b240c1d5251	1843	}
yihui	5:9b240c1d5251	1844	else {
yihui	5:9b240c1d5251	1845	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
yihui	5:9b240c1d5251	1846	}
yihui	5:9b240c1d5251	1847	}
yihui	5:9b240c1d5251	1848
yihui	5:9b240c1d5251	1849
yihui	5:9b240c1d5251	1850	/** \brief Encode Priority
yihui	5:9b240c1d5251	1851
yihui	5:9b240c1d5251	1852	The function encodes the priority for an interrupt with the given priority group,
yihui	5:9b240c1d5251	1853	preemptive priority value, and subpriority value.
yihui	5:9b240c1d5251	1854	In case of a conflict between priority grouping and available
yihui	5:9b240c1d5251	1855	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
yihui	5:9b240c1d5251	1856
yihui	5:9b240c1d5251	1857	\param [in] PriorityGroup Used priority group.
yihui	5:9b240c1d5251	1858	\param [in] PreemptPriority Preemptive priority value (starting from 0).
yihui	5:9b240c1d5251	1859	\param [in] SubPriority Subpriority value (starting from 0).
yihui	5:9b240c1d5251	1860	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
yihui	5:9b240c1d5251	1861	*/
yihui	5:9b240c1d5251	1862	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
yihui	5:9b240c1d5251	1863	{
yihui	5:9b240c1d5251	1864	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
yihui	5:9b240c1d5251	1865	uint32_t PreemptPriorityBits;
yihui	5:9b240c1d5251	1866	uint32_t SubPriorityBits;
yihui	5:9b240c1d5251	1867
yihui	5:9b240c1d5251	1868	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
yihui	5:9b240c1d5251	1869	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
yihui	5:9b240c1d5251	1870
yihui	5:9b240c1d5251	1871	return (
yihui	5:9b240c1d5251	1872	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
yihui	5:9b240c1d5251	1873	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
yihui	5:9b240c1d5251	1874	);
yihui	5:9b240c1d5251	1875	}
yihui	5:9b240c1d5251	1876
yihui	5:9b240c1d5251	1877
yihui	5:9b240c1d5251	1878	/** \brief Decode Priority
yihui	5:9b240c1d5251	1879
yihui	5:9b240c1d5251	1880	The function decodes an interrupt priority value with a given priority group to
yihui	5:9b240c1d5251	1881	preemptive priority value and subpriority value.
yihui	5:9b240c1d5251	1882	In case of a conflict between priority grouping and available
yihui	5:9b240c1d5251	1883	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
yihui	5:9b240c1d5251	1884
yihui	5:9b240c1d5251	1885	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
yihui	5:9b240c1d5251	1886	\param [in] PriorityGroup Used priority group.
yihui	5:9b240c1d5251	1887	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
yihui	5:9b240c1d5251	1888	\param [out] pSubPriority Subpriority value (starting from 0).
yihui	5:9b240c1d5251	1889	*/
yihui	5:9b240c1d5251	1890	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
yihui	5:9b240c1d5251	1891	{
yihui	5:9b240c1d5251	1892	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
yihui	5:9b240c1d5251	1893	uint32_t PreemptPriorityBits;
yihui	5:9b240c1d5251	1894	uint32_t SubPriorityBits;
yihui	5:9b240c1d5251	1895
yihui	5:9b240c1d5251	1896	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
yihui	5:9b240c1d5251	1897	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
yihui	5:9b240c1d5251	1898
yihui	5:9b240c1d5251	1899	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
yihui	5:9b240c1d5251	1900	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
yihui	5:9b240c1d5251	1901	}
yihui	5:9b240c1d5251	1902
yihui	5:9b240c1d5251	1903
yihui	5:9b240c1d5251	1904	/** \brief System Reset
yihui	5:9b240c1d5251	1905
yihui	5:9b240c1d5251	1906	The function initiates a system reset request to reset the MCU.
yihui	5:9b240c1d5251	1907	*/
yihui	5:9b240c1d5251	1908	__STATIC_INLINE void NVIC_SystemReset(void)
yihui	5:9b240c1d5251	1909	{
yihui	5:9b240c1d5251	1910	__DSB(); /* Ensure all outstanding memory accesses included
yihui	5:9b240c1d5251	1911	buffered write are completed before reset */
yihui	5:9b240c1d5251	1912	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
yihui	5:9b240c1d5251	1913	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
yihui	5:9b240c1d5251	1914	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
yihui	5:9b240c1d5251	1915	__DSB(); /* Ensure completion of memory access */
yihui	5:9b240c1d5251	1916	while(1) { __NOP(); } /* wait until reset */
yihui	5:9b240c1d5251	1917	}
yihui	5:9b240c1d5251	1918
yihui	5:9b240c1d5251	1919	/@} end of CMSIS_Core_NVICFunctions /
yihui	5:9b240c1d5251	1920
yihui	5:9b240c1d5251	1921
yihui	5:9b240c1d5251	1922	/* ########################## FPU functions #################################### */
yihui	5:9b240c1d5251	1923	/** \ingroup CMSIS_Core_FunctionInterface
yihui	5:9b240c1d5251	1924	\defgroup CMSIS_Core_FpuFunctions FPU Functions
yihui	5:9b240c1d5251	1925	\brief Function that provides FPU type.
yihui	5:9b240c1d5251	1926	@{
yihui	5:9b240c1d5251	1927	*/
yihui	5:9b240c1d5251	1928
yihui	5:9b240c1d5251	1929	/**
yihui	5:9b240c1d5251	1930	\fn uint32_t SCB_GetFPUType(void)
yihui	5:9b240c1d5251	1931	\brief get FPU type
yihui	5:9b240c1d5251	1932	\returns
yihui	5:9b240c1d5251	1933	- \b 0: No FPU
yihui	5:9b240c1d5251	1934	- \b 1: Single precision FPU
yihui	5:9b240c1d5251	1935	- \b 2: Double + Single precision FPU
yihui	5:9b240c1d5251	1936	*/
yihui	5:9b240c1d5251	1937	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
yihui	5:9b240c1d5251	1938	{
yihui	5:9b240c1d5251	1939	uint32_t mvfr0;
yihui	5:9b240c1d5251	1940
yihui	5:9b240c1d5251	1941	mvfr0 = SCB->MVFR0;
yihui	5:9b240c1d5251	1942	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
yihui	5:9b240c1d5251	1943	return 2UL; // Double + Single precision FPU
yihui	5:9b240c1d5251	1944	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
yihui	5:9b240c1d5251	1945	return 1UL; // Single precision FPU
yihui	5:9b240c1d5251	1946	} else {
yihui	5:9b240c1d5251	1947	return 0UL; // No FPU
yihui	5:9b240c1d5251	1948	}
yihui	5:9b240c1d5251	1949	}
yihui	5:9b240c1d5251	1950
yihui	5:9b240c1d5251	1951
yihui	5:9b240c1d5251	1952	/@} end of CMSIS_Core_FpuFunctions /
yihui	5:9b240c1d5251	1953
yihui	5:9b240c1d5251	1954
yihui	5:9b240c1d5251	1955
yihui	5:9b240c1d5251	1956	/* ########################## Cache functions #################################### */
yihui	5:9b240c1d5251	1957	/** \ingroup CMSIS_Core_FunctionInterface
yihui	5:9b240c1d5251	1958	\defgroup CMSIS_Core_CacheFunctions Cache Functions
yihui	5:9b240c1d5251	1959	\brief Functions that configure Instruction and Data cache.
yihui	5:9b240c1d5251	1960	@{
yihui	5:9b240c1d5251	1961	*/
yihui	5:9b240c1d5251	1962
yihui	5:9b240c1d5251	1963	/* Cache Size ID Register Macros */
yihui	5:9b240c1d5251	1964	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
yihui	5:9b240c1d5251	1965	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
yihui	5:9b240c1d5251	1966	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
yihui	5:9b240c1d5251	1967
yihui	5:9b240c1d5251	1968
yihui	5:9b240c1d5251	1969	/** \brief Enable I-Cache
yihui	5:9b240c1d5251	1970
yihui	5:9b240c1d5251	1971	The function turns on I-Cache
yihui	5:9b240c1d5251	1972	*/
yihui	5:9b240c1d5251	1973	__STATIC_INLINE void SCB_EnableICache (void)
yihui	5:9b240c1d5251	1974	{
yihui	5:9b240c1d5251	1975	#if (__ICACHE_PRESENT == 1)
yihui	5:9b240c1d5251	1976	__DSB();
yihui	5:9b240c1d5251	1977	__ISB();
yihui	5:9b240c1d5251	1978	SCB->ICIALLU = 0UL; // invalidate I-Cache
yihui	5:9b240c1d5251	1979	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
yihui	5:9b240c1d5251	1980	__DSB();
yihui	5:9b240c1d5251	1981	__ISB();
yihui	5:9b240c1d5251	1982	#endif
yihui	5:9b240c1d5251	1983	}
yihui	5:9b240c1d5251	1984
yihui	5:9b240c1d5251	1985
yihui	5:9b240c1d5251	1986	/** \brief Disable I-Cache
yihui	5:9b240c1d5251	1987
yihui	5:9b240c1d5251	1988	The function turns off I-Cache
yihui	5:9b240c1d5251	1989	*/
yihui	5:9b240c1d5251	1990	__STATIC_INLINE void SCB_DisableICache (void)
yihui	5:9b240c1d5251	1991	{
yihui	5:9b240c1d5251	1992	#if (__ICACHE_PRESENT == 1)
yihui	5:9b240c1d5251	1993	__DSB();
yihui	5:9b240c1d5251	1994	__ISB();
yihui	5:9b240c1d5251	1995	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
yihui	5:9b240c1d5251	1996	SCB->ICIALLU = 0UL; // invalidate I-Cache
yihui	5:9b240c1d5251	1997	__DSB();
yihui	5:9b240c1d5251	1998	__ISB();
yihui	5:9b240c1d5251	1999	#endif
yihui	5:9b240c1d5251	2000	}
yihui	5:9b240c1d5251	2001
yihui	5:9b240c1d5251	2002
yihui	5:9b240c1d5251	2003	/** \brief Invalidate I-Cache
yihui	5:9b240c1d5251	2004
yihui	5:9b240c1d5251	2005	The function invalidates I-Cache
yihui	5:9b240c1d5251	2006	*/
yihui	5:9b240c1d5251	2007	__STATIC_INLINE void SCB_InvalidateICache (void)
yihui	5:9b240c1d5251	2008	{
yihui	5:9b240c1d5251	2009	#if (__ICACHE_PRESENT == 1)
yihui	5:9b240c1d5251	2010	__DSB();
yihui	5:9b240c1d5251	2011	__ISB();
yihui	5:9b240c1d5251	2012	SCB->ICIALLU = 0UL;
yihui	5:9b240c1d5251	2013	__DSB();
yihui	5:9b240c1d5251	2014	__ISB();
yihui	5:9b240c1d5251	2015	#endif
yihui	5:9b240c1d5251	2016	}
yihui	5:9b240c1d5251	2017
yihui	5:9b240c1d5251	2018
yihui	5:9b240c1d5251	2019	/** \brief Enable D-Cache
yihui	5:9b240c1d5251	2020
yihui	5:9b240c1d5251	2021	The function turns on D-Cache
yihui	5:9b240c1d5251	2022	*/
yihui	5:9b240c1d5251	2023	__STATIC_INLINE void SCB_EnableDCache (void)
yihui	5:9b240c1d5251	2024	{
yihui	5:9b240c1d5251	2025	#if (__DCACHE_PRESENT == 1)
yihui	5:9b240c1d5251	2026	uint32_t ccsidr, sshift, wshift, sw;
yihui	5:9b240c1d5251	2027	uint32_t sets, ways;
yihui	5:9b240c1d5251	2028
yihui	5:9b240c1d5251	2029	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
yihui	5:9b240c1d5251	2030	ccsidr = SCB->CCSIDR;
yihui	5:9b240c1d5251	2031	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
yihui	5:9b240c1d5251	2032	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
yihui	5:9b240c1d5251	2033	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
yihui	5:9b240c1d5251	2034	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
yihui	5:9b240c1d5251	2035
yihui	5:9b240c1d5251	2036	__DSB();
yihui	5:9b240c1d5251	2037
yihui	5:9b240c1d5251	2038	do { // invalidate D-Cache
yihui	5:9b240c1d5251	2039	uint32_t tmpways = ways;
yihui	5:9b240c1d5251	2040	do {
yihui	5:9b240c1d5251	2041	sw = ((tmpways << wshift) \| (sets << sshift));
yihui	5:9b240c1d5251	2042	SCB->DCISW = sw;
yihui	5:9b240c1d5251	2043	} while(tmpways--);
yihui	5:9b240c1d5251	2044	} while(sets--);
yihui	5:9b240c1d5251	2045	__DSB();
yihui	5:9b240c1d5251	2046
yihui	5:9b240c1d5251	2047	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
yihui	5:9b240c1d5251	2048
yihui	5:9b240c1d5251	2049	__DSB();
yihui	5:9b240c1d5251	2050	__ISB();
yihui	5:9b240c1d5251	2051	#endif
yihui	5:9b240c1d5251	2052	}
yihui	5:9b240c1d5251	2053
yihui	5:9b240c1d5251	2054
yihui	5:9b240c1d5251	2055	/** \brief Disable D-Cache
yihui	5:9b240c1d5251	2056
yihui	5:9b240c1d5251	2057	The function turns off D-Cache
yihui	5:9b240c1d5251	2058	*/
yihui	5:9b240c1d5251	2059	__STATIC_INLINE void SCB_DisableDCache (void)
yihui	5:9b240c1d5251	2060	{
yihui	5:9b240c1d5251	2061	#if (__DCACHE_PRESENT == 1)
yihui	5:9b240c1d5251	2062	uint32_t ccsidr, sshift, wshift, sw;
yihui	5:9b240c1d5251	2063	uint32_t sets, ways;
yihui	5:9b240c1d5251	2064
yihui	5:9b240c1d5251	2065	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
yihui	5:9b240c1d5251	2066	ccsidr = SCB->CCSIDR;
yihui	5:9b240c1d5251	2067	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
yihui	5:9b240c1d5251	2068	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
yihui	5:9b240c1d5251	2069	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
yihui	5:9b240c1d5251	2070	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
yihui	5:9b240c1d5251	2071
yihui	5:9b240c1d5251	2072	__DSB();
yihui	5:9b240c1d5251	2073
yihui	5:9b240c1d5251	2074	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
yihui	5:9b240c1d5251	2075
yihui	5:9b240c1d5251	2076	do { // clean & invalidate D-Cache
yihui	5:9b240c1d5251	2077	uint32_t tmpways = ways;
yihui	5:9b240c1d5251	2078	do {
yihui	5:9b240c1d5251	2079	sw = ((tmpways << wshift) \| (sets << sshift));
yihui	5:9b240c1d5251	2080	SCB->DCCISW = sw;
yihui	5:9b240c1d5251	2081	} while(tmpways--);
yihui	5:9b240c1d5251	2082	} while(sets--);
yihui	5:9b240c1d5251	2083
yihui	5:9b240c1d5251	2084
yihui	5:9b240c1d5251	2085	__DSB();
yihui	5:9b240c1d5251	2086	__ISB();
yihui	5:9b240c1d5251	2087	#endif
yihui	5:9b240c1d5251	2088	}
yihui	5:9b240c1d5251	2089
yihui	5:9b240c1d5251	2090
yihui	5:9b240c1d5251	2091	/** \brief Invalidate D-Cache
yihui	5:9b240c1d5251	2092
yihui	5:9b240c1d5251	2093	The function invalidates D-Cache
yihui	5:9b240c1d5251	2094	*/
yihui	5:9b240c1d5251	2095	__STATIC_INLINE void SCB_InvalidateDCache (void)
yihui	5:9b240c1d5251	2096	{
yihui	5:9b240c1d5251	2097	#if (__DCACHE_PRESENT == 1)
yihui	5:9b240c1d5251	2098	uint32_t ccsidr, sshift, wshift, sw;
yihui	5:9b240c1d5251	2099	uint32_t sets, ways;
yihui	5:9b240c1d5251	2100
yihui	5:9b240c1d5251	2101	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
yihui	5:9b240c1d5251	2102	ccsidr = SCB->CCSIDR;
yihui	5:9b240c1d5251	2103	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
yihui	5:9b240c1d5251	2104	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
yihui	5:9b240c1d5251	2105	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
yihui	5:9b240c1d5251	2106	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
yihui	5:9b240c1d5251	2107
yihui	5:9b240c1d5251	2108	__DSB();
yihui	5:9b240c1d5251	2109
yihui	5:9b240c1d5251	2110	do { // invalidate D-Cache
yihui	5:9b240c1d5251	2111	uint32_t tmpways = ways;
yihui	5:9b240c1d5251	2112	do {
yihui	5:9b240c1d5251	2113	sw = ((tmpways << wshift) \| (sets << sshift));
yihui	5:9b240c1d5251	2114	SCB->DCISW = sw;
yihui	5:9b240c1d5251	2115	} while(tmpways--);
yihui	5:9b240c1d5251	2116	} while(sets--);
yihui	5:9b240c1d5251	2117
yihui	5:9b240c1d5251	2118	__DSB();
yihui	5:9b240c1d5251	2119	__ISB();
yihui	5:9b240c1d5251	2120	#endif
yihui	5:9b240c1d5251	2121	}
yihui	5:9b240c1d5251	2122
yihui	5:9b240c1d5251	2123
yihui	5:9b240c1d5251	2124	/** \brief Clean D-Cache
yihui	5:9b240c1d5251	2125
yihui	5:9b240c1d5251	2126	The function cleans D-Cache
yihui	5:9b240c1d5251	2127	*/
yihui	5:9b240c1d5251	2128	__STATIC_INLINE void SCB_CleanDCache (void)
yihui	5:9b240c1d5251	2129	{
yihui	5:9b240c1d5251	2130	#if (__DCACHE_PRESENT == 1)
yihui	5:9b240c1d5251	2131	uint32_t ccsidr, sshift, wshift, sw;
yihui	5:9b240c1d5251	2132	uint32_t sets, ways;
yihui	5:9b240c1d5251	2133
yihui	5:9b240c1d5251	2134	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
yihui	5:9b240c1d5251	2135	ccsidr = SCB->CCSIDR;
yihui	5:9b240c1d5251	2136	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
yihui	5:9b240c1d5251	2137	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
yihui	5:9b240c1d5251	2138	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
yihui	5:9b240c1d5251	2139	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
yihui	5:9b240c1d5251	2140
yihui	5:9b240c1d5251	2141	__DSB();
yihui	5:9b240c1d5251	2142
yihui	5:9b240c1d5251	2143	do { // clean D-Cache
yihui	5:9b240c1d5251	2144	uint32_t tmpways = ways;
yihui	5:9b240c1d5251	2145	do {
yihui	5:9b240c1d5251	2146	sw = ((tmpways << wshift) \| (sets << sshift));
yihui	5:9b240c1d5251	2147	SCB->DCCSW = sw;
yihui	5:9b240c1d5251	2148	} while(tmpways--);
yihui	5:9b240c1d5251	2149	} while(sets--);
yihui	5:9b240c1d5251	2150
yihui	5:9b240c1d5251	2151	__DSB();
yihui	5:9b240c1d5251	2152	__ISB();
yihui	5:9b240c1d5251	2153	#endif
yihui	5:9b240c1d5251	2154	}
yihui	5:9b240c1d5251	2155
yihui	5:9b240c1d5251	2156
yihui	5:9b240c1d5251	2157	/** \brief Clean & Invalidate D-Cache
yihui	5:9b240c1d5251	2158
yihui	5:9b240c1d5251	2159	The function cleans and Invalidates D-Cache
yihui	5:9b240c1d5251	2160	*/
yihui	5:9b240c1d5251	2161	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
yihui	5:9b240c1d5251	2162	{
yihui	5:9b240c1d5251	2163	#if (__DCACHE_PRESENT == 1)
yihui	5:9b240c1d5251	2164	uint32_t ccsidr, sshift, wshift, sw;
yihui	5:9b240c1d5251	2165	uint32_t sets, ways;
yihui	5:9b240c1d5251	2166
yihui	5:9b240c1d5251	2167	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
yihui	5:9b240c1d5251	2168	ccsidr = SCB->CCSIDR;
yihui	5:9b240c1d5251	2169	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
yihui	5:9b240c1d5251	2170	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
yihui	5:9b240c1d5251	2171	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
yihui	5:9b240c1d5251	2172	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
yihui	5:9b240c1d5251	2173
yihui	5:9b240c1d5251	2174	__DSB();
yihui	5:9b240c1d5251	2175
yihui	5:9b240c1d5251	2176	do { // clean & invalidate D-Cache
yihui	5:9b240c1d5251	2177	uint32_t tmpways = ways;
yihui	5:9b240c1d5251	2178	do {
yihui	5:9b240c1d5251	2179	sw = ((tmpways << wshift) \| (sets << sshift));
yihui	5:9b240c1d5251	2180	SCB->DCCISW = sw;
yihui	5:9b240c1d5251	2181	} while(tmpways--);
yihui	5:9b240c1d5251	2182	} while(sets--);
yihui	5:9b240c1d5251	2183
yihui	5:9b240c1d5251	2184	__DSB();
yihui	5:9b240c1d5251	2185	__ISB();
yihui	5:9b240c1d5251	2186	#endif
yihui	5:9b240c1d5251	2187	}
yihui	5:9b240c1d5251	2188
yihui	5:9b240c1d5251	2189
yihui	5:9b240c1d5251	2190	/**
yihui	5:9b240c1d5251	2191	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
yihui	5:9b240c1d5251	2192	\brief D-Cache Invalidate by address
yihui	5:9b240c1d5251	2193	\param[in] addr address (aligned to 32-byte boundary)
yihui	5:9b240c1d5251	2194	\param[in] dsize size of memory block (in number of bytes)
yihui	5:9b240c1d5251	2195	*/
yihui	5:9b240c1d5251	2196	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
yihui	5:9b240c1d5251	2197	{
yihui	5:9b240c1d5251	2198	#if (__DCACHE_PRESENT == 1)
yihui	5:9b240c1d5251	2199	int32_t op_size = dsize;
yihui	5:9b240c1d5251	2200	uint32_t op_addr = (uint32_t)addr;
yihui	5:9b240c1d5251	2201	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
yihui	5:9b240c1d5251	2202
yihui	5:9b240c1d5251	2203	__DSB();
yihui	5:9b240c1d5251	2204
yihui	5:9b240c1d5251	2205	while (op_size > 0) {
yihui	5:9b240c1d5251	2206	SCB->DCIMVAC = op_addr;
yihui	5:9b240c1d5251	2207	op_addr += linesize;
yihui	5:9b240c1d5251	2208	op_size -= (int32_t)linesize;
yihui	5:9b240c1d5251	2209	}
yihui	5:9b240c1d5251	2210
yihui	5:9b240c1d5251	2211	__DSB();
yihui	5:9b240c1d5251	2212	__ISB();
yihui	5:9b240c1d5251	2213	#endif
yihui	5:9b240c1d5251	2214	}
yihui	5:9b240c1d5251	2215
yihui	5:9b240c1d5251	2216
yihui	5:9b240c1d5251	2217	/**
yihui	5:9b240c1d5251	2218	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
yihui	5:9b240c1d5251	2219	\brief D-Cache Clean by address
yihui	5:9b240c1d5251	2220	\param[in] addr address (aligned to 32-byte boundary)
yihui	5:9b240c1d5251	2221	\param[in] dsize size of memory block (in number of bytes)
yihui	5:9b240c1d5251	2222	*/
yihui	5:9b240c1d5251	2223	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
yihui	5:9b240c1d5251	2224	{
yihui	5:9b240c1d5251	2225	#if (__DCACHE_PRESENT == 1)
yihui	5:9b240c1d5251	2226	int32_t op_size = dsize;
yihui	5:9b240c1d5251	2227	uint32_t op_addr = (uint32_t) addr;
yihui	5:9b240c1d5251	2228	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
yihui	5:9b240c1d5251	2229
yihui	5:9b240c1d5251	2230	__DSB();
yihui	5:9b240c1d5251	2231
yihui	5:9b240c1d5251	2232	while (op_size > 0) {
yihui	5:9b240c1d5251	2233	SCB->DCCMVAC = op_addr;
yihui	5:9b240c1d5251	2234	op_addr += linesize;
yihui	5:9b240c1d5251	2235	op_size -= (int32_t)linesize;
yihui	5:9b240c1d5251	2236	}
yihui	5:9b240c1d5251	2237
yihui	5:9b240c1d5251	2238	__DSB();
yihui	5:9b240c1d5251	2239	__ISB();
yihui	5:9b240c1d5251	2240	#endif
yihui	5:9b240c1d5251	2241	}
yihui	5:9b240c1d5251	2242
yihui	5:9b240c1d5251	2243
yihui	5:9b240c1d5251	2244	/**
yihui	5:9b240c1d5251	2245	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
yihui	5:9b240c1d5251	2246	\brief D-Cache Clean and Invalidate by address
yihui	5:9b240c1d5251	2247	\param[in] addr address (aligned to 32-byte boundary)
yihui	5:9b240c1d5251	2248	\param[in] dsize size of memory block (in number of bytes)
yihui	5:9b240c1d5251	2249	*/
yihui	5:9b240c1d5251	2250	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
yihui	5:9b240c1d5251	2251	{
yihui	5:9b240c1d5251	2252	#if (__DCACHE_PRESENT == 1)
yihui	5:9b240c1d5251	2253	int32_t op_size = dsize;
yihui	5:9b240c1d5251	2254	uint32_t op_addr = (uint32_t) addr;
yihui	5:9b240c1d5251	2255	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
yihui	5:9b240c1d5251	2256
yihui	5:9b240c1d5251	2257	__DSB();
yihui	5:9b240c1d5251	2258
yihui	5:9b240c1d5251	2259	while (op_size > 0) {
yihui	5:9b240c1d5251	2260	SCB->DCCIMVAC = op_addr;
yihui	5:9b240c1d5251	2261	op_addr += linesize;
yihui	5:9b240c1d5251	2262	op_size -= (int32_t)linesize;
yihui	5:9b240c1d5251	2263	}
yihui	5:9b240c1d5251	2264
yihui	5:9b240c1d5251	2265	__DSB();
yihui	5:9b240c1d5251	2266	__ISB();
yihui	5:9b240c1d5251	2267	#endif
yihui	5:9b240c1d5251	2268	}
yihui	5:9b240c1d5251	2269
yihui	5:9b240c1d5251	2270
yihui	5:9b240c1d5251	2271	/@} end of CMSIS_Core_CacheFunctions /
yihui	5:9b240c1d5251	2272
yihui	5:9b240c1d5251	2273
yihui	5:9b240c1d5251	2274
yihui	5:9b240c1d5251	2275	/* ################################## SysTick function ############################################ */
yihui	5:9b240c1d5251	2276	/** \ingroup CMSIS_Core_FunctionInterface
yihui	5:9b240c1d5251	2277	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
yihui	5:9b240c1d5251	2278	\brief Functions that configure the System.
yihui	5:9b240c1d5251	2279	@{
yihui	5:9b240c1d5251	2280	*/
yihui	5:9b240c1d5251	2281
yihui	5:9b240c1d5251	2282	#if (__Vendor_SysTickConfig == 0)
yihui	5:9b240c1d5251	2283
yihui	5:9b240c1d5251	2284	/** \brief System Tick Configuration
yihui	5:9b240c1d5251	2285
yihui	5:9b240c1d5251	2286	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
yihui	5:9b240c1d5251	2287	Counter is in free running mode to generate periodic interrupts.
yihui	5:9b240c1d5251	2288
yihui	5:9b240c1d5251	2289	\param [in] ticks Number of ticks between two interrupts.
yihui	5:9b240c1d5251	2290
yihui	5:9b240c1d5251	2291	\return 0 Function succeeded.
yihui	5:9b240c1d5251	2292	\return 1 Function failed.
yihui	5:9b240c1d5251	2293
yihui	5:9b240c1d5251	2294	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
yihui	5:9b240c1d5251	2295	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
yihui	5:9b240c1d5251	2296	must contain a vendor-specific implementation of this function.
yihui	5:9b240c1d5251	2297
yihui	5:9b240c1d5251	2298	*/
yihui	5:9b240c1d5251	2299	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
yihui	5:9b240c1d5251	2300	{
yihui	5:9b240c1d5251	2301	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
yihui	5:9b240c1d5251	2302
yihui	5:9b240c1d5251	2303	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
yihui	5:9b240c1d5251	2304	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
yihui	5:9b240c1d5251	2305	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
yihui	5:9b240c1d5251	2306	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
yihui	5:9b240c1d5251	2307	SysTick_CTRL_TICKINT_Msk \|
yihui	5:9b240c1d5251	2308	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
yihui	5:9b240c1d5251	2309	return (0UL); /* Function successful */
yihui	5:9b240c1d5251	2310	}
yihui	5:9b240c1d5251	2311
yihui	5:9b240c1d5251	2312	#endif
yihui	5:9b240c1d5251	2313
yihui	5:9b240c1d5251	2314	/@} end of CMSIS_Core_SysTickFunctions /
yihui	5:9b240c1d5251	2315
yihui	5:9b240c1d5251	2316
yihui	5:9b240c1d5251	2317
yihui	5:9b240c1d5251	2318	/* ##################################### Debug In/Output function ########################################### */
yihui	5:9b240c1d5251	2319	/** \ingroup CMSIS_Core_FunctionInterface
yihui	5:9b240c1d5251	2320	\defgroup CMSIS_core_DebugFunctions ITM Functions
yihui	5:9b240c1d5251	2321	\brief Functions that access the ITM debug interface.
yihui	5:9b240c1d5251	2322	@{
yihui	5:9b240c1d5251	2323	*/
yihui	5:9b240c1d5251	2324
yihui	5:9b240c1d5251	2325	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
yihui	5:9b240c1d5251	2326	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
yihui	5:9b240c1d5251	2327
yihui	5:9b240c1d5251	2328
yihui	5:9b240c1d5251	2329	/** \brief ITM Send Character
yihui	5:9b240c1d5251	2330
yihui	5:9b240c1d5251	2331	The function transmits a character via the ITM channel 0, and
yihui	5:9b240c1d5251	2332	\li Just returns when no debugger is connected that has booked the output.
yihui	5:9b240c1d5251	2333	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
yihui	5:9b240c1d5251	2334
yihui	5:9b240c1d5251	2335	\param [in] ch Character to transmit.
yihui	5:9b240c1d5251	2336
yihui	5:9b240c1d5251	2337	\returns Character to transmit.
yihui	5:9b240c1d5251	2338	*/
yihui	5:9b240c1d5251	2339	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
yihui	5:9b240c1d5251	2340	{
yihui	5:9b240c1d5251	2341	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
yihui	5:9b240c1d5251	2342	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
yihui	5:9b240c1d5251	2343	{
yihui	5:9b240c1d5251	2344	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
yihui	5:9b240c1d5251	2345	ITM->PORT[0].u8 = (uint8_t)ch;
yihui	5:9b240c1d5251	2346	}
yihui	5:9b240c1d5251	2347	return (ch);
yihui	5:9b240c1d5251	2348	}
yihui	5:9b240c1d5251	2349
yihui	5:9b240c1d5251	2350
yihui	5:9b240c1d5251	2351	/** \brief ITM Receive Character
yihui	5:9b240c1d5251	2352
yihui	5:9b240c1d5251	2353	The function inputs a character via the external variable \ref ITM_RxBuffer.
yihui	5:9b240c1d5251	2354
yihui	5:9b240c1d5251	2355	\return Received character.
yihui	5:9b240c1d5251	2356	\return -1 No character pending.
yihui	5:9b240c1d5251	2357	*/
yihui	5:9b240c1d5251	2358	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
yihui	5:9b240c1d5251	2359	int32_t ch = -1; /* no character available */
yihui	5:9b240c1d5251	2360
yihui	5:9b240c1d5251	2361	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
yihui	5:9b240c1d5251	2362	ch = ITM_RxBuffer;
yihui	5:9b240c1d5251	2363	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
yihui	5:9b240c1d5251	2364	}
yihui	5:9b240c1d5251	2365
yihui	5:9b240c1d5251	2366	return (ch);
yihui	5:9b240c1d5251	2367	}
yihui	5:9b240c1d5251	2368
yihui	5:9b240c1d5251	2369
yihui	5:9b240c1d5251	2370	/** \brief ITM Check Character
yihui	5:9b240c1d5251	2371
yihui	5:9b240c1d5251	2372	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
yihui	5:9b240c1d5251	2373
yihui	5:9b240c1d5251	2374	\return 0 No character available.
yihui	5:9b240c1d5251	2375	\return 1 Character available.
yihui	5:9b240c1d5251	2376	*/
yihui	5:9b240c1d5251	2377	__STATIC_INLINE int32_t ITM_CheckChar (void) {
yihui	5:9b240c1d5251	2378
yihui	5:9b240c1d5251	2379	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
yihui	5:9b240c1d5251	2380	return (0); /* no character available */
yihui	5:9b240c1d5251	2381	} else {
yihui	5:9b240c1d5251	2382	return (1); /* character available */
yihui	5:9b240c1d5251	2383	}
yihui	5:9b240c1d5251	2384	}
yihui	5:9b240c1d5251	2385
yihui	5:9b240c1d5251	2386	/@} end of CMSIS_core_DebugFunctions /
yihui	5:9b240c1d5251	2387
yihui	5:9b240c1d5251	2388
yihui	5:9b240c1d5251	2389
yihui	5:9b240c1d5251	2390
yihui	5:9b240c1d5251	2391	#ifdef __cplusplus
yihui	5:9b240c1d5251	2392	}
yihui	5:9b240c1d5251	2393	#endif
yihui	5:9b240c1d5251	2394
yihui	5:9b240c1d5251	2395	#endif /* __CORE_CM7_H_DEPENDANT */
yihui	5:9b240c1d5251	2396
yihui	5:9b240c1d5251	2397	#endif /* __CMSIS_GENERIC */

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Type:	Program
Created:	10 Dec 2015
Imports:	49
Forks:	0
Commits:	6
Dependents:	0
Dependencies:	1
Followers:	2

mbed-src/targets/cmsis/core_cm7.h@5:9b240c1d5251, 2015-12-10 (annotated)

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