Stephane Swanepoel / PowerControl

Original

Dependents:   mbed_multiplex mbed_multiplex_matrix

EthernetPowerControl.cpp@0:dedd847106ba, 2015-09-04 (annotated)

Committer:
yenzo
Date:
Fri Sep 04 21:36:03 2015 +0000
Revision:
0:dedd847106ba
No change

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yenzo 0:dedd847106ba 1 #include "EthernetPowerControl.h"
yenzo 0:dedd847106ba 2
yenzo 0:dedd847106ba 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
yenzo 0:dedd847106ba 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
yenzo 0:dedd847106ba 5 unsigned int tout;
yenzo 0:dedd847106ba 6 /* Hardware MII Management for LPC176x devices. */
yenzo 0:dedd847106ba 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
yenzo 0:dedd847106ba 8 LPC_EMAC->MWTD = Value;
yenzo 0:dedd847106ba 9
yenzo 0:dedd847106ba 10 /* Wait utill operation completed */
yenzo 0:dedd847106ba 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
yenzo 0:dedd847106ba 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
yenzo 0:dedd847106ba 13 break;
yenzo 0:dedd847106ba 14 }
yenzo 0:dedd847106ba 15 }
yenzo 0:dedd847106ba 16 }
yenzo 0:dedd847106ba 17
yenzo 0:dedd847106ba 18 static unsigned short read_PHY (unsigned int PhyReg) {
yenzo 0:dedd847106ba 19 /* Read a PHY register 'PhyReg'. */
yenzo 0:dedd847106ba 20 unsigned int tout, val;
yenzo 0:dedd847106ba 21
yenzo 0:dedd847106ba 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
yenzo 0:dedd847106ba 23 LPC_EMAC->MCMD = MCMD_READ;
yenzo 0:dedd847106ba 24
yenzo 0:dedd847106ba 25 /* Wait until operation completed */
yenzo 0:dedd847106ba 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
yenzo 0:dedd847106ba 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
yenzo 0:dedd847106ba 28 break;
yenzo 0:dedd847106ba 29 }
yenzo 0:dedd847106ba 30 }
yenzo 0:dedd847106ba 31 LPC_EMAC->MCMD = 0;
yenzo 0:dedd847106ba 32 val = LPC_EMAC->MRDD;
yenzo 0:dedd847106ba 33
yenzo 0:dedd847106ba 34 return (val);
yenzo 0:dedd847106ba 35 }
yenzo 0:dedd847106ba 36
yenzo 0:dedd847106ba 37 void EMAC_Init()
yenzo 0:dedd847106ba 38 {
yenzo 0:dedd847106ba 39 unsigned int tout,regv;
yenzo 0:dedd847106ba 40 /* Power Up the EMAC controller. */
yenzo 0:dedd847106ba 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
yenzo 0:dedd847106ba 42
yenzo 0:dedd847106ba 43 LPC_PINCON->PINSEL2 = 0x50150105;
yenzo 0:dedd847106ba 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
yenzo 0:dedd847106ba 45 LPC_PINCON->PINSEL3 |= 0x00000005;
yenzo 0:dedd847106ba 46
yenzo 0:dedd847106ba 47 /* Reset all EMAC internal modules. */
yenzo 0:dedd847106ba 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
yenzo 0:dedd847106ba 49 MAC1_SIM_RES | MAC1_SOFT_RES;
yenzo 0:dedd847106ba 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
yenzo 0:dedd847106ba 51
yenzo 0:dedd847106ba 52 /* A short delay after reset. */
yenzo 0:dedd847106ba 53 for (tout = 100; tout; tout--);
yenzo 0:dedd847106ba 54
yenzo 0:dedd847106ba 55 /* Initialize MAC control registers. */
yenzo 0:dedd847106ba 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
yenzo 0:dedd847106ba 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
yenzo 0:dedd847106ba 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
yenzo 0:dedd847106ba 59 LPC_EMAC->CLRT = CLRT_DEF;
yenzo 0:dedd847106ba 60 LPC_EMAC->IPGR = IPGR_DEF;
yenzo 0:dedd847106ba 61
yenzo 0:dedd847106ba 62 /* Enable Reduced MII interface. */
yenzo 0:dedd847106ba 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
yenzo 0:dedd847106ba 64
yenzo 0:dedd847106ba 65 /* Reset Reduced MII Logic. */
yenzo 0:dedd847106ba 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
yenzo 0:dedd847106ba 67 for (tout = 100; tout; tout--);
yenzo 0:dedd847106ba 68 LPC_EMAC->SUPP = 0;
yenzo 0:dedd847106ba 69
yenzo 0:dedd847106ba 70 /* Put the DP83848C in reset mode */
yenzo 0:dedd847106ba 71 write_PHY (PHY_REG_BMCR, 0x8000);
yenzo 0:dedd847106ba 72
yenzo 0:dedd847106ba 73 /* Wait for hardware reset to end. */
yenzo 0:dedd847106ba 74 for (tout = 0; tout < 0x100000; tout++) {
yenzo 0:dedd847106ba 75 regv = read_PHY (PHY_REG_BMCR);
yenzo 0:dedd847106ba 76 if (!(regv & 0x8000)) {
yenzo 0:dedd847106ba 77 /* Reset complete */
yenzo 0:dedd847106ba 78 break;
yenzo 0:dedd847106ba 79 }
yenzo 0:dedd847106ba 80 }
yenzo 0:dedd847106ba 81 }
yenzo 0:dedd847106ba 82
yenzo 0:dedd847106ba 83
yenzo 0:dedd847106ba 84 void PHY_PowerDown()
yenzo 0:dedd847106ba 85 {
yenzo 0:dedd847106ba 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
yenzo 0:dedd847106ba 87 EMAC_Init(); //init EMAC if it is not already init'd
yenzo 0:dedd847106ba 88
yenzo 0:dedd847106ba 89 unsigned int regv;
yenzo 0:dedd847106ba 90 regv = read_PHY(PHY_REG_BMCR);
yenzo 0:dedd847106ba 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
yenzo 0:dedd847106ba 92 regv = read_PHY(PHY_REG_BMCR);
yenzo 0:dedd847106ba 93
yenzo 0:dedd847106ba 94 //shouldn't need the EMAC now.
yenzo 0:dedd847106ba 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
yenzo 0:dedd847106ba 96
yenzo 0:dedd847106ba 97 //and turn off the PHY OSC
yenzo 0:dedd847106ba 98 LPC_GPIO1->FIODIR |= 0x8000000;
yenzo 0:dedd847106ba 99 LPC_GPIO1->FIOCLR = 0x8000000;
yenzo 0:dedd847106ba 100 }
yenzo 0:dedd847106ba 101
yenzo 0:dedd847106ba 102 void PHY_PowerUp()
yenzo 0:dedd847106ba 103 {
yenzo 0:dedd847106ba 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
yenzo 0:dedd847106ba 105 EMAC_Init(); //init EMAC if it is not already init'd
yenzo 0:dedd847106ba 106
yenzo 0:dedd847106ba 107 LPC_GPIO1->FIODIR |= 0x8000000;
yenzo 0:dedd847106ba 108 LPC_GPIO1->FIOSET = 0x8000000;
yenzo 0:dedd847106ba 109
yenzo 0:dedd847106ba 110 //wait for osc to be stable
yenzo 0:dedd847106ba 111 wait_ms(200);
yenzo 0:dedd847106ba 112
yenzo 0:dedd847106ba 113 unsigned int regv;
yenzo 0:dedd847106ba 114 regv = read_PHY(PHY_REG_BMCR);
yenzo 0:dedd847106ba 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
yenzo 0:dedd847106ba 116 regv = read_PHY(PHY_REG_BMCR);
yenzo 0:dedd847106ba 117 }
yenzo 0:dedd847106ba 118
yenzo 0:dedd847106ba 119 void PHY_EnergyDetect_Enable()
yenzo 0:dedd847106ba 120 {
yenzo 0:dedd847106ba 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
yenzo 0:dedd847106ba 122 EMAC_Init(); //init EMAC if it is not already init'd
yenzo 0:dedd847106ba 123
yenzo 0:dedd847106ba 124 unsigned int regv;
yenzo 0:dedd847106ba 125 regv = read_PHY(PHY_REG_EDCR);
yenzo 0:dedd847106ba 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
yenzo 0:dedd847106ba 127 regv = read_PHY(PHY_REG_EDCR);
yenzo 0:dedd847106ba 128 }
yenzo 0:dedd847106ba 129
yenzo 0:dedd847106ba 130 void PHY_EnergyDetect_Disable()
yenzo 0:dedd847106ba 131 {
yenzo 0:dedd847106ba 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
yenzo 0:dedd847106ba 133 EMAC_Init(); //init EMAC if it is not already init'd
yenzo 0:dedd847106ba 134 unsigned int regv;
yenzo 0:dedd847106ba 135 regv = read_PHY(PHY_REG_EDCR);
yenzo 0:dedd847106ba 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
yenzo 0:dedd847106ba 137 regv = read_PHY(PHY_REG_EDCR);
yenzo 0:dedd847106ba 138 }