Yuji Notsu
/
OV7670_camera_test
This program is for OV7670 and TFT-LCD(REL225L01)
OV7670.h@0:03f32e3679c8, 2012-02-16 (annotated)
- Committer:
- y_notsu
- Date:
- Thu Feb 16 14:51:28 2012 +0000
- Revision:
- 0:03f32e3679c8
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
y_notsu | 0:03f32e3679c8 | 1 | #include "mbed.h" |
y_notsu | 0:03f32e3679c8 | 2 | |
y_notsu | 0:03f32e3679c8 | 3 | #define OV7670_I2C_ADDR 0x42 |
y_notsu | 0:03f32e3679c8 | 4 | |
y_notsu | 0:03f32e3679c8 | 5 | /* |
y_notsu | 0:03f32e3679c8 | 6 | * Basic window sizes. These probably belong somewhere more globally |
y_notsu | 0:03f32e3679c8 | 7 | * useful. |
y_notsu | 0:03f32e3679c8 | 8 | */ |
y_notsu | 0:03f32e3679c8 | 9 | #define VGA_WIDTH 640 |
y_notsu | 0:03f32e3679c8 | 10 | #define VGA_HEIGHT 480 |
y_notsu | 0:03f32e3679c8 | 11 | #define QVGA_WIDTH 320 |
y_notsu | 0:03f32e3679c8 | 12 | #define QVGA_HEIGHT 240 |
y_notsu | 0:03f32e3679c8 | 13 | #define CIF_WIDTH 352 |
y_notsu | 0:03f32e3679c8 | 14 | #define CIF_HEIGHT 288 |
y_notsu | 0:03f32e3679c8 | 15 | #define QCIF_WIDTH 176 |
y_notsu | 0:03f32e3679c8 | 16 | #define QCIF_HEIGHT 144 |
y_notsu | 0:03f32e3679c8 | 17 | |
y_notsu | 0:03f32e3679c8 | 18 | /* Register */ |
y_notsu | 0:03f32e3679c8 | 19 | #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ |
y_notsu | 0:03f32e3679c8 | 20 | #define REG_BLUE 0x01 /* blue gain */ |
y_notsu | 0:03f32e3679c8 | 21 | #define REG_RED 0x02 /* red gain */ |
y_notsu | 0:03f32e3679c8 | 22 | #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ |
y_notsu | 0:03f32e3679c8 | 23 | #define REG_COM1 0x04 /* Control 1 */ |
y_notsu | 0:03f32e3679c8 | 24 | #define COM1_CCIR656 0x40 /* CCIR656 enable */ |
y_notsu | 0:03f32e3679c8 | 25 | #define REG_BAVE 0x05 /* U/B Average level */ |
y_notsu | 0:03f32e3679c8 | 26 | #define REG_GbAVE 0x06 /* Y/Gb Average level */ |
y_notsu | 0:03f32e3679c8 | 27 | #define REG_AECHH 0x07 /* AEC MS 5 bits */ |
y_notsu | 0:03f32e3679c8 | 28 | #define REG_RAVE 0x08 /* V/R Average level */ |
y_notsu | 0:03f32e3679c8 | 29 | #define REG_COM2 0x09 /* Control 2 */ |
y_notsu | 0:03f32e3679c8 | 30 | #define COM2_SSLEEP 0x10 /* Soft sleep mode */ |
y_notsu | 0:03f32e3679c8 | 31 | #define REG_PID 0x0a /* Product ID MSB */ |
y_notsu | 0:03f32e3679c8 | 32 | #define REG_VER 0x0b /* Product ID LSB */ |
y_notsu | 0:03f32e3679c8 | 33 | #define REG_COM3 0x0c /* Control 3 */ |
y_notsu | 0:03f32e3679c8 | 34 | #define COM3_SWAP 0x40 /* Byte swap */ |
y_notsu | 0:03f32e3679c8 | 35 | #define COM3_SCALEEN 0x08 /* Enable scaling */ |
y_notsu | 0:03f32e3679c8 | 36 | #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ |
y_notsu | 0:03f32e3679c8 | 37 | #define REG_COM4 0x0d /* Control 4 */ |
y_notsu | 0:03f32e3679c8 | 38 | #define REG_COM5 0x0e /* All "reserved" */ |
y_notsu | 0:03f32e3679c8 | 39 | #define REG_COM6 0x0f /* Control 6 */ |
y_notsu | 0:03f32e3679c8 | 40 | #define REG_AECH 0x10 /* More bits of AEC value */ |
y_notsu | 0:03f32e3679c8 | 41 | #define REG_CLKRC 0x11 /* Clocl control */ |
y_notsu | 0:03f32e3679c8 | 42 | #define CLK_EXT 0x40 /* Use external clock directly */ |
y_notsu | 0:03f32e3679c8 | 43 | #define CLK_SCALE 0x3f /* Mask for internal clock scale */ |
y_notsu | 0:03f32e3679c8 | 44 | #define REG_COM7 0x12 /* Control 7 */ |
y_notsu | 0:03f32e3679c8 | 45 | #define COM7_RESET 0x80 /* Register reset */ |
y_notsu | 0:03f32e3679c8 | 46 | #define COM7_FMT_MASK 0x38 |
y_notsu | 0:03f32e3679c8 | 47 | #define COM7_FMT_VGA 0x00 |
y_notsu | 0:03f32e3679c8 | 48 | #define COM7_FMT_CIF 0x20 /* CIF format */ |
y_notsu | 0:03f32e3679c8 | 49 | #define COM7_FMT_QVGA 0x10 /* QVGA format */ |
y_notsu | 0:03f32e3679c8 | 50 | #define COM7_FMT_QCIF 0x08 /* QCIF format */ |
y_notsu | 0:03f32e3679c8 | 51 | #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ |
y_notsu | 0:03f32e3679c8 | 52 | #define COM7_YUV 0x00 /* YUV */ |
y_notsu | 0:03f32e3679c8 | 53 | #define COM7_BAYER 0x01 /* Bayer format */ |
y_notsu | 0:03f32e3679c8 | 54 | #define COM7_PBAYER 0x05 /* "Processed bayer" */ |
y_notsu | 0:03f32e3679c8 | 55 | #define REG_COM8 0x13 /* Control 8 */ |
y_notsu | 0:03f32e3679c8 | 56 | #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ |
y_notsu | 0:03f32e3679c8 | 57 | #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ |
y_notsu | 0:03f32e3679c8 | 58 | #define COM8_BFILT 0x20 /* Band filter enable */ |
y_notsu | 0:03f32e3679c8 | 59 | #define COM8_AGC 0x04 /* Auto gain enable */ |
y_notsu | 0:03f32e3679c8 | 60 | #define COM8_AWB 0x02 /* White balance enable */ |
y_notsu | 0:03f32e3679c8 | 61 | #define COM8_AEC 0x01 /* Auto exposure enable */ |
y_notsu | 0:03f32e3679c8 | 62 | #define REG_COM9 0x14 /* Control 9 - gain ceiling */ |
y_notsu | 0:03f32e3679c8 | 63 | #define REG_COM10 0x15 /* Control 10 */ |
y_notsu | 0:03f32e3679c8 | 64 | #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ |
y_notsu | 0:03f32e3679c8 | 65 | #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ |
y_notsu | 0:03f32e3679c8 | 66 | #define COM10_HREF_REV 0x08 /* Reverse HREF */ |
y_notsu | 0:03f32e3679c8 | 67 | #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ |
y_notsu | 0:03f32e3679c8 | 68 | #define COM10_VS_NEG 0x02 /* VSYNC negative */ |
y_notsu | 0:03f32e3679c8 | 69 | #define COM10_HS_NEG 0x01 /* HSYNC negative */ |
y_notsu | 0:03f32e3679c8 | 70 | #define REG_HSTART 0x17 /* Horiz start high bits */ |
y_notsu | 0:03f32e3679c8 | 71 | #define REG_HSTOP 0x18 /* Horiz stop high bits */ |
y_notsu | 0:03f32e3679c8 | 72 | #define REG_VSTART 0x19 /* Vert start high bits */ |
y_notsu | 0:03f32e3679c8 | 73 | #define REG_VSTOP 0x1a /* Vert stop high bits */ |
y_notsu | 0:03f32e3679c8 | 74 | #define REG_PSHFT 0x1b /* Pixel delay after HREF */ |
y_notsu | 0:03f32e3679c8 | 75 | #define REG_MIDH 0x1c /* Manuf. ID high */ |
y_notsu | 0:03f32e3679c8 | 76 | #define REG_MIDL 0x1d /* Manuf. ID low */ |
y_notsu | 0:03f32e3679c8 | 77 | #define REG_MVFP 0x1e /* Mirror / vflip */ |
y_notsu | 0:03f32e3679c8 | 78 | #define MVFP_MIRROR 0x20 /* Mirror image */ |
y_notsu | 0:03f32e3679c8 | 79 | #define MVFP_FLIP 0x10 /* Vertical flip */ |
y_notsu | 0:03f32e3679c8 | 80 | |
y_notsu | 0:03f32e3679c8 | 81 | #define REG_AEW 0x24 /* AGC upper limit */ |
y_notsu | 0:03f32e3679c8 | 82 | #define REG_AEB 0x25 /* AGC lower limit */ |
y_notsu | 0:03f32e3679c8 | 83 | #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ |
y_notsu | 0:03f32e3679c8 | 84 | #define REG_HSYST 0x30 /* HSYNC rising edge delay */ |
y_notsu | 0:03f32e3679c8 | 85 | #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ |
y_notsu | 0:03f32e3679c8 | 86 | #define REG_HREF 0x32 /* HREF pieces */ |
y_notsu | 0:03f32e3679c8 | 87 | #define REG_TSLB 0x3a /* lots of stuff */ |
y_notsu | 0:03f32e3679c8 | 88 | #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ |
y_notsu | 0:03f32e3679c8 | 89 | #define REG_COM11 0x3b /* Control 11 */ |
y_notsu | 0:03f32e3679c8 | 90 | #define COM11_NIGHT 0x80 /* NIght mode enable */ |
y_notsu | 0:03f32e3679c8 | 91 | #define COM11_NMFR 0x60 /* Two bit NM frame rate */ |
y_notsu | 0:03f32e3679c8 | 92 | #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ |
y_notsu | 0:03f32e3679c8 | 93 | #define COM11_50HZ 0x08 /* Manual 50Hz select */ |
y_notsu | 0:03f32e3679c8 | 94 | #define COM11_EXP 0x02 |
y_notsu | 0:03f32e3679c8 | 95 | #define REG_COM12 0x3c /* Control 12 */ |
y_notsu | 0:03f32e3679c8 | 96 | #define COM12_HREF 0x80 /* HREF always */ |
y_notsu | 0:03f32e3679c8 | 97 | #define REG_COM13 0x3d /* Control 13 */ |
y_notsu | 0:03f32e3679c8 | 98 | #define COM13_GAMMA 0x80 /* Gamma enable */ |
y_notsu | 0:03f32e3679c8 | 99 | #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ |
y_notsu | 0:03f32e3679c8 | 100 | #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ |
y_notsu | 0:03f32e3679c8 | 101 | #define REG_COM14 0x3e /* Control 14 */ |
y_notsu | 0:03f32e3679c8 | 102 | #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ |
y_notsu | 0:03f32e3679c8 | 103 | #define REG_EDGE 0x3f /* Edge enhancement factor */ |
y_notsu | 0:03f32e3679c8 | 104 | #define REG_COM15 0x40 /* Control 15 */ |
y_notsu | 0:03f32e3679c8 | 105 | #define COM15_R10F0 0x00 /* Data range 10 to F0 */ |
y_notsu | 0:03f32e3679c8 | 106 | #define COM15_R01FE 0x80 /* 01 to FE */ |
y_notsu | 0:03f32e3679c8 | 107 | #define COM15_R00FF 0xc0 /* 00 to FF */ |
y_notsu | 0:03f32e3679c8 | 108 | #define COM15_RGB565 0x10 /* RGB565 output */ |
y_notsu | 0:03f32e3679c8 | 109 | #define COM15_RGB555 0x30 /* RGB555 output */ |
y_notsu | 0:03f32e3679c8 | 110 | #define REG_COM16 0x41 /* Control 16 */ |
y_notsu | 0:03f32e3679c8 | 111 | #define COM16_AWBGAIN 0x08 /* AWB gain enable */ |
y_notsu | 0:03f32e3679c8 | 112 | #define REG_COM17 0x42 /* Control 17 */ |
y_notsu | 0:03f32e3679c8 | 113 | #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ |
y_notsu | 0:03f32e3679c8 | 114 | #define COM17_CBAR 0x08 /* DSP Color bar */ |
y_notsu | 0:03f32e3679c8 | 115 | |
y_notsu | 0:03f32e3679c8 | 116 | /* |
y_notsu | 0:03f32e3679c8 | 117 | * This matrix defines how the colors are generated, must be |
y_notsu | 0:03f32e3679c8 | 118 | * tweaked to adjust hue and saturation. |
y_notsu | 0:03f32e3679c8 | 119 | * |
y_notsu | 0:03f32e3679c8 | 120 | * Order: v-red, v-green, v-blue, u-red, u-green, u-blue |
y_notsu | 0:03f32e3679c8 | 121 | * |
y_notsu | 0:03f32e3679c8 | 122 | * They are nine-bit signed quantities, with the sign bit |
y_notsu | 0:03f32e3679c8 | 123 | * stored in 0x58. Sign for v-red is bit 0, and up from there. |
y_notsu | 0:03f32e3679c8 | 124 | */ |
y_notsu | 0:03f32e3679c8 | 125 | #define REG_CMATRIX_BASE 0x4f |
y_notsu | 0:03f32e3679c8 | 126 | #define CMATRIX_LEN 6 |
y_notsu | 0:03f32e3679c8 | 127 | #define REG_CMATRIX_SIGN 0x58 |
y_notsu | 0:03f32e3679c8 | 128 | |
y_notsu | 0:03f32e3679c8 | 129 | |
y_notsu | 0:03f32e3679c8 | 130 | #define REG_BRIGHT 0x55 /* Brightness */ |
y_notsu | 0:03f32e3679c8 | 131 | #define REG_CONTRAS 0x56 /* Contrast control */ |
y_notsu | 0:03f32e3679c8 | 132 | |
y_notsu | 0:03f32e3679c8 | 133 | #define REG_GFIX 0x69 /* Fix gain control */ |
y_notsu | 0:03f32e3679c8 | 134 | |
y_notsu | 0:03f32e3679c8 | 135 | #define REG_REG76 0x76 /* OV's name */ |
y_notsu | 0:03f32e3679c8 | 136 | #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ |
y_notsu | 0:03f32e3679c8 | 137 | #define R76_WHTPCOR 0x40 /* White pixel correction enable */ |
y_notsu | 0:03f32e3679c8 | 138 | |
y_notsu | 0:03f32e3679c8 | 139 | #define REG_RGB444 0x8c /* RGB 444 control */ |
y_notsu | 0:03f32e3679c8 | 140 | #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ |
y_notsu | 0:03f32e3679c8 | 141 | #define R444_RGBX 0x01 /* Empty nibble at end */ |
y_notsu | 0:03f32e3679c8 | 142 | |
y_notsu | 0:03f32e3679c8 | 143 | #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ |
y_notsu | 0:03f32e3679c8 | 144 | #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ |
y_notsu | 0:03f32e3679c8 | 145 | |
y_notsu | 0:03f32e3679c8 | 146 | #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ |
y_notsu | 0:03f32e3679c8 | 147 | #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ |
y_notsu | 0:03f32e3679c8 | 148 | #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ |
y_notsu | 0:03f32e3679c8 | 149 | #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ |
y_notsu | 0:03f32e3679c8 | 150 | #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ |
y_notsu | 0:03f32e3679c8 | 151 | #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ |
y_notsu | 0:03f32e3679c8 | 152 | #define REG_BD60MAX 0xab /* 60hz banding step limit */ |
y_notsu | 0:03f32e3679c8 | 153 | |
y_notsu | 0:03f32e3679c8 | 154 | struct regval_list { |
y_notsu | 0:03f32e3679c8 | 155 | unsigned char reg_num; |
y_notsu | 0:03f32e3679c8 | 156 | unsigned char value; |
y_notsu | 0:03f32e3679c8 | 157 | }; |
y_notsu | 0:03f32e3679c8 | 158 | |
y_notsu | 0:03f32e3679c8 | 159 | static struct regval_list ov7670_default_regs[] = { |
y_notsu | 0:03f32e3679c8 | 160 | { REG_COM7, COM7_RESET }, |
y_notsu | 0:03f32e3679c8 | 161 | /* |
y_notsu | 0:03f32e3679c8 | 162 | * Clock scale: 3 = 15fps |
y_notsu | 0:03f32e3679c8 | 163 | * 2 = 20fps |
y_notsu | 0:03f32e3679c8 | 164 | * 1 = 30fps |
y_notsu | 0:03f32e3679c8 | 165 | */ |
y_notsu | 0:03f32e3679c8 | 166 | { REG_CLKRC, 1 }, /* OV: clock scale (30 fps), internal clk= external clk/(1+1) */ |
y_notsu | 0:03f32e3679c8 | 167 | { REG_TSLB, 0x04 }, /* OV */ |
y_notsu | 0:03f32e3679c8 | 168 | { REG_COM7, 0 }, /* VGA,YUV */ |
y_notsu | 0:03f32e3679c8 | 169 | /* |
y_notsu | 0:03f32e3679c8 | 170 | * Set the hardware window. These values from OV don't entirely |
y_notsu | 0:03f32e3679c8 | 171 | * make sense - hstop is less than hstart. But they work... |
y_notsu | 0:03f32e3679c8 | 172 | */ |
y_notsu | 0:03f32e3679c8 | 173 | { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, |
y_notsu | 0:03f32e3679c8 | 174 | { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, |
y_notsu | 0:03f32e3679c8 | 175 | { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, |
y_notsu | 0:03f32e3679c8 | 176 | |
y_notsu | 0:03f32e3679c8 | 177 | { REG_COM3, 0 }, { REG_COM14, 0 }, |
y_notsu | 0:03f32e3679c8 | 178 | /* Mystery scaling numbers */ |
y_notsu | 0:03f32e3679c8 | 179 | { 0x70, 0x3a }, //Bit[7]:Test Pattern |
y_notsu | 0:03f32e3679c8 | 180 | //Bit[6:0]:Horizontal scale factor |
y_notsu | 0:03f32e3679c8 | 181 | { 0x71, 0x35 }, //Bit[7]:Test Pattern (/w 0x70) |
y_notsu | 0:03f32e3679c8 | 182 | //Bit[6:0]:Vertical scale factor |
y_notsu | 0:03f32e3679c8 | 183 | { 0x72, 0x11 }, //DCW control |
y_notsu | 0:03f32e3679c8 | 184 | //Bit[7] Vertical average calculation option |
y_notsu | 0:03f32e3679c8 | 185 | // 0:Vertical truncation |
y_notsu | 0:03f32e3679c8 | 186 | // 1:Vertical rounding |
y_notsu | 0:03f32e3679c8 | 187 | //Bit[6] Vertical down sampling option |
y_notsu | 0:03f32e3679c8 | 188 | // 0:Vertical truncation |
y_notsu | 0:03f32e3679c8 | 189 | // 1:Vertical rounding |
y_notsu | 0:03f32e3679c8 | 190 | //Bit[5:4] Vertical down sampling rate |
y_notsu | 0:03f32e3679c8 | 191 | // 00:No down sampling, 01: by2, 10:by4, 11:by8 |
y_notsu | 0:03f32e3679c8 | 192 | //Bit[3] Horizontal averagecalculation option |
y_notsu | 0:03f32e3679c8 | 193 | // 0: Horizontal truncation |
y_notsu | 0:03f32e3679c8 | 194 | // 1: Horizontal rounding |
y_notsu | 0:03f32e3679c8 | 195 | //Bit[2] Horizontal down sampling option |
y_notsu | 0:03f32e3679c8 | 196 | // 0: Horizontal truncation |
y_notsu | 0:03f32e3679c8 | 197 | // 1: Horizontal rounding |
y_notsu | 0:03f32e3679c8 | 198 | //Bit[1:0] Horizontal down sampling rate |
y_notsu | 0:03f32e3679c8 | 199 | // 00: No down sampling, 01: by2, 10:by4, 11:by8 |
y_notsu | 0:03f32e3679c8 | 200 | { 0x73, 0xf0 }, //Bit[7:4] Reserved (Original : 0b1111) |
y_notsu | 0:03f32e3679c8 | 201 | //Bit[3] Bypass clock divider for DSP scale control |
y_notsu | 0:03f32e3679c8 | 202 | // 0: Enable clock divider, 1:Bypass clock divider |
y_notsu | 0:03f32e3679c8 | 203 | // Bit[2:0] Clock divider control for DSP scale control |
y_notsu | 0:03f32e3679c8 | 204 | // 000: Divided by 1, 001:Divided by 2, 010:Divided by4 |
y_notsu | 0:03f32e3679c8 | 205 | // 100: Divided by 8, 101:Divided by 16, 110-111:Not allowed |
y_notsu | 0:03f32e3679c8 | 206 | { 0xa2, 0x02 }, //Pixel Clock Delay |
y_notsu | 0:03f32e3679c8 | 207 | //Bit[7]: Reserved (original:0) |
y_notsu | 0:03f32e3679c8 | 208 | //Bit[6:0] Scaling output delay (original :0x02) |
y_notsu | 0:03f32e3679c8 | 209 | { REG_COM10, 0x20 },//Common Control 10 (original :0x00) |
y_notsu | 0:03f32e3679c8 | 210 | //Bit[7] Reserved |
y_notsu | 0:03f32e3679c8 | 211 | //Bit[6] HREF changed to HSYNC |
y_notsu | 0:03f32e3679c8 | 212 | //Bit[5] PCLK output option (0: Free running PCLK, 1: PCLK does not toggle during horizontal blank) |
y_notsu | 0:03f32e3679c8 | 213 | //Bit[4] PCLK reverse |
y_notsu | 0:03f32e3679c8 | 214 | //Bit[3] HREF reverse |
y_notsu | 0:03f32e3679c8 | 215 | //Bit[2] VSYNC option (0: VSYNC changes on falling edge of PCLK, 1:rising edge) |
y_notsu | 0:03f32e3679c8 | 216 | //Bit[1] VSYNC negative |
y_notsu | 0:03f32e3679c8 | 217 | //Bit[0] HSYNC negative |
y_notsu | 0:03f32e3679c8 | 218 | |
y_notsu | 0:03f32e3679c8 | 219 | /* Gamma curve values */ |
y_notsu | 0:03f32e3679c8 | 220 | { 0x7a, 0x20 }, { 0x7b, 0x10 }, |
y_notsu | 0:03f32e3679c8 | 221 | { 0x7c, 0x1e }, { 0x7d, 0x35 }, |
y_notsu | 0:03f32e3679c8 | 222 | { 0x7e, 0x5a }, { 0x7f, 0x69 }, |
y_notsu | 0:03f32e3679c8 | 223 | { 0x80, 0x76 }, { 0x81, 0x80 }, |
y_notsu | 0:03f32e3679c8 | 224 | { 0x82, 0x88 }, { 0x83, 0x8f }, |
y_notsu | 0:03f32e3679c8 | 225 | { 0x84, 0x96 }, { 0x85, 0xa3 }, |
y_notsu | 0:03f32e3679c8 | 226 | { 0x86, 0xaf }, { 0x87, 0xc4 }, |
y_notsu | 0:03f32e3679c8 | 227 | { 0x88, 0xd7 }, { 0x89, 0xe8 }, |
y_notsu | 0:03f32e3679c8 | 228 | |
y_notsu | 0:03f32e3679c8 | 229 | /* AGC and AEC parameters. Note we start by disabling those features, |
y_notsu | 0:03f32e3679c8 | 230 | then turn them only after tweaking the values. */ |
y_notsu | 0:03f32e3679c8 | 231 | { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, |
y_notsu | 0:03f32e3679c8 | 232 | // Common control 8 (for AGC, AEC Off) |
y_notsu | 0:03f32e3679c8 | 233 | { REG_GAIN, 0 }, |
y_notsu | 0:03f32e3679c8 | 234 | { REG_AECH, 0x04 }, //AEC[9:2] |
y_notsu | 0:03f32e3679c8 | 235 | { 0x07, 0x00 }, //Bit[7:6] Reserved |
y_notsu | 0:03f32e3679c8 | 236 | //Bit[5:0] AEC[15:10] |
y_notsu | 0:03f32e3679c8 | 237 | { 0x04, 0x00 }, //Common control 1 |
y_notsu | 0:03f32e3679c8 | 238 | //Bit[7] Reserved |
y_notsu | 0:03f32e3679c8 | 239 | //Bit[6] CCIR format (0:Disable, 1:Enable) |
y_notsu | 0:03f32e3679c8 | 240 | //Bit[5:2] Reserved |
y_notsu | 0:03f32e3679c8 | 241 | //Bit[1:0] AEC[1:0] |
y_notsu | 0:03f32e3679c8 | 242 | { REG_COM4, 0x40 }, /* magic reserved bit */ |
y_notsu | 0:03f32e3679c8 | 243 | //Bit[7:6] Reserved (Original 0b01) |
y_notsu | 0:03f32e3679c8 | 244 | //Bit[5:4] Average option(must be same value as COM17[7:6])(Original 0b00) |
y_notsu | 0:03f32e3679c8 | 245 | //Bit[3:0] Reserved (Original 0b0000) |
y_notsu | 0:03f32e3679c8 | 246 | { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ |
y_notsu | 0:03f32e3679c8 | 247 | { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, |
y_notsu | 0:03f32e3679c8 | 248 | { REG_AEW, 0x95 }, //AGC/AEC - Stable Operating Region(Upper limit) |
y_notsu | 0:03f32e3679c8 | 249 | { REG_AEB, 0x33 }, //AGC/AEC - Stable Operating Region(Lower limit) |
y_notsu | 0:03f32e3679c8 | 250 | { REG_VPT, 0xe3 }, //AGC/AEC Fast mode Operating Region |
y_notsu | 0:03f32e3679c8 | 251 | //Bit[7:4]: High nibble of upper limit of fast mode control zone |
y_notsu | 0:03f32e3679c8 | 252 | //Bit[3:0]: High nibble of lower limit of fast mode control zone |
y_notsu | 0:03f32e3679c8 | 253 | { REG_HAECC1, 0x78 },// Histgram based AEC/AGC Control 1 (Original : 0x78, Spec init:0xC0) |
y_notsu | 0:03f32e3679c8 | 254 | { REG_HAECC2, 0x68 },// Histgram based AEC/AGC Control 2 (Original : 0x68, Spec init:0x90) |
y_notsu | 0:03f32e3679c8 | 255 | { 0xa1, 0x03 }, /* magic */ |
y_notsu | 0:03f32e3679c8 | 256 | { REG_HAECC3, 0xd8 },// Histgram based AEC/AGC Control 3 (Original : 0xd8, Spec init:0xF0) |
y_notsu | 0:03f32e3679c8 | 257 | { REG_HAECC4, 0xd8 },// Histgram based AEC/AGC Control 4 (Original : 0xd8, Spec init:0xC1) |
y_notsu | 0:03f32e3679c8 | 258 | { REG_HAECC5, 0xf0 },// Histgram based AEC/AGC Control 5 (Original : 0xf0, Spec init:0xf0) |
y_notsu | 0:03f32e3679c8 | 259 | { REG_HAECC6, 0x90 },// Histgram based AEC/AGC Control 6 (Original : 0x90, Spec init:0xC1) |
y_notsu | 0:03f32e3679c8 | 260 | { REG_HAECC7, 0x94 },// Histgram based AEC/AGC Control 7 (Original : 0x94, Spec init:0x14) |
y_notsu | 0:03f32e3679c8 | 261 | //Bit[7]: AEC algorithm selection(0:Average-based, 1:Histogram-based) |
y_notsu | 0:03f32e3679c8 | 262 | //Bit[6:0] Reserved |
y_notsu | 0:03f32e3679c8 | 263 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, |
y_notsu | 0:03f32e3679c8 | 264 | //COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ |
y_notsu | 0:03f32e3679c8 | 265 | //COM8_AECSTEP 0x40 /* Unlimited AEC step size */ |
y_notsu | 0:03f32e3679c8 | 266 | //COM8_BFILT 0x20 /* Band filter enable */ |
y_notsu | 0:03f32e3679c8 | 267 | //COM8_AGC 0x04 /* Auto gain enable */ |
y_notsu | 0:03f32e3679c8 | 268 | //COM8_AWB 0x02 /* White balance enable */ |
y_notsu | 0:03f32e3679c8 | 269 | //COM8_AEC 0x01 /* Auto exposure enable */ |
y_notsu | 0:03f32e3679c8 | 270 | /* Almost all of these are magic "reserved" values. */ |
y_notsu | 0:03f32e3679c8 | 271 | { REG_COM5, 0x61 }, //Bit[7:0] Reserved |
y_notsu | 0:03f32e3679c8 | 272 | { REG_COM6, 0x4b }, //Bit[7]: Output optical black line output 0:Disable,1:Enable(original:0) |
y_notsu | 0:03f32e3679c8 | 273 | //Bit[6:2] Reserved (0b10010) |
y_notsu | 0:03f32e3679c8 | 274 | //Bit[1] Reset all timing when format changes 0:No reset,1:Reset (original:1) |
y_notsu | 0:03f32e3679c8 | 275 | //Bit[0] Reserved (1) |
y_notsu | 0:03f32e3679c8 | 276 | { 0x16, 0x02 }, //Reserved |
y_notsu | 0:03f32e3679c8 | 277 | { REG_MVFP, 0x03 }, //Bit[7:6] Reserved (original 0b00) |
y_notsu | 0:03f32e3679c8 | 278 | //Bit[5] Mirror 0:Normal, 1:Mirror (original 0) |
y_notsu | 0:03f32e3679c8 | 279 | //Bit[4] VFlip 0:Normal, 1:Vertically flip (origianl 0) |
y_notsu | 0:03f32e3679c8 | 280 | //Bit[3] Reserved (original 0) |
y_notsu | 0:03f32e3679c8 | 281 | //Bit[2] Black sun enable (original 1) |
y_notsu | 0:03f32e3679c8 | 282 | //Bit[1:0] Reserved (original 0b11) |
y_notsu | 0:03f32e3679c8 | 283 | { 0x21, 0x02 }, { 0x22, 0x91 }, |
y_notsu | 0:03f32e3679c8 | 284 | { 0x29, 0x07 }, { 0x33, 0x0b }, |
y_notsu | 0:03f32e3679c8 | 285 | { 0x35, 0x0b }, { 0x37, 0x1d }, |
y_notsu | 0:03f32e3679c8 | 286 | { 0x38, 0x71 }, { 0x39, 0x2a }, |
y_notsu | 0:03f32e3679c8 | 287 | { REG_COM12, 0x68 }, { 0x4d, 0x40 }, |
y_notsu | 0:03f32e3679c8 | 288 | { 0x4e, 0x20 }, { REG_GFIX, 0 }, |
y_notsu | 0:03f32e3679c8 | 289 | { 0x6b, 0xca }, //Bit[7:6] PLL control Original:11(x8) |
y_notsu | 0:03f32e3679c8 | 290 | { 0x74, 0x10 }, //Bit[4]: Digital gain contrl: 1:by VREF[7:6],0:by REG74[1:0] |
y_notsu | 0:03f32e3679c8 | 291 | { 0x8d, 0x4f }, { 0x8e, 0 }, |
y_notsu | 0:03f32e3679c8 | 292 | { 0x8f, 0 }, { 0x90, 0 }, |
y_notsu | 0:03f32e3679c8 | 293 | { 0x91, 0 }, { 0x96, 0 }, |
y_notsu | 0:03f32e3679c8 | 294 | { 0x9a, 0 }, { 0xb0, 0x84 }, |
y_notsu | 0:03f32e3679c8 | 295 | { 0xb1, 0x0c }, { 0xb2, 0x0e }, |
y_notsu | 0:03f32e3679c8 | 296 | { 0xb3, 0x82 }, { 0xb8, 0x0a }, |
y_notsu | 0:03f32e3679c8 | 297 | |
y_notsu | 0:03f32e3679c8 | 298 | /* More reserved magic, some of which tweaks white balance */ |
y_notsu | 0:03f32e3679c8 | 299 | { 0x43, 0x0a }, { 0x44, 0xf0 }, |
y_notsu | 0:03f32e3679c8 | 300 | { 0x45, 0x34 }, { 0x46, 0x58 }, |
y_notsu | 0:03f32e3679c8 | 301 | { 0x47, 0x28 }, { 0x48, 0x3a }, |
y_notsu | 0:03f32e3679c8 | 302 | { 0x59, 0x88 }, { 0x5a, 0x88 }, |
y_notsu | 0:03f32e3679c8 | 303 | { 0x5b, 0x44 }, { 0x5c, 0x67 }, |
y_notsu | 0:03f32e3679c8 | 304 | { 0x5d, 0x49 }, { 0x5e, 0x0e }, |
y_notsu | 0:03f32e3679c8 | 305 | { 0x6c, 0x0a }, { 0x6d, 0x55 }, |
y_notsu | 0:03f32e3679c8 | 306 | { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ |
y_notsu | 0:03f32e3679c8 | 307 | { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, |
y_notsu | 0:03f32e3679c8 | 308 | { REG_RED, 0x60 }, |
y_notsu | 0:03f32e3679c8 | 309 | //{ REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, |
y_notsu | 0:03f32e3679c8 | 310 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AWB }, |
y_notsu | 0:03f32e3679c8 | 311 | /* Matrix coefficients */ //default value |
y_notsu | 0:03f32e3679c8 | 312 | { 0x4f, 0x80 }, { 0x50, 0x80 }, |
y_notsu | 0:03f32e3679c8 | 313 | { 0x51, 0 }, { 0x52, 0x22 }, |
y_notsu | 0:03f32e3679c8 | 314 | { 0x53, 0x5e }, { 0x54, 0x80 }, |
y_notsu | 0:03f32e3679c8 | 315 | { 0x58, 0x9e }, |
y_notsu | 0:03f32e3679c8 | 316 | |
y_notsu | 0:03f32e3679c8 | 317 | { REG_COM16, COM16_AWBGAIN }, |
y_notsu | 0:03f32e3679c8 | 318 | { REG_EDGE, 0x00 }, //Bit[7:5]: Reserved |
y_notsu | 0:03f32e3679c8 | 319 | //Bit[4:0]: Edge enchandement factor (original: 0x00) |
y_notsu | 0:03f32e3679c8 | 320 | { 0x75, 0x05 }, //Bit[7:5] : reserved, Bit[4:0] : Edge Enhancement lower limit (original:0x05) |
y_notsu | 0:03f32e3679c8 | 321 | { 0x76, 0xff }, //Bit[7]:Black correction enable 0:Disable, 1:Enable(original:1) |
y_notsu | 0:03f32e3679c8 | 322 | //Bit[6]:White pixel correction enable: 0:Disable, 1:Enable(original:1) |
y_notsu | 0:03f32e3679c8 | 323 | //Bit[5]:Reserved (original:0b10) |
y_notsu | 0:03f32e3679c8 | 324 | //Bit[4:0]: Edge Enhancement higher limit(original:0x01) |
y_notsu | 0:03f32e3679c8 | 325 | { 0x4c, 0 }, //De-noise Setength |
y_notsu | 0:03f32e3679c8 | 326 | { 0x77, 0x00 }, //De-noise offset (original 0x01) |
y_notsu | 0:03f32e3679c8 | 327 | { REG_COM13, 0xc3 }, //Common Control 13 |
y_notsu | 0:03f32e3679c8 | 328 | //Bit[7] Gamma enable |
y_notsu | 0:03f32e3679c8 | 329 | //Bit[6] UV saturation level |
y_notsu | 0:03f32e3679c8 | 330 | //Bit[5:1] Reserved |
y_notsu | 0:03f32e3679c8 | 331 | //Bit[0] UV swap |
y_notsu | 0:03f32e3679c8 | 332 | { 0x4b, 0x09 }, //Bit[7:1] Reserved |
y_notsu | 0:03f32e3679c8 | 333 | //Bit[0] UV average enable |
y_notsu | 0:03f32e3679c8 | 334 | { 0xc9, 0x60 }, //Saturation Control |
y_notsu | 0:03f32e3679c8 | 335 | //Bit[7:4] UV saturation control min |
y_notsu | 0:03f32e3679c8 | 336 | //Bit[3:0] UV saturation control result |
y_notsu | 0:03f32e3679c8 | 337 | { REG_COM16, 0x38 }, //Common control 16 (Original 0b00111000) |
y_notsu | 0:03f32e3679c8 | 338 | //Bit[7:6] Reserved (Original 0b00) |
y_notsu | 0:03f32e3679c8 | 339 | //Bit[5] Enable edge enhancement threshold auto-adjustment for YUV output (Original 1) |
y_notsu | 0:03f32e3679c8 | 340 | //Bit[4] De-noise threshold auto-adjustment (0:Disable, 1:Enable)(Original 1) |
y_notsu | 0:03f32e3679c8 | 341 | //Bit[3] AWB gain enable (Original 1) |
y_notsu | 0:03f32e3679c8 | 342 | //Bit[2] Reserved |
y_notsu | 0:03f32e3679c8 | 343 | //Bit[1] Color matrix coefficient double option (0: Original, 1:Double) |
y_notsu | 0:03f32e3679c8 | 344 | //Bit[0] Reserved (Original 0) |
y_notsu | 0:03f32e3679c8 | 345 | { 0x56, 0x40 }, //Martix Coefficient Sign for Coefficient 5 to 0 |
y_notsu | 0:03f32e3679c8 | 346 | //Bit[7] Auto contrast center enable |
y_notsu | 0:03f32e3679c8 | 347 | //Bit[6] Reserved |
y_notsu | 0:03f32e3679c8 | 348 | //Bit[5:0] Matrix coefficient sign (0:Plus, 1:Minus) |
y_notsu | 0:03f32e3679c8 | 349 | { 0x34, 0x11 }, //Array Reference Control Bit[7:0] Reserved |
y_notsu | 0:03f32e3679c8 | 350 | { REG_COM11, COM11_EXP|COM11_HZAUTO }, //Common control 11 |
y_notsu | 0:03f32e3679c8 | 351 | //Bit[7] Night mode (0:disable, 1:Enable) |
y_notsu | 0:03f32e3679c8 | 352 | //Bit[6:5] Minimum frame rate of night mode |
y_notsu | 0:03f32e3679c8 | 353 | //00:same, 01:1/2, 10:1/4, 11:1/8 |
y_notsu | 0:03f32e3679c8 | 354 | //Bit[4] D56_Auto (0:Disable, 1:Enable) |
y_notsu | 0:03f32e3679c8 | 355 | //Bit[3] Banding filter value select |
y_notsu | 0:03f32e3679c8 | 356 | // 0: Select BD60ST, 1:Select BD50ST |
y_notsu | 0:03f32e3679c8 | 357 | //Bit[2] Reserved |
y_notsu | 0:03f32e3679c8 | 358 | //Bit[1] Exprosure timing can be less than limit of banding filter |
y_notsu | 0:03f32e3679c8 | 359 | //Bit[0] Reserved |
y_notsu | 0:03f32e3679c8 | 360 | { 0xa4, 0x88 }, { 0x96, 0 }, |
y_notsu | 0:03f32e3679c8 | 361 | { 0x97, 0x30 }, { 0x98, 0x20 }, |
y_notsu | 0:03f32e3679c8 | 362 | { 0x99, 0x30 }, { 0x9a, 0x84 }, |
y_notsu | 0:03f32e3679c8 | 363 | { 0x9b, 0x29 }, { 0x9c, 0x03 }, |
y_notsu | 0:03f32e3679c8 | 364 | { 0x9d, 0x4c }, { 0x9e, 0x3f }, |
y_notsu | 0:03f32e3679c8 | 365 | { 0x78, 0x04 }, |
y_notsu | 0:03f32e3679c8 | 366 | |
y_notsu | 0:03f32e3679c8 | 367 | /* Extra-weird stuff. Some sort of multiplexor register */ |
y_notsu | 0:03f32e3679c8 | 368 | { 0x79, 0x01 }, { 0xc8, 0xf0 }, |
y_notsu | 0:03f32e3679c8 | 369 | { 0x79, 0x0f }, { 0xc8, 0x00 }, |
y_notsu | 0:03f32e3679c8 | 370 | { 0x79, 0x10 }, { 0xc8, 0x7e }, |
y_notsu | 0:03f32e3679c8 | 371 | { 0x79, 0x0a }, { 0xc8, 0x80 }, |
y_notsu | 0:03f32e3679c8 | 372 | { 0x79, 0x0b }, { 0xc8, 0x01 }, |
y_notsu | 0:03f32e3679c8 | 373 | { 0x79, 0x0c }, { 0xc8, 0x0f }, |
y_notsu | 0:03f32e3679c8 | 374 | { 0x79, 0x0d }, { 0xc8, 0x20 }, |
y_notsu | 0:03f32e3679c8 | 375 | { 0x79, 0x09 }, { 0xc8, 0x80 }, |
y_notsu | 0:03f32e3679c8 | 376 | { 0x79, 0x02 }, { 0xc8, 0xc0 }, |
y_notsu | 0:03f32e3679c8 | 377 | { 0x79, 0x03 }, { 0xc8, 0x40 }, |
y_notsu | 0:03f32e3679c8 | 378 | { 0x79, 0x05 }, { 0xc8, 0x30 }, |
y_notsu | 0:03f32e3679c8 | 379 | { 0x79, 0x26 }, |
y_notsu | 0:03f32e3679c8 | 380 | |
y_notsu | 0:03f32e3679c8 | 381 | /* Added register value */ |
y_notsu | 0:03f32e3679c8 | 382 | //{ 0x30, 0x00 }, //REG_HSYSET (HSYNC Rising Edge Delay : 08 -> 00 |
y_notsu | 0:03f32e3679c8 | 383 | //{ 0x2A, 0x00 }, // Dummy Pixel insert MSB |
y_notsu | 0:03f32e3679c8 | 384 | //{ 0x2B, 0x00 }, // Dummy Pixel insert MSB |
y_notsu | 0:03f32e3679c8 | 385 | { 0x15, 0x05 }, // Common Control 10 : Bit[4] 1:PCLK negative |
y_notsu | 0:03f32e3679c8 | 386 | { 0x3A, 0x05 }, //Bit[7:6]: Reserved (origina:0b00) |
y_notsu | 0:03f32e3679c8 | 387 | //Bit[5]: Negative Image 0:Normal, 1:Negative (original:0) |
y_notsu | 0:03f32e3679c8 | 388 | //Bit[4]: UV output value 0:Normal, 1:User define (original:0) |
y_notsu | 0:03f32e3679c8 | 389 | //Bit[3]: Output sequence (original:1) |
y_notsu | 0:03f32e3679c8 | 390 | //Bit[2:1]:reserved |
y_notsu | 0:03f32e3679c8 | 391 | //Bit[0]: Auto output window |
y_notsu | 0:03f32e3679c8 | 392 | |
y_notsu | 0:03f32e3679c8 | 393 | { 0xff, 0xff }, /* END MARKER */ |
y_notsu | 0:03f32e3679c8 | 394 | }; |
y_notsu | 0:03f32e3679c8 | 395 | |
y_notsu | 0:03f32e3679c8 | 396 | static struct regval_list ov7670_fmt_rgb565[] = { |
y_notsu | 0:03f32e3679c8 | 397 | { REG_COM7, COM7_FMT_QVGA|COM7_RGB }, /* Selects RGB mode */ |
y_notsu | 0:03f32e3679c8 | 398 | { REG_RGB444, 0 }, /* No RGB444 please */ |
y_notsu | 0:03f32e3679c8 | 399 | { REG_COM1, 0x0 }, |
y_notsu | 0:03f32e3679c8 | 400 | { REG_COM15, 0xc0 | COM15_RGB565 }, |
y_notsu | 0:03f32e3679c8 | 401 | { REG_COM9, 0x28 }, /* 16x gain ceiling; 0x8 is reserved bit */ |
y_notsu | 0:03f32e3679c8 | 402 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ |
y_notsu | 0:03f32e3679c8 | 403 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ |
y_notsu | 0:03f32e3679c8 | 404 | { 0x51, 0 }, /* vb */ |
y_notsu | 0:03f32e3679c8 | 405 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
y_notsu | 0:03f32e3679c8 | 406 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ |
y_notsu | 0:03f32e3679c8 | 407 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ |
y_notsu | 0:03f32e3679c8 | 408 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, |
y_notsu | 0:03f32e3679c8 | 409 | { 0xff, 0xff }, |
y_notsu | 0:03f32e3679c8 | 410 | }; |
y_notsu | 0:03f32e3679c8 | 411 | |
y_notsu | 0:03f32e3679c8 | 412 | // QVGA setting |
y_notsu | 0:03f32e3679c8 | 413 | const int width = QVGA_WIDTH; |
y_notsu | 0:03f32e3679c8 | 414 | const int height= QVGA_HEIGHT; |
y_notsu | 0:03f32e3679c8 | 415 | const int com7_bit= COM7_FMT_QVGA; |
y_notsu | 0:03f32e3679c8 | 416 | const int hstart= 164; /* Empirically determined */ |
y_notsu | 0:03f32e3679c8 | 417 | const int hstop= 20; //Original code: 20 |
y_notsu | 0:03f32e3679c8 | 418 | const int vstart= 14; |
y_notsu | 0:03f32e3679c8 | 419 | const int vstop= 494; |
y_notsu | 0:03f32e3679c8 | 420 |