arm_shift_q7.c

00001 /* ----------------------------------------------------------------------    
00002 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.    
00003 *    
00004 * $Date:        19. March 2015
00005 * $Revision:    V.1.4.5
00006 *    
00007 * Project:      CMSIS DSP Library    
00008 * Title:        arm_shift_q7.c    
00009 *    
00010 * Description:  Processing function for the Q7 Shifting    
00011 *    
00012 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
00013 *  
00014 * Redistribution and use in source and binary forms, with or without 
00015 * modification, are permitted provided that the following conditions
00016 * are met:
00017 *   - Redistributions of source code must retain the above copyright
00018 *     notice, this list of conditions and the following disclaimer.
00019 *   - Redistributions in binary form must reproduce the above copyright
00020 *     notice, this list of conditions and the following disclaimer in
00021 *     the documentation and/or other materials provided with the 
00022 *     distribution.
00023 *   - Neither the name of ARM LIMITED nor the names of its contributors
00024 *     may be used to endorse or promote products derived from this
00025 *     software without specific prior written permission.
00026 *
00027 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00028 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00029 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00030 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
00031 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00032 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00033 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00034 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00035 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00036 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
00037 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00038 * POSSIBILITY OF SUCH DAMAGE.   
00039 * -------------------------------------------------------------------- */
00040 
00041 #include "arm_math.h"
00042 
00043 /**        
00044  * @ingroup groupMath        
00045  */
00046 
00047 /**        
00048  * @addtogroup shift        
00049  * @{        
00050  */
00051 
00052 
00053 /**        
00054  * @brief  Shifts the elements of a Q7 vector a specified number of bits.        
00055  * @param[in]  *pSrc points to the input vector        
00056  * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.        
00057  * @param[out]  *pDst points to the output vector        
00058  * @param[in]  blockSize number of samples in the vector        
00059  * @return none.        
00060  *    
00061  * \par Conditions for optimum performance    
00062  *  Input and output buffers should be aligned by 32-bit    
00063  *    
00064  *        
00065  * <b>Scaling and Overflow Behavior:</b>        
00066  * \par        
00067  * The function uses saturating arithmetic.        
00068  * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.        
00069  */
00070 
00071 void arm_shift_q7(
00072   q7_t * pSrc,
00073   int8_t shiftBits,
00074   q7_t * pDst,
00075   uint32_t blockSize)
00076 {
00077   uint32_t blkCnt;                               /* loop counter */
00078   uint8_t sign;                                  /* Sign of shiftBits */
00079 
00080 #ifndef ARM_MATH_CM0_FAMILY
00081 
00082 /* Run the below code for Cortex-M4 and Cortex-M3 */
00083   q7_t in1;                                      /* Input value1 */
00084   q7_t in2;                                      /* Input value2 */
00085   q7_t in3;                                      /* Input value3 */
00086   q7_t in4;                                      /* Input value4 */
00087 
00088 
00089   /*loop Unrolling */
00090   blkCnt = blockSize >> 2u;
00091 
00092   /* Getting the sign of shiftBits */
00093   sign = (shiftBits & 0x80);
00094 
00095   /* If the shift value is positive then do right shift else left shift */
00096   if(sign == 0u)
00097   {
00098     /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
00099      ** a second loop below computes the remaining 1 to 3 samples. */
00100     while(blkCnt > 0u)
00101     {
00102       /* C = A << shiftBits */
00103       /* Read 4 inputs */
00104       in1 = *pSrc;
00105       in2 = *(pSrc + 1);
00106       in3 = *(pSrc + 2);
00107       in4 = *(pSrc + 3);
00108 
00109       /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
00110       *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
00111                                    __SSAT((in2 << shiftBits), 8),
00112                                    __SSAT((in3 << shiftBits), 8),
00113                                    __SSAT((in4 << shiftBits), 8));
00114       /* Update source pointer to process next sampels */
00115       pSrc += 4u;
00116 
00117       /* Decrement the loop counter */
00118       blkCnt--;
00119     }
00120 
00121     /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
00122      ** No loop unrolling is used. */
00123     blkCnt = blockSize % 0x4u;
00124 
00125     while(blkCnt > 0u)
00126     {
00127       /* C = A << shiftBits */
00128       /* Shift the input and then store the result in the destination buffer. */
00129       *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
00130 
00131       /* Decrement the loop counter */
00132       blkCnt--;
00133     }
00134   }
00135   else
00136   {
00137     shiftBits = -shiftBits;
00138     /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
00139      ** a second loop below computes the remaining 1 to 3 samples. */
00140     while(blkCnt > 0u)
00141     {
00142       /* C = A >> shiftBits */
00143       /* Read 4 inputs */
00144       in1 = *pSrc;
00145       in2 = *(pSrc + 1);
00146       in3 = *(pSrc + 2);
00147       in4 = *(pSrc + 3);
00148 
00149       /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
00150       *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),
00151                                    (in3 >> shiftBits), (in4 >> shiftBits));
00152 
00153 
00154       pSrc += 4u;
00155 
00156       /* Decrement the loop counter */
00157       blkCnt--;
00158     }
00159 
00160     /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
00161      ** No loop unrolling is used. */
00162     blkCnt = blockSize % 0x4u;
00163 
00164     while(blkCnt > 0u)
00165     {
00166       /* C = A >> shiftBits */
00167       /* Shift the input and then store the result in the destination buffer. */
00168       in1 = *pSrc++;
00169       *pDst++ = (in1 >> shiftBits);
00170 
00171       /* Decrement the loop counter */
00172       blkCnt--;
00173     }
00174   }
00175 
00176 #else
00177 
00178   /* Run the below code for Cortex-M0 */
00179 
00180   /* Getting the sign of shiftBits */
00181   sign = (shiftBits & 0x80);
00182 
00183   /* If the shift value is positive then do right shift else left shift */
00184   if(sign == 0u)
00185   {
00186     /* Initialize blkCnt with number of samples */
00187     blkCnt = blockSize;
00188 
00189     while(blkCnt > 0u)
00190     {
00191       /* C = A << shiftBits */
00192       /* Shift the input and then store the result in the destination buffer. */
00193       *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
00194 
00195       /* Decrement the loop counter */
00196       blkCnt--;
00197     }
00198   }
00199   else
00200   {
00201     /* Initialize blkCnt with number of samples */
00202     blkCnt = blockSize;
00203 
00204     while(blkCnt > 0u)
00205     {
00206       /* C = A >> shiftBits */
00207       /* Shift the input and then store the result in the destination buffer. */
00208       *pDst++ = (*pSrc++ >> -shiftBits);
00209 
00210       /* Decrement the loop counter */
00211       blkCnt--;
00212     }
00213   }
00214 
00215 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
00216 }
00217 
00218 /**        
00219  * @} end of shift group        
00220  */