Raphael Kwon / Ethernet

BSD style socket API for W5500.

Dependencies:   W5500

Dependents:   W5500_Porting_WIZnetLib W5500_Porting_WIZnetLib W5500_Porting_WIZnetLib_LPC800

Fork of Ethernet by Raphael Kwon

wizchip_conf.c@2:ee0f7508fb5c, 2014-02-18 (annotated)

Committer:
xeon011
Date:
Tue Feb 18 05:41:48 2014 +0000
Revision:
2:ee0f7508fb5c
Parent:
0:9158fe13dc14 
First release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
xeon011 0:9158fe13dc14 1 //****************************************************************************/
xeon011 0:9158fe13dc14 2 //!
xeon011 0:9158fe13dc14 3 //! \file wizchip_conf.c
xeon011 0:9158fe13dc14 4 //! \brief WIZCHIP Config Header File.
xeon011 0:9158fe13dc14 5 //! \version 1.0.0
xeon011 0:9158fe13dc14 6 //! \date 2013/10/01
xeon011 0:9158fe13dc14 7 //! \par Revision history
xeon011 0:9158fe13dc14 8 //! <2013/10/01> 1st Release
xeon011 0:9158fe13dc14 9 //! \author MidnightCow
xeon011 0:9158fe13dc14 10 //! \copyright
xeon011 0:9158fe13dc14 11 //!
xeon011 0:9158fe13dc14 12 //! Copyright (c) 2013, WIZnet Co., LTD.
xeon011 0:9158fe13dc14 13 //! All rights reserved.
xeon011 0:9158fe13dc14 14 //!
xeon011 0:9158fe13dc14 15 //! Redistribution and use in source and binary forms, with or without
xeon011 0:9158fe13dc14 16 //! modification, are permitted provided that the following conditions
xeon011 0:9158fe13dc14 17 //! are met:
xeon011 0:9158fe13dc14 18 //!
xeon011 0:9158fe13dc14 19 //! * Redistributions of source code must retain the above copyright
xeon011 0:9158fe13dc14 20 //! notice, this list of conditions and the following disclaimer.
xeon011 0:9158fe13dc14 21 //! * Redistributions in binary form must reproduce the above copyright
xeon011 0:9158fe13dc14 22 //! notice, this list of conditions and the following disclaimer in the
xeon011 0:9158fe13dc14 23 //! documentation and/or other materials provided with the distribution.
xeon011 0:9158fe13dc14 24 //! * Neither the name of the <ORGANIZATION> nor the names of its
xeon011 0:9158fe13dc14 25 //! contributors may be used to endorse or promote products derived
xeon011 0:9158fe13dc14 26 //! from this software without specific prior written permission.
xeon011 0:9158fe13dc14 27 //!
xeon011 0:9158fe13dc14 28 //! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
xeon011 0:9158fe13dc14 29 //! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
xeon011 0:9158fe13dc14 30 //! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
xeon011 0:9158fe13dc14 31 //! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
xeon011 0:9158fe13dc14 32 //! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
xeon011 0:9158fe13dc14 33 //! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
xeon011 0:9158fe13dc14 34 //! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
xeon011 0:9158fe13dc14 35 //! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
xeon011 0:9158fe13dc14 36 //! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
xeon011 0:9158fe13dc14 37 //! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
xeon011 0:9158fe13dc14 38 //! THE POSSIBILITY OF SUCH DAMAGE.
xeon011 0:9158fe13dc14 39 //
xeon011 0:9158fe13dc14 40 //*****************************************************************************/
xeon011 0:9158fe13dc14 41 #include "wizchip_conf.h"
xeon011 0:9158fe13dc14 42 /**
xeon011 0:9158fe13dc14 43 * @brief Default function to enable interrupt.
xeon011 0:9158fe13dc14 44 * @note This function help not to access wrong address. If you do not describe this function or register any functions,
xeon011 0:9158fe13dc14 45 * null function is called.
xeon011 0:9158fe13dc14 46 */
xeon011 0:9158fe13dc14 47 void wizchip_cris_enter(void) {};
xeon011 0:9158fe13dc14 48 /**
xeon011 0:9158fe13dc14 49 * @brief Default function to disable interrupt.
xeon011 0:9158fe13dc14 50 * @note This function help not to access wrong address. If you do not describe this function or register any functions,
xeon011 0:9158fe13dc14 51 * null function is called.
xeon011 0:9158fe13dc14 52 */
xeon011 0:9158fe13dc14 53 void wizchip_cris_exit(void) {};
xeon011 0:9158fe13dc14 54 /**
xeon011 0:9158fe13dc14 55 * @brief Default function to select chip.
xeon011 0:9158fe13dc14 56 * @note This function help not to access wrong address. If you do not describe this function or register any functions,
xeon011 0:9158fe13dc14 57 * null function is called.
xeon011 0:9158fe13dc14 58 */
xeon011 0:9158fe13dc14 59 void wizchip_cs_select(void) {};
xeon011 0:9158fe13dc14 60 /**
xeon011 0:9158fe13dc14 61 * @brief Default function to deselect chip.
xeon011 0:9158fe13dc14 62 * @note This function help not to access wrong address. If you do not describe this function or register any functions,
xeon011 0:9158fe13dc14 63 * null function is called.
xeon011 0:9158fe13dc14 64 */
xeon011 0:9158fe13dc14 65 void wizchip_cs_deselect(void) {};
xeon011 0:9158fe13dc14 66 /**
xeon011 0:9158fe13dc14 67 * @brief Default function to read in direct or indirect interface.
xeon011 0:9158fe13dc14 68 * @note This function help not to access wrong address. If you do not describe this function or register any functions,
xeon011 0:9158fe13dc14 69 * null function is called.
xeon011 0:9158fe13dc14 70 */
xeon011 0:9158fe13dc14 71 uint8_t wizchip_bus_readbyte(uint32_t AddrSel) { return * ((volatile uint8_t *) AddrSel); };
xeon011 0:9158fe13dc14 72 /**
xeon011 0:9158fe13dc14 73 * @brief Default function to write in direct or indirect interface.
xeon011 0:9158fe13dc14 74 * @note This function help not to access wrong address. If you do not describe this function or register any functions,
xeon011 0:9158fe13dc14 75 * null function is called.
xeon011 0:9158fe13dc14 76 */
xeon011 0:9158fe13dc14 77
xeon011 0:9158fe13dc14 78 void wizchip_bus_writebyte(uint32_t AddrSel, uint8_t wb) { *((volatile uint8_t*)AddrSel) = wb; };
xeon011 0:9158fe13dc14 79 /**
xeon011 0:9158fe13dc14 80 * @brief Default function to read in SPI interface.
xeon011 0:9158fe13dc14 81 * @note This function help not to access wrong address. If you do not describe this function or register any functions,
xeon011 0:9158fe13dc14 82 * null function is called.
xeon011 0:9158fe13dc14 83 */
xeon011 0:9158fe13dc14 84 uint8_t wizchip_spi_readbyte(void) {return 0;};
xeon011 0:9158fe13dc14 85 /**
xeon011 0:9158fe13dc14 86 * @brief Default function to write in SPI interface.
xeon011 0:9158fe13dc14 87 * @note This function help not to access wrong address. If you do not describe this function or register any functions,
xeon011 0:9158fe13dc14 88 * null function is called.
xeon011 0:9158fe13dc14 89 */
xeon011 0:9158fe13dc14 90 void wizchip_spi_writebyte(uint8_t wb) {};
xeon011 0:9158fe13dc14 91
xeon011 0:9158fe13dc14 92 /**
xeon011 0:9158fe13dc14 93 * @\ref _WIZCHIP instance
xeon011 0:9158fe13dc14 94 */
xeon011 0:9158fe13dc14 95 _WIZCHIP WIZCHIP =
xeon011 0:9158fe13dc14 96 {
xeon011 0:9158fe13dc14 97 .id = _WIZCHIP_ID_,
xeon011 0:9158fe13dc14 98 .if_mode = _WIZCHIP_IO_MODE_,
xeon011 0:9158fe13dc14 99 .CRIS._enter = wizchip_cris_enter,
xeon011 0:9158fe13dc14 100 .CRIS._exit = wizchip_cris_exit,
xeon011 0:9158fe13dc14 101 .CS._select = wizchip_cs_select,
xeon011 0:9158fe13dc14 102 .CS._deselect = wizchip_cs_deselect,
xeon011 0:9158fe13dc14 103 .IF.BUS._read_byte = wizchip_bus_readbyte,
xeon011 0:9158fe13dc14 104 .IF.BUS._write_byte = wizchip_bus_writebyte
xeon011 0:9158fe13dc14 105 // .IF.SPI._read_byte = wizchip_spi_readbyte,
xeon011 0:9158fe13dc14 106 // .IF.SPI._write_byte = wizchip_spi_writebyte
xeon011 0:9158fe13dc14 107 };
xeon011 0:9158fe13dc14 108
xeon011 0:9158fe13dc14 109 static uint8_t _DNS_[4]; // DNS server ip address
xeon011 0:9158fe13dc14 110 static dhcp_mode _DHCP_; // DHCP mode
xeon011 0:9158fe13dc14 111
xeon011 0:9158fe13dc14 112 void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void))
xeon011 0:9158fe13dc14 113 {
xeon011 0:9158fe13dc14 114 if(!cris_en || !cris_ex)
xeon011 0:9158fe13dc14 115 {
xeon011 0:9158fe13dc14 116 WIZCHIP.CRIS._enter = wizchip_cris_enter;
xeon011 0:9158fe13dc14 117 WIZCHIP.CRIS._exit = wizchip_cris_exit;
xeon011 0:9158fe13dc14 118 }
xeon011 0:9158fe13dc14 119 else
xeon011 0:9158fe13dc14 120 {
xeon011 0:9158fe13dc14 121 WIZCHIP.CRIS._enter = cris_en;
xeon011 0:9158fe13dc14 122 WIZCHIP.CRIS._exit = cris_ex;
xeon011 0:9158fe13dc14 123 }
xeon011 0:9158fe13dc14 124 }
xeon011 0:9158fe13dc14 125
xeon011 0:9158fe13dc14 126 void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void))
xeon011 0:9158fe13dc14 127 {
xeon011 0:9158fe13dc14 128 if(!cs_sel || !cs_desel)
xeon011 0:9158fe13dc14 129 {
xeon011 0:9158fe13dc14 130 WIZCHIP.CS._select = wizchip_cs_select;
xeon011 0:9158fe13dc14 131 WIZCHIP.CS._deselect = wizchip_cs_deselect;
xeon011 0:9158fe13dc14 132 }
xeon011 0:9158fe13dc14 133 else
xeon011 0:9158fe13dc14 134 {
xeon011 0:9158fe13dc14 135 WIZCHIP.CS._select = cs_sel;
xeon011 0:9158fe13dc14 136 WIZCHIP.CS._deselect = cs_desel;
xeon011 0:9158fe13dc14 137 }
xeon011 0:9158fe13dc14 138 }
xeon011 0:9158fe13dc14 139
xeon011 0:9158fe13dc14 140 void reg_wizchip_bus_cbfunc(uint8_t(*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, uint8_t wb))
xeon011 0:9158fe13dc14 141 {
xeon011 0:9158fe13dc14 142 while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_BUS_));
xeon011 0:9158fe13dc14 143
xeon011 0:9158fe13dc14 144 if(!bus_rb || !bus_wb)
xeon011 0:9158fe13dc14 145 {
xeon011 0:9158fe13dc14 146 WIZCHIP.IF.BUS._read_byte = wizchip_bus_readbyte;
xeon011 0:9158fe13dc14 147 WIZCHIP.IF.BUS._write_byte = wizchip_bus_writebyte;
xeon011 0:9158fe13dc14 148 }
xeon011 0:9158fe13dc14 149 else
xeon011 0:9158fe13dc14 150 {
xeon011 0:9158fe13dc14 151 WIZCHIP.IF.BUS._read_byte = bus_rb;
xeon011 0:9158fe13dc14 152 WIZCHIP.IF.BUS._write_byte = bus_wb;
xeon011 0:9158fe13dc14 153 }
xeon011 0:9158fe13dc14 154 }
xeon011 0:9158fe13dc14 155
xeon011 0:9158fe13dc14 156 void reg_wizchip_spi_cbfunc(uint8_t (*spi_rb)(void), void (*spi_wb)(uint8_t wb))
xeon011 0:9158fe13dc14 157 {
xeon011 0:9158fe13dc14 158 while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
xeon011 0:9158fe13dc14 159
xeon011 0:9158fe13dc14 160 if(!spi_rb || !spi_wb)
xeon011 0:9158fe13dc14 161 {
xeon011 0:9158fe13dc14 162 WIZCHIP.IF.SPI._read_byte = wizchip_spi_readbyte;
xeon011 0:9158fe13dc14 163 WIZCHIP.IF.SPI._write_byte = wizchip_spi_writebyte;
xeon011 0:9158fe13dc14 164 }
xeon011 0:9158fe13dc14 165 else
xeon011 0:9158fe13dc14 166 {
xeon011 0:9158fe13dc14 167 WIZCHIP.IF.SPI._read_byte = spi_rb;
xeon011 0:9158fe13dc14 168 WIZCHIP.IF.SPI._write_byte = spi_wb;
xeon011 0:9158fe13dc14 169 }
xeon011 0:9158fe13dc14 170 }
xeon011 0:9158fe13dc14 171
xeon011 0:9158fe13dc14 172 int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg)
xeon011 0:9158fe13dc14 173 {
xeon011 0:9158fe13dc14 174 uint8_t tmp = 0;
xeon011 0:9158fe13dc14 175 uint8_t* ptmp[2] = {0,0};
xeon011 0:9158fe13dc14 176 switch(cwtype)
xeon011 0:9158fe13dc14 177 {
xeon011 0:9158fe13dc14 178 case CW_RESET_WIZCHIP:
xeon011 0:9158fe13dc14 179 wizchip_sw_reset();
xeon011 0:9158fe13dc14 180 break;
xeon011 0:9158fe13dc14 181 case CW_INIT_WIZCHIP:
xeon011 0:9158fe13dc14 182 if(arg != 0)
xeon011 0:9158fe13dc14 183 {
xeon011 0:9158fe13dc14 184 ptmp[0] = (uint8_t*)arg;
xeon011 0:9158fe13dc14 185 ptmp[1] = ptmp[0] + _WIZCHIP_SOCK_NUM_;
xeon011 0:9158fe13dc14 186 }
xeon011 0:9158fe13dc14 187 return wizchip_init(ptmp[0], ptmp[1]);
xeon011 0:9158fe13dc14 188 case CW_CLR_INTERRUPT:
xeon011 0:9158fe13dc14 189 wizchip_clrinterrupt(*((intr_kind*)arg));
xeon011 0:9158fe13dc14 190 break;
xeon011 0:9158fe13dc14 191 case CW_GET_INTERRUPT:
xeon011 0:9158fe13dc14 192 *((intr_kind*)arg) = wizchip_getinterrupt();
xeon011 0:9158fe13dc14 193 break;
xeon011 0:9158fe13dc14 194 case CW_SET_INTRMASK:
xeon011 0:9158fe13dc14 195 wizchip_setinterruptmask(*((intr_kind*)arg));
xeon011 0:9158fe13dc14 196 break;
xeon011 0:9158fe13dc14 197 case CW_GET_INTRMASK:
xeon011 0:9158fe13dc14 198 *((intr_kind*)arg) = wizchip_getinterruptmask();
xeon011 0:9158fe13dc14 199 break;
xeon011 0:9158fe13dc14 200 #if _WIZCHIP_ > 5100
xeon011 0:9158fe13dc14 201 case CW_SET_INTRTIME:
xeon011 0:9158fe13dc14 202 setINTLEVEL(*(uint16_t*)arg);
xeon011 0:9158fe13dc14 203 break;
xeon011 0:9158fe13dc14 204 case CW_GET_INTRTIME:
xeon011 0:9158fe13dc14 205 *(uint16_t*)arg = getINTLEVEL();
xeon011 0:9158fe13dc14 206 break;
xeon011 0:9158fe13dc14 207 #endif
xeon011 0:9158fe13dc14 208 case CW_GET_ID:
xeon011 0:9158fe13dc14 209 ((uint8_t*)arg)[0] = WIZCHIP.id[0];
xeon011 0:9158fe13dc14 210 ((uint8_t*)arg)[1] = WIZCHIP.id[1];
xeon011 0:9158fe13dc14 211 ((uint8_t*)arg)[2] = WIZCHIP.id[2];
xeon011 0:9158fe13dc14 212 ((uint8_t*)arg)[3] = WIZCHIP.id[3];
xeon011 0:9158fe13dc14 213 ((uint8_t*)arg)[4] = WIZCHIP.id[4];
xeon011 0:9158fe13dc14 214 ((uint8_t*)arg)[5] = 0;
xeon011 0:9158fe13dc14 215 break;
xeon011 0:9158fe13dc14 216 #if _WIZCHIP_ == 5500
xeon011 0:9158fe13dc14 217 case CW_RESET_PHY:
xeon011 0:9158fe13dc14 218 wizphy_reset();
xeon011 0:9158fe13dc14 219 break;
xeon011 0:9158fe13dc14 220 case CW_SET_PHYCONF:
xeon011 0:9158fe13dc14 221 wizphy_setphyconf((wiz_PhyConf*)arg);
xeon011 0:9158fe13dc14 222 break;
xeon011 0:9158fe13dc14 223 case CW_GET_PHYCONF:
xeon011 0:9158fe13dc14 224 wizphy_getphyconf((wiz_PhyConf*)arg);
xeon011 0:9158fe13dc14 225 break;
xeon011 0:9158fe13dc14 226 case CW_GET_PHYSTATUS:
xeon011 0:9158fe13dc14 227 break;
xeon011 0:9158fe13dc14 228 case CW_SET_PHYPOWMODE:
xeon011 0:9158fe13dc14 229 return wizphy_setphypmode(*(uint8_t*)arg);
xeon011 0:9158fe13dc14 230 #endif
xeon011 0:9158fe13dc14 231 case CW_GET_PHYPOWMODE:
xeon011 0:9158fe13dc14 232 tmp = wizphy_getphypmode();
xeon011 0:9158fe13dc14 233 if((int8_t)tmp == -1) return -1;
xeon011 0:9158fe13dc14 234 *(uint8_t*)arg = tmp;
xeon011 0:9158fe13dc14 235 break;
xeon011 0:9158fe13dc14 236 case CW_GET_PHYLINK:
xeon011 0:9158fe13dc14 237 tmp = wizphy_getphylink();
xeon011 0:9158fe13dc14 238 if((int8_t)tmp == -1) return -1;
xeon011 0:9158fe13dc14 239 *(uint8_t*)arg = tmp;
xeon011 0:9158fe13dc14 240 break;
xeon011 0:9158fe13dc14 241 default:
xeon011 0:9158fe13dc14 242 return -1;
xeon011 0:9158fe13dc14 243 }
xeon011 0:9158fe13dc14 244 return 0;
xeon011 0:9158fe13dc14 245 }
xeon011 0:9158fe13dc14 246
xeon011 0:9158fe13dc14 247
xeon011 0:9158fe13dc14 248 int8_t ctlnetwork(ctlnetwork_type cntype, void* arg)
xeon011 0:9158fe13dc14 249 {
xeon011 0:9158fe13dc14 250
xeon011 0:9158fe13dc14 251 switch(cntype)
xeon011 0:9158fe13dc14 252 {
xeon011 0:9158fe13dc14 253 case CN_SET_NETINFO:
xeon011 0:9158fe13dc14 254 wizchip_setnetinfo((wiz_NetInfo*)arg);
xeon011 0:9158fe13dc14 255 break;
xeon011 0:9158fe13dc14 256 case CN_GET_NETINFO:
xeon011 0:9158fe13dc14 257 wizchip_getnetinfo((wiz_NetInfo*)arg);
xeon011 0:9158fe13dc14 258 break;
xeon011 0:9158fe13dc14 259 case CN_SET_NETMODE:
xeon011 0:9158fe13dc14 260 return wizchip_setnetmode(*(netmode_type*)arg);
xeon011 0:9158fe13dc14 261 case CN_GET_NETMODE:
xeon011 0:9158fe13dc14 262 *(netmode_type*)arg = wizchip_getnetmode();
xeon011 0:9158fe13dc14 263 break;
xeon011 0:9158fe13dc14 264 case CN_SET_TIMEOUT:
xeon011 0:9158fe13dc14 265 wizchip_settimeout((wiz_NetTimeout*)arg);
xeon011 0:9158fe13dc14 266 break;
xeon011 0:9158fe13dc14 267 case CN_GET_TIMEOUT:
xeon011 0:9158fe13dc14 268 wizchip_gettimeout((wiz_NetTimeout*)arg);
xeon011 0:9158fe13dc14 269 break;
xeon011 0:9158fe13dc14 270 default:
xeon011 0:9158fe13dc14 271 return -1;
xeon011 0:9158fe13dc14 272 }
xeon011 0:9158fe13dc14 273 return 0;
xeon011 0:9158fe13dc14 274 }
xeon011 0:9158fe13dc14 275
xeon011 0:9158fe13dc14 276 void wizchip_sw_reset(void)
xeon011 0:9158fe13dc14 277 {
xeon011 0:9158fe13dc14 278 uint8_t gw[4], sn[4], sip[4];
xeon011 0:9158fe13dc14 279 uint8_t mac[6];
xeon011 0:9158fe13dc14 280 getSHAR(mac);
xeon011 0:9158fe13dc14 281 getGAR(gw); getSUBR(sn); getSIPR(sip);
xeon011 0:9158fe13dc14 282 setMR(MR_RST);
xeon011 0:9158fe13dc14 283 getMR(); // for delay
xeon011 0:9158fe13dc14 284 setSHAR(mac);
xeon011 0:9158fe13dc14 285 setGAR(gw);
xeon011 0:9158fe13dc14 286 setSUBR(sn);
xeon011 0:9158fe13dc14 287 setSIPR(sip);
xeon011 0:9158fe13dc14 288 }
xeon011 0:9158fe13dc14 289
xeon011 0:9158fe13dc14 290 int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize)
xeon011 0:9158fe13dc14 291 {
xeon011 0:9158fe13dc14 292 int8_t i;
xeon011 0:9158fe13dc14 293 int8_t tmp = 0;
xeon011 0:9158fe13dc14 294 wizchip_sw_reset();
xeon011 0:9158fe13dc14 295 if(txsize)
xeon011 0:9158fe13dc14 296 {
xeon011 0:9158fe13dc14 297 tmp = 0;
xeon011 0:9158fe13dc14 298 for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
xeon011 0:9158fe13dc14 299 tmp += txsize[i];
xeon011 0:9158fe13dc14 300 if(tmp > 16) return -1;
xeon011 0:9158fe13dc14 301 for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
xeon011 0:9158fe13dc14 302 setSn_TXBUF_SIZE(i, txsize[i]);
xeon011 0:9158fe13dc14 303 }
xeon011 0:9158fe13dc14 304 if(rxsize)
xeon011 0:9158fe13dc14 305 {
xeon011 0:9158fe13dc14 306 tmp = 0;
xeon011 0:9158fe13dc14 307 for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
xeon011 0:9158fe13dc14 308 tmp += rxsize[i];
xeon011 0:9158fe13dc14 309 if(tmp > 16) return -1;
xeon011 0:9158fe13dc14 310 for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
xeon011 0:9158fe13dc14 311 setSn_RXBUF_SIZE(i, rxsize[i]);
xeon011 0:9158fe13dc14 312 }
xeon011 0:9158fe13dc14 313 return 0;
xeon011 0:9158fe13dc14 314 }
xeon011 0:9158fe13dc14 315
xeon011 0:9158fe13dc14 316 void wizchip_clrinterrupt(intr_kind intr)
xeon011 0:9158fe13dc14 317 {
xeon011 0:9158fe13dc14 318 uint8_t ir = (uint8_t)intr;
xeon011 0:9158fe13dc14 319 uint8_t sir = (uint8_t)((uint16_t)intr >> 8);
xeon011 0:9158fe13dc14 320 #if _WIZCHIP_ < 5500
xeon011 0:9158fe13dc14 321 ir |= (1<<4); // IK_WOL
xeon011 0:9158fe13dc14 322 #endif
xeon011 0:9158fe13dc14 323 #if _WIZCHIP_ == 5200
xeon011 0:9158fe13dc14 324 ir |= (1 << 6);
xeon011 0:9158fe13dc14 325 #endif
xeon011 0:9158fe13dc14 326
xeon011 0:9158fe13dc14 327 #if _WIZCHIP_ < 5200
xeon011 0:9158fe13dc14 328 sir &= 0x0F;
xeon011 0:9158fe13dc14 329 #endif
xeon011 0:9158fe13dc14 330
xeon011 0:9158fe13dc14 331 #if _WIZCHIP_ == 5100
xeon011 0:9158fe13dc14 332 ir |= sir;
xeon011 0:9158fe13dc14 333 setIR(ir);
xeon011 0:9158fe13dc14 334 #else
xeon011 0:9158fe13dc14 335 setIR(ir);
xeon011 0:9158fe13dc14 336 setSIR(sir);
xeon011 0:9158fe13dc14 337 #endif
xeon011 0:9158fe13dc14 338 }
xeon011 0:9158fe13dc14 339
xeon011 0:9158fe13dc14 340 intr_kind wizchip_getinterrupt(void)
xeon011 0:9158fe13dc14 341 {
xeon011 0:9158fe13dc14 342 uint8_t ir = 0;
xeon011 0:9158fe13dc14 343 uint8_t sir = 0;
xeon011 0:9158fe13dc14 344 uint16_t ret = 0;
xeon011 0:9158fe13dc14 345 #if _WIZCHIP_ == 5100
xeon011 0:9158fe13dc14 346 ir = getIR();
xeon011 0:9158fe13dc14 347 sir = ir 0x0F;
xeon011 0:9158fe13dc14 348 #else
xeon011 0:9158fe13dc14 349 ir = getIR();
xeon011 0:9158fe13dc14 350 sir = getSIR();
xeon011 0:9158fe13dc14 351 #endif
xeon011 0:9158fe13dc14 352
xeon011 0:9158fe13dc14 353 #if _WIZCHIP_ < 5500
xeon011 0:9158fe13dc14 354 ir &= ~(1<<4); // IK_WOL
xeon011 0:9158fe13dc14 355 #endif
xeon011 0:9158fe13dc14 356 #if _WIZCHIP_ == 5200
xeon011 0:9158fe13dc14 357 ir &= ~(1 << 6);
xeon011 0:9158fe13dc14 358 #endif
xeon011 0:9158fe13dc14 359 ret = sir;
xeon011 0:9158fe13dc14 360 ret = (ret << 8) + ir;
xeon011 0:9158fe13dc14 361 return (intr_kind)ret;
xeon011 0:9158fe13dc14 362 }
xeon011 0:9158fe13dc14 363
xeon011 0:9158fe13dc14 364 void wizchip_setinterruptmask(intr_kind intr)
xeon011 0:9158fe13dc14 365 {
xeon011 0:9158fe13dc14 366 uint8_t imr = (uint8_t)intr;
xeon011 0:9158fe13dc14 367 uint8_t simr = (uint8_t)((uint16_t)intr >> 8);
xeon011 0:9158fe13dc14 368 #if _WIZCHIP_ < 5500
xeon011 0:9158fe13dc14 369 imr &= ~(1<<4); // IK_WOL
xeon011 0:9158fe13dc14 370 #endif
xeon011 0:9158fe13dc14 371 #if _WIZCHIP_ == 5200
xeon011 0:9158fe13dc14 372 imr &= ~(1 << 6);
xeon011 0:9158fe13dc14 373 #endif
xeon011 0:9158fe13dc14 374
xeon011 0:9158fe13dc14 375 #if _WIZCHIP_ < 5200
xeon011 0:9158fe13dc14 376 simr &= 0x0F;
xeon011 0:9158fe13dc14 377 #endif
xeon011 0:9158fe13dc14 378
xeon011 0:9158fe13dc14 379 #if _WIZCHIP_ == 5100
xeon011 0:9158fe13dc14 380 imr |= simr;
xeon011 0:9158fe13dc14 381 setIMR(imr);
xeon011 0:9158fe13dc14 382 #else
xeon011 0:9158fe13dc14 383 setIMR(imr);
xeon011 0:9158fe13dc14 384 setSIMR(simr);
xeon011 0:9158fe13dc14 385 #endif
xeon011 0:9158fe13dc14 386 }
xeon011 0:9158fe13dc14 387
xeon011 0:9158fe13dc14 388 intr_kind wizchip_getinterruptmask(void)
xeon011 0:9158fe13dc14 389 {
xeon011 0:9158fe13dc14 390 uint8_t imr = 0;
xeon011 0:9158fe13dc14 391 uint8_t simr = 0;
xeon011 0:9158fe13dc14 392 uint16_t ret = 0;
xeon011 0:9158fe13dc14 393 #if _WIZCHIP_ == 5100
xeon011 0:9158fe13dc14 394 imr = getIMR();
xeon011 0:9158fe13dc14 395 simr = imr 0x0F;
xeon011 0:9158fe13dc14 396 #else
xeon011 0:9158fe13dc14 397 imr = getIMR();
xeon011 0:9158fe13dc14 398 simr = getSIMR();
xeon011 0:9158fe13dc14 399 #endif
xeon011 0:9158fe13dc14 400
xeon011 0:9158fe13dc14 401 #if _WIZCHIP_ < 5500
xeon011 0:9158fe13dc14 402 imr &= ~(1<<4); // IK_WOL
xeon011 0:9158fe13dc14 403 #endif
xeon011 0:9158fe13dc14 404 #if _WIZCHIP_ == 5200
xeon011 0:9158fe13dc14 405 imr &= ~(1 << 6); // IK_DEST_UNREACH
xeon011 0:9158fe13dc14 406 #endif
xeon011 0:9158fe13dc14 407 ret = simr;
xeon011 0:9158fe13dc14 408 ret = (ret << 8) + imr;
xeon011 0:9158fe13dc14 409 return (intr_kind)ret;
xeon011 0:9158fe13dc14 410 }
xeon011 0:9158fe13dc14 411
xeon011 0:9158fe13dc14 412 int8_t wizphy_getphylink(void)
xeon011 0:9158fe13dc14 413 {
xeon011 0:9158fe13dc14 414 int8_t tmp;
xeon011 0:9158fe13dc14 415 #if _WIZCHIP_ == 5200
xeon011 0:9158fe13dc14 416 if(getPHYSTATUS() & PHYSTATUS_LINK)
xeon011 0:9158fe13dc14 417 tmp = PHY_LINK_ON;
xeon011 0:9158fe13dc14 418 else
xeon011 0:9158fe13dc14 419 tmp = PHY_LINK_OFF;
xeon011 0:9158fe13dc14 420 #elif _WIZCHIP_ == 5500
xeon011 0:9158fe13dc14 421 if(getPHYCFGR() & PHYCFGR_LNK_ON)
xeon011 0:9158fe13dc14 422 tmp = PHY_LINK_ON;
xeon011 0:9158fe13dc14 423 else
xeon011 0:9158fe13dc14 424 tmp = PHY_LINK_OFF;
xeon011 0:9158fe13dc14 425 #else
xeon011 0:9158fe13dc14 426 tmp = -1;
xeon011 0:9158fe13dc14 427 #endif
xeon011 0:9158fe13dc14 428 return tmp;
xeon011 0:9158fe13dc14 429 }
xeon011 0:9158fe13dc14 430
xeon011 0:9158fe13dc14 431 #if _WIZCHIP_ > 5100
xeon011 0:9158fe13dc14 432
xeon011 0:9158fe13dc14 433 int8_t wizphy_getphypmode(void)
xeon011 0:9158fe13dc14 434 {
xeon011 0:9158fe13dc14 435 int8_t tmp = 0;
xeon011 0:9158fe13dc14 436 #if _WIZCHIP_ == 5200
xeon011 0:9158fe13dc14 437 if(getPHYSTATUS() & PHYSTATUS_POWERDOWN)
xeon011 0:9158fe13dc14 438 tmp = PHY_POWER_DOWN;
xeon011 0:9158fe13dc14 439 else
xeon011 0:9158fe13dc14 440 tmp = PHY_POWER_NORM;
xeon011 0:9158fe13dc14 441 #elif _WIZCHIP_ == 5500
xeon011 0:9158fe13dc14 442 if(getPHYCFGR() & PHYCFGR_OPMDC_PDOWN)
xeon011 0:9158fe13dc14 443 tmp = PHY_POWER_DOWN;
xeon011 0:9158fe13dc14 444 else
xeon011 0:9158fe13dc14 445 tmp = PHY_POWER_NORM;
xeon011 0:9158fe13dc14 446 #else
xeon011 0:9158fe13dc14 447 tmp = -1;
xeon011 0:9158fe13dc14 448 #endif
xeon011 0:9158fe13dc14 449 return tmp;
xeon011 0:9158fe13dc14 450 }
xeon011 0:9158fe13dc14 451 #endif
xeon011 0:9158fe13dc14 452
xeon011 0:9158fe13dc14 453 #if _WIZCHIP_ == 5500
xeon011 0:9158fe13dc14 454 void wizphy_reset(void)
xeon011 0:9158fe13dc14 455 {
xeon011 0:9158fe13dc14 456 uint8_t tmp = getPHYCFGR();
xeon011 0:9158fe13dc14 457 tmp &= PHYCFGR_RST;
xeon011 0:9158fe13dc14 458 setPHYCFGR(tmp);
xeon011 0:9158fe13dc14 459 tmp = getPHYCFGR();
xeon011 0:9158fe13dc14 460 tmp |= ~PHYCFGR_RST;
xeon011 0:9158fe13dc14 461 setPHYCFGR(tmp);
xeon011 0:9158fe13dc14 462 }
xeon011 0:9158fe13dc14 463
xeon011 0:9158fe13dc14 464 void wizphy_setphyconf(wiz_PhyConf* phyconf)
xeon011 0:9158fe13dc14 465 {
xeon011 0:9158fe13dc14 466 uint8_t tmp = 0;
xeon011 0:9158fe13dc14 467 if(phyconf->by == PHY_CONFBY_SW)
xeon011 0:9158fe13dc14 468 tmp |= PHYCFGR_OPMD;
xeon011 0:9158fe13dc14 469 else
xeon011 0:9158fe13dc14 470 tmp &= ~PHYCFGR_OPMD;
xeon011 0:9158fe13dc14 471 if(phyconf->mode == PHY_MODE_AUTONEGO)
xeon011 0:9158fe13dc14 472 tmp |= PHYCFGR_OPMDC_ALLA;
xeon011 0:9158fe13dc14 473 else
xeon011 0:9158fe13dc14 474 {
xeon011 0:9158fe13dc14 475 if(phyconf->duplex == PHY_DUPLEX_FULL)
xeon011 0:9158fe13dc14 476 {
xeon011 0:9158fe13dc14 477 if(phyconf->speed == PHY_SPEED_100)
xeon011 0:9158fe13dc14 478 tmp |= PHYCFGR_OPMDC_100F;
xeon011 0:9158fe13dc14 479 else
xeon011 0:9158fe13dc14 480 tmp |= PHYCFGR_OPMDC_10F;
xeon011 0:9158fe13dc14 481 }
xeon011 0:9158fe13dc14 482 else
xeon011 0:9158fe13dc14 483 {
xeon011 0:9158fe13dc14 484 if(phyconf->speed == PHY_SPEED_100)
xeon011 0:9158fe13dc14 485 tmp |= PHYCFGR_OPMDC_100H;
xeon011 0:9158fe13dc14 486 else
xeon011 0:9158fe13dc14 487 tmp |= PHYCFGR_OPMDC_10H;
xeon011 0:9158fe13dc14 488 }
xeon011 0:9158fe13dc14 489 }
xeon011 0:9158fe13dc14 490 setPHYCFGR(tmp);
xeon011 0:9158fe13dc14 491 wizphy_reset();
xeon011 0:9158fe13dc14 492 }
xeon011 0:9158fe13dc14 493
xeon011 0:9158fe13dc14 494 void wizphy_getphyconf(wiz_PhyConf* phyconf)
xeon011 0:9158fe13dc14 495 {
xeon011 0:9158fe13dc14 496 uint8_t tmp = 0;
xeon011 0:9158fe13dc14 497 tmp = getPHYCFGR();
xeon011 0:9158fe13dc14 498 phyconf->by = (tmp & PHYCFGR_OPMD) ? PHY_CONFBY_SW : PHY_CONFBY_HW;
xeon011 0:9158fe13dc14 499 switch(tmp & PHYCFGR_OPMDC_ALLA)
xeon011 0:9158fe13dc14 500 {
xeon011 0:9158fe13dc14 501 case PHYCFGR_OPMDC_ALLA:
xeon011 0:9158fe13dc14 502 case PHYCFGR_OPMDC_100FA:
xeon011 0:9158fe13dc14 503 phyconf->mode = PHY_MODE_AUTONEGO;
xeon011 0:9158fe13dc14 504 break;
xeon011 0:9158fe13dc14 505 default:
xeon011 0:9158fe13dc14 506 phyconf->mode = PHY_MODE_MANUAL;
xeon011 0:9158fe13dc14 507 break;
xeon011 0:9158fe13dc14 508 }
xeon011 0:9158fe13dc14 509 switch(tmp & PHYCFGR_OPMDC_ALLA)
xeon011 0:9158fe13dc14 510 {
xeon011 0:9158fe13dc14 511 case PHYCFGR_OPMDC_100FA:
xeon011 0:9158fe13dc14 512 case PHYCFGR_OPMDC_100F:
xeon011 0:9158fe13dc14 513 case PHYCFGR_OPMDC_100H:
xeon011 0:9158fe13dc14 514 phyconf->speed = PHY_SPEED_100;
xeon011 0:9158fe13dc14 515 break;
xeon011 0:9158fe13dc14 516 default:
xeon011 0:9158fe13dc14 517 phyconf->speed = PHY_SPEED_10;
xeon011 0:9158fe13dc14 518 break;
xeon011 0:9158fe13dc14 519 }
xeon011 0:9158fe13dc14 520 switch(tmp & PHYCFGR_OPMDC_ALLA)
xeon011 0:9158fe13dc14 521 {
xeon011 0:9158fe13dc14 522 case PHYCFGR_OPMDC_100FA:
xeon011 0:9158fe13dc14 523 case PHYCFGR_OPMDC_100F:
xeon011 0:9158fe13dc14 524 case PHYCFGR_OPMDC_10F:
xeon011 0:9158fe13dc14 525 phyconf->duplex = PHY_DUPLEX_FULL;
xeon011 0:9158fe13dc14 526 break;
xeon011 0:9158fe13dc14 527 default:
xeon011 0:9158fe13dc14 528 phyconf->duplex = PHY_DUPLEX_HALF;
xeon011 0:9158fe13dc14 529 break;
xeon011 0:9158fe13dc14 530 }
xeon011 0:9158fe13dc14 531 }
xeon011 0:9158fe13dc14 532
xeon011 0:9158fe13dc14 533 void wizphy_getphystat(wiz_PhyConf* phyconf)
xeon011 0:9158fe13dc14 534 {
xeon011 0:9158fe13dc14 535 uint8_t tmp = getPHYCFGR();
xeon011 0:9158fe13dc14 536 phyconf->duplex = (tmp & PHYCFGR_DPX_FULL) ? PHY_DUPLEX_FULL : PHY_DUPLEX_HALF;
xeon011 0:9158fe13dc14 537 phyconf->speed = (tmp & PHYCFGR_SPD_100) ? PHY_SPEED_100 : PHY_SPEED_10;
xeon011 0:9158fe13dc14 538 }
xeon011 0:9158fe13dc14 539
xeon011 0:9158fe13dc14 540 int8_t wizphy_setphypmode(uint8_t pmode)
xeon011 0:9158fe13dc14 541 {
xeon011 0:9158fe13dc14 542 uint8_t tmp = 0;
xeon011 0:9158fe13dc14 543 tmp = getPHYCFGR();
xeon011 0:9158fe13dc14 544 if((tmp & PHYCFGR_OPMD)== 0) return -1;
xeon011 0:9158fe13dc14 545 tmp &= ~PHYCFGR_OPMDC_ALLA;
xeon011 0:9158fe13dc14 546 if( pmode == PHY_POWER_DOWN)
xeon011 0:9158fe13dc14 547 tmp |= PHYCFGR_OPMDC_PDOWN;
xeon011 0:9158fe13dc14 548 else
xeon011 0:9158fe13dc14 549 tmp |= PHYCFGR_OPMDC_ALLA;
xeon011 0:9158fe13dc14 550 setPHYCFGR(tmp);
xeon011 0:9158fe13dc14 551 wizphy_reset();
xeon011 0:9158fe13dc14 552 tmp = getPHYCFGR();
xeon011 0:9158fe13dc14 553 if( pmode == PHY_POWER_DOWN)
xeon011 0:9158fe13dc14 554 {
xeon011 0:9158fe13dc14 555 if(tmp & PHYCFGR_OPMDC_PDOWN) return 0;
xeon011 0:9158fe13dc14 556 }
xeon011 0:9158fe13dc14 557 else
xeon011 0:9158fe13dc14 558 {
xeon011 0:9158fe13dc14 559 if(tmp & PHYCFGR_OPMDC_ALLA) return 0;
xeon011 0:9158fe13dc14 560 }
xeon011 0:9158fe13dc14 561 return -1;
xeon011 0:9158fe13dc14 562 }
xeon011 0:9158fe13dc14 563 #endif
xeon011 0:9158fe13dc14 564
xeon011 0:9158fe13dc14 565
xeon011 0:9158fe13dc14 566 void wizchip_setnetinfo(wiz_NetInfo* pnetinfo)
xeon011 0:9158fe13dc14 567 {
xeon011 0:9158fe13dc14 568 setSHAR(pnetinfo->mac);
xeon011 0:9158fe13dc14 569 setGAR(pnetinfo->gw);
xeon011 0:9158fe13dc14 570 setSUBR(pnetinfo->sn);
xeon011 0:9158fe13dc14 571 setSIPR(pnetinfo->ip);
xeon011 0:9158fe13dc14 572 _DNS_[0] = pnetinfo->dns[0];
xeon011 0:9158fe13dc14 573 _DNS_[1] = pnetinfo->dns[1];
xeon011 0:9158fe13dc14 574 _DNS_[2] = pnetinfo->dns[2];
xeon011 0:9158fe13dc14 575 _DNS_[3] = pnetinfo->dns[3];
xeon011 0:9158fe13dc14 576 _DHCP_ = pnetinfo->dhcp;
xeon011 0:9158fe13dc14 577 }
xeon011 0:9158fe13dc14 578
xeon011 0:9158fe13dc14 579 void wizchip_getnetinfo(wiz_NetInfo* pnetinfo)
xeon011 0:9158fe13dc14 580 {
xeon011 0:9158fe13dc14 581 getSHAR(pnetinfo->mac);
xeon011 0:9158fe13dc14 582 getGAR(pnetinfo->gw);
xeon011 0:9158fe13dc14 583 getSUBR(pnetinfo->sn);
xeon011 0:9158fe13dc14 584 getSIPR(pnetinfo->ip);
xeon011 0:9158fe13dc14 585 pnetinfo->dns[0]= _DNS_[0];
xeon011 0:9158fe13dc14 586 pnetinfo->dns[1]= _DNS_[1];
xeon011 0:9158fe13dc14 587 pnetinfo->dns[2]= _DNS_[2];
xeon011 0:9158fe13dc14 588 pnetinfo->dns[3]= _DNS_[3];
xeon011 0:9158fe13dc14 589 pnetinfo->dhcp = _DHCP_;
xeon011 0:9158fe13dc14 590 }
xeon011 0:9158fe13dc14 591
xeon011 0:9158fe13dc14 592 int8_t wizchip_setnetmode(netmode_type netmode)
xeon011 0:9158fe13dc14 593 {
xeon011 0:9158fe13dc14 594 uint8_t tmp = 0;
xeon011 0:9158fe13dc14 595 #if _WIZCHIP_ != 5500
xeon011 0:9158fe13dc14 596 if(netmode & ~(NM_WAKEONLAN | NM_PPPOE | NM_PINGBLOCK)) return -1;
xeon011 0:9158fe13dc14 597 #else
xeon011 0:9158fe13dc14 598 if(netmode & ~(NM_WAKEONLAN | NM_PPPOE | NM_PINGBLOCK | NM_FORCEARP)) return -1;
xeon011 0:9158fe13dc14 599 #endif
xeon011 0:9158fe13dc14 600 tmp = getMR();
xeon011 0:9158fe13dc14 601 tmp |= (uint8_t)netmode;
xeon011 0:9158fe13dc14 602 setMR(tmp);
xeon011 0:9158fe13dc14 603 return 0;
xeon011 0:9158fe13dc14 604 }
xeon011 0:9158fe13dc14 605
xeon011 0:9158fe13dc14 606 netmode_type wizchip_getnetmode(void)
xeon011 0:9158fe13dc14 607 {
xeon011 0:9158fe13dc14 608 return (netmode_type) getMR();
xeon011 0:9158fe13dc14 609 }
xeon011 0:9158fe13dc14 610
xeon011 0:9158fe13dc14 611 void wizchip_settimeout(wiz_NetTimeout* nettime)
xeon011 0:9158fe13dc14 612 {
xeon011 0:9158fe13dc14 613 setRCR(nettime->retry_cnt);
xeon011 0:9158fe13dc14 614 setRTR(nettime->time_100us);
xeon011 0:9158fe13dc14 615 }
xeon011 0:9158fe13dc14 616
xeon011 0:9158fe13dc14 617 void wizchip_gettimeout(wiz_NetTimeout* nettime)
xeon011 0:9158fe13dc14 618 {
xeon011 0:9158fe13dc14 619 nettime->retry_cnt = getRCR();
xeon011 0:9158fe13dc14 620 nettime->time_100us = getRTR();
xeon011 0:9158fe13dc14 621 }