Trung Nguyen / Mbed 2 deprecated FINAL_PROJECT_4180

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Dependencies:   mbed

Fork of FINAL_PROJECT_4180 by Gedeon Nyengele

MEM.h@9:48e93bcd1d5c, 2016-04-25 (annotated)

Committer:
nyengele
Date:
Mon Apr 25 01:39:32 2016 +0000
Revision:
9:48e93bcd1d5c
user_id to int done

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nyengele 9:48e93bcd1d5c 1 #ifndef MEM_H
nyengele 9:48e93bcd1d5c 2 #define MEM_H
nyengele 9:48e93bcd1d5c 3
nyengele 9:48e93bcd1d5c 4 #include "mbed.h"
nyengele 9:48e93bcd1d5c 5
nyengele 9:48e93bcd1d5c 6 #define MEM_START_ADDR 0
nyengele 9:48e93bcd1d5c 7 #define MEM_PAGE_OFFSET (1 << 8)
nyengele 9:48e93bcd1d5c 8 #define MEM_SECTOR_OFFSET (1 << 12)
nyengele 9:48e93bcd1d5c 9
nyengele 9:48e93bcd1d5c 10 // Chip Manufacturer Info
nyengele 9:48e93bcd1d5c 11 typedef struct {
nyengele 9:48e93bcd1d5c 12 int manuf_id;
nyengele 9:48e93bcd1d5c 13 int mem_type;
nyengele 9:48e93bcd1d5c 14 int mem_size;
nyengele 9:48e93bcd1d5c 15 } FLASH_MEM_INFO;
nyengele 9:48e93bcd1d5c 16
nyengele 9:48e93bcd1d5c 17 // Supported Commands
nyengele 9:48e93bcd1d5c 18 struct FLASH_MEM_CMD {
nyengele 9:48e93bcd1d5c 19 static const int WREN = 0x06; // Set Write Enable Latch
nyengele 9:48e93bcd1d5c 20 static const int WRDI = 0x04; // Reset Write Enable Latch
nyengele 9:48e93bcd1d5c 21 static const int RDSR = 0x05; // Read Status Register
nyengele 9:48e93bcd1d5c 22 static const int WRSR = 0x01; // Write Status Register
nyengele 9:48e93bcd1d5c 23 static const int READ = 0x03; // Read Data from Memory Array
nyengele 9:48e93bcd1d5c 24 static const int FAST_READ = 0x0B; // Read Data from Memory Array (with dummy cycles)
nyengele 9:48e93bcd1d5c 25 static const int PROGRAM = 0x02; // Program Data Into Memory Array
nyengele 9:48e93bcd1d5c 26 static const int SECTOR_ERASE = 0x20; // Erase 1 4KB Sector in Memory
nyengele 9:48e93bcd1d5c 27 static const int BLOCK_ERASE = 0x52; // Erase 1 64KB Block in Memory
nyengele 9:48e93bcd1d5c 28 static const int CHIP_ERASE = 0x60; // Erase Entire Memory Array
nyengele 9:48e93bcd1d5c 29 static const int RDID = 0x9F; // Read Manufacturer and Product ID
nyengele 9:48e93bcd1d5c 30 };
nyengele 9:48e93bcd1d5c 31
nyengele 9:48e93bcd1d5c 32 // Memory Operations Status
nyengele 9:48e93bcd1d5c 33 enum MEM_STATUS {
nyengele 9:48e93bcd1d5c 34 FAIL = 0,
nyengele 9:48e93bcd1d5c 35 SUCCESS,
nyengele 9:48e93bcd1d5c 36 BUSY,
nyengele 9:48e93bcd1d5c 37 READY,
nyengele 9:48e93bcd1d5c 38 };
nyengele 9:48e93bcd1d5c 39
nyengele 9:48e93bcd1d5c 40
nyengele 9:48e93bcd1d5c 41 class MEM_DEVICE
nyengele 9:48e93bcd1d5c 42 {
nyengele 9:48e93bcd1d5c 43 SPI *dev;
nyengele 9:48e93bcd1d5c 44
nyengele 9:48e93bcd1d5c 45 public:
nyengele 9:48e93bcd1d5c 46 /**
nyengele 9:48e93bcd1d5c 47 * Constructor
nyengele 9:48e93bcd1d5c 48 *
nyengele 9:48e93bcd1d5c 49 * @param mosi MOSI pin for SPI
nyengele 9:48e93bcd1d5c 50 * @param miso MISO pin for SPI
nyengele 9:48e93bcd1d5c 51 * @param sck clock pin for SPI
nyengele 9:48e93bcd1d5c 52 * @param cs Chip Select pin
nyengele 9:48e93bcd1d5c 53 */
nyengele 9:48e93bcd1d5c 54 MEM_DEVICE(PinName mosi, PinName miso, PinName sck, PinName cs);
nyengele 9:48e93bcd1d5c 55
nyengele 9:48e93bcd1d5c 56
nyengele 9:48e93bcd1d5c 57 /**
nyengele 9:48e93bcd1d5c 58 * Destructor
nyengele 9:48e93bcd1d5c 59 */
nyengele 9:48e93bcd1d5c 60 ~MEM_DEVICE();
nyengele 9:48e93bcd1d5c 61
nyengele 9:48e93bcd1d5c 62 /**
nyengele 9:48e93bcd1d5c 63 * Set mode and number of bits to use
nyengele 9:48e93bcd1d5c 64 *
nyengele 9:48e93bcd1d5c 65 * @param databits number data bits
nyengele 9:48e93bcd1d5c 66 * @param mode SPI mode to use (0, 1, 2, 3)
nyengele 9:48e93bcd1d5c 67 */
nyengele 9:48e93bcd1d5c 68 void format(int databits, int mode);
nyengele 9:48e93bcd1d5c 69
nyengele 9:48e93bcd1d5c 70 /**
nyengele 9:48e93bcd1d5c 71 * Read multiple consecutive bytes from memory device
nyengele 9:48e93bcd1d5c 72 *
nyengele 9:48e93bcd1d5c 73 * @param startAddr address where to start reading from
nyengele 9:48e93bcd1d5c 74 * @param numOfBytes number of consecutive bytes to read
nyengele 9:48e93bcd1d5c 75 * @param destBuffer buffer where to copy bytes to
nyengele 9:48e93bcd1d5c 76 * @return status of the read operation (FAIL or SUCCESS)
nyengele 9:48e93bcd1d5c 77 */
nyengele 9:48e93bcd1d5c 78 MEM_STATUS read_bytes(int startAddr, int numOfBytes, char *destBuffer);
nyengele 9:48e93bcd1d5c 79
nyengele 9:48e93bcd1d5c 80 /**
nyengele 9:48e93bcd1d5c 81 * Write multiple consecutive bytes to memory device
nyengele 9:48e93bcd1d5c 82 *
nyengele 9:48e93bcd1d5c 83 * @param startAddr address where to start writing to
nyengele 9:48e93bcd1d5c 84 * @param numOfBytes number of consecutive bytes to write
nyengele 9:48e93bcd1d5c 85 * @param srcBuffer buffer where to write from
nyengele 9:48e93bcd1d5c 86 * @return status of the write operation (FAIL or SUCCESS)
nyengele 9:48e93bcd1d5c 87 */
nyengele 9:48e93bcd1d5c 88 MEM_STATUS write_bytes(int startAddr, int numOfBytes, char *srcBuffer);
nyengele 9:48e93bcd1d5c 89
nyengele 9:48e93bcd1d5c 90 /**
nyengele 9:48e93bcd1d5c 91 * Clears the entire flash memory
nyengele 9:48e93bcd1d5c 92 *
nyengele 9:48e93bcd1d5c 93 * @return status of the clear operation (FAIL or SUCCESS)
nyengele 9:48e93bcd1d5c 94 */
nyengele 9:48e93bcd1d5c 95 MEM_STATUS erase();
nyengele 9:48e93bcd1d5c 96
nyengele 9:48e93bcd1d5c 97 /**
nyengele 9:48e93bcd1d5c 98 * Reads the status of the memory device
nyengele 9:48e93bcd1d5c 99 *
nyengele 9:48e93bcd1d5c 100 * @return status of the operation (FAIL, BUSY, READY)
nyengele 9:48e93bcd1d5c 101 */
nyengele 9:48e93bcd1d5c 102 MEM_STATUS read_status();
nyengele 9:48e93bcd1d5c 103 };
nyengele 9:48e93bcd1d5c 104
nyengele 9:48e93bcd1d5c 105 #endif