MAX30001.h

00001 /*******************************************************************************
00002 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
00003 *
00004 * Permission is hereby granted, free of charge, to any person obtaining a
00005 * copy of this software and associated documentation files (the "Software"),
00006 * to deal in the Software without restriction, including without limitation
00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00008 * and/or sell copies of the Software, and to permit persons to whom the
00009 * Software is furnished to do so, subject to the following conditions:
00010 *
00011 * The above copyright notice and this permission notice shall be included
00012 * in all copies or substantial portions of the Software.
00013 *
00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00020 * OTHER DEALINGS IN THE SOFTWARE.
00021 *
00022 * Except as contained in this notice, the name of Maxim Integrated
00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated
00024 * Products, Inc. Branding Policy.
00025 *
00026 * The mere transfer of this software does not imply any licenses
00027 * of trade secrets, proprietary technology, copyrights, patents,
00028 * trademarks, maskwork rights, or any other form of intellectual
00029 * property whatsoever. Maxim Integrated Products, Inc. retains all
00030 * ownership rights.
00031 *******************************************************************************/
00032 /*
00033  * max30001.h
00034  *
00035  *  Created on: Oct 9, 2015
00036  *      Author: faisal.tariq
00037  */
00038 
00039 #ifndef MAX30001_H_
00040 #define MAX30001_H_
00041 
00042 #include "mbed.h"
00043 #include "USBSerial.h"
00044 
00045 #define mbed_COMPLIANT // Uncomment to Use timer for MAX30001 FCLK (for mbed)
00046                        // Comment to use the RTC clock
00047 
00048 
00049 
00050 #define ASYNC_SPI_BUFFER_SIZE (32 * 3) // Maximimum buffer size for async byte transfers
00051 
00052 // Defines for data callbacks
00053 #define MAX30001_DATA_ECG        0x30
00054 #define MAX30001_DATA_PACE       0x31
00055 #define MAX30001_DATA_RTOR       0x32
00056 #define MAX30001_DATA_BIOZ       0x33
00057 #define MAX30001_DATA_LEADOFF_DC 0x34
00058 #define MAX30001_DATA_LEADOFF_AC 0x35
00059 #define MAX30001_DATA_BCGMON     0x36
00060 #define MAX30001_DATA_ACLEADON   0x37
00061 
00062 #define MAX30001_SPI_MASTER_PORT 0
00063 #define MAX30001_SPI_SS_INDEX    0
00064 
00065 #define MAX30001_INT_PORT_B      3
00066 #define MAX30001_INT_PIN_B       6
00067 
00068 #define MAX30001_INT_PORT_2B     4
00069 #define MAX30001_INT_PIN_2B      5
00070 
00071 #define MAX30001_INT_PORT_FCLK   1
00072 #define MAX30001_INT_PIN_FCLK    7
00073 
00074 #define MAX30001_FUNC_SEL_TMR    2 // 0=FW Control, 1= Pulse Train, 2=Timer
00075 
00076 #define MAX30001_INDEX    3
00077 #define MAX30001_POLARITY 0
00078 #define MAX30001_PERIOD   30518
00079 #define MAX30001_CYCLE    50
00080 
00081 #define MAX30001_IOMUX_IO_ENABLE 1
00082 
00083 #define MAX30001_SPI_PORT            0
00084 #define MAX30001_CS_PIN              0
00085 #define MAX30001_CS_POLARITY         0
00086 #define MAX30001_CS_ACTIVITY_DELAY   0
00087 #define MAX30001_CS_INACTIVITY_DELAY 0
00088 #define MAX30001_CLK_HI              1
00089 #define MAX30001_CLK_LOW             1
00090 #define MAX30001_ALT_CLK             0
00091 #define MAX30001_CLK_POLARITY        0
00092 #define MAX30001_CLK_PHASE           0
00093 #define MAX30001_WRITE               1
00094 #define MAX30001_READ                0
00095 
00096 #define MAX30001_INT_PORT_B  3
00097 #define MAX30001INT_PIN_B    6
00098 
00099 void MAX30001_AllowInterrupts(int state);
00100 
00101 /**
00102 * Maxim Integrated MAX30001 ECG/BIOZ chip
00103 */
00104 class MAX30001 {
00105 
00106 public:
00107   typedef enum { // MAX30001 Register addresses
00108     STATUS     = 0x01,
00109     EN_INT     = 0x02,
00110     EN_INT2    = 0x03,
00111     MNGR_INT   = 0x04,
00112     MNGR_DYN   = 0x05,
00113     SW_RST     = 0x08,
00114     SYNCH      = 0x09,
00115     FIFO_RST   = 0x0A,
00116     INFO       = 0x0F,
00117     CNFG_GEN   = 0x10,
00118     CNFG_CAL   = 0x12,
00119     CNFG_EMUX  = 0x14,
00120     CNFG_ECG   = 0x15,
00121     CNFG_BMUX  = 0x17,
00122     CNFG_BIOZ  = 0x18,
00123     CNFG_PACE  = 0x1A,
00124     CNFG_RTOR1 = 0x1D,
00125     CNFG_RTOR2 = 0x1E,
00126 
00127     // Data locations
00128     ECG_FIFO_BURST = 0x20,
00129     ECG_FIFO       = 0x21,
00130     FIFO_BURST     = 0x22,
00131     BIOZ_FIFO      = 0x23,
00132     RTOR           = 0x25,
00133 
00134     PACE0_FIFO_BURST = 0x30,
00135     PACE0_A          = 0x31,
00136     PACE0_B          = 0x32,
00137     PACE0_C          = 0x33,
00138 
00139     PACE1_FIFO_BURST = 0x34,
00140     PACE1_A          = 0x35,
00141     PACE1_B          = 0x36,
00142     PACE1_C          = 0x37,
00143 
00144     PACE2_FIFO_BURST = 0x38,
00145     PACE2_A          = 0x39,
00146     PACE2_B          = 0x3A,
00147     PACE2_C          = 0x3B,
00148 
00149     PACE3_FIFO_BURST = 0x3C,
00150     PACE3_A          = 0x3D,
00151     PACE3_B          = 0x3E,
00152     PACE3_C          = 0x3F,
00153 
00154     PACE4_FIFO_BURST = 0x40,
00155     PACE4_A          = 0x41,
00156     PACE4_B          = 0x42,
00157     PACE4_C          = 0x43,
00158 
00159     PACE5_FIFO_BURST = 0x44,
00160     PACE5_A          = 0x45,
00161     PACE5_B          = 0x46,
00162     PACE5_C          = 0x47,
00163 
00164   } MAX30001_REG_map_t;
00165 
00166   /**
00167    * @brief STATUS (0x01)
00168    */
00169   union max30001_status_reg {
00170     uint32_t all;
00171 
00172     struct {
00173       uint32_t loff_nl : 1;
00174       uint32_t loff_nh : 1;
00175       uint32_t loff_pl : 1;
00176       uint32_t loff_ph : 1;
00177 
00178       uint32_t bcgmn     : 1;
00179       uint32_t bcgmp     : 1;
00180       uint32_t reserved1 : 1;
00181       uint32_t reserved2 : 1;
00182 
00183       uint32_t pllint : 1;
00184       uint32_t samp   : 1;
00185       uint32_t rrint  : 1;
00186       uint32_t lonint : 1;
00187 
00188       uint32_t pedge  : 1;
00189       uint32_t povf   : 1;
00190       uint32_t pint   : 1;
00191       uint32_t bcgmon : 1;
00192 
00193       uint32_t bundr : 1;
00194       uint32_t bover : 1;
00195       uint32_t bovf  : 1;
00196       uint32_t bint  : 1;
00197 
00198       uint32_t dcloffint : 1;
00199       uint32_t fstint    : 1;
00200       uint32_t eovf      : 1;
00201       uint32_t eint      : 1;
00202 
00203       uint32_t reserved : 8;
00204 
00205     } bit;
00206 
00207   } max30001_status;
00208 
00209 
00210   /**
00211    * @brief EN_INT (0x02)
00212    */
00213 
00214   union max30001_en_int_reg {
00215     uint32_t all;
00216 
00217     struct {
00218       uint32_t intb_type : 2;
00219       uint32_t reserved1 : 1;
00220       uint32_t reserved2 : 1;
00221 
00222       uint32_t reserved3 : 1;
00223       uint32_t reserved4 : 1;
00224       uint32_t reserved5 : 1;
00225       uint32_t reserved6 : 1;
00226 
00227       uint32_t en_pllint : 1;
00228       uint32_t en_samp   : 1;
00229       uint32_t en_rrint  : 1;
00230       uint32_t en_lonint : 1;
00231 
00232       uint32_t en_pedge  : 1;
00233       uint32_t en_povf   : 1;
00234       uint32_t en_pint   : 1;
00235       uint32_t en_bcgmon : 1;
00236 
00237       uint32_t en_bundr : 1;
00238       uint32_t en_bover : 1;
00239       uint32_t en_bovf  : 1;
00240       uint32_t en_bint  : 1;
00241 
00242       uint32_t en_dcloffint : 1;
00243       uint32_t en_fstint    : 1;
00244       uint32_t en_eovf      : 1;
00245       uint32_t en_eint      : 1;
00246 
00247       uint32_t reserved : 8;
00248 
00249     } bit;
00250 
00251   } max30001_en_int;
00252 
00253 
00254   /**
00255    * @brief EN_INT2 (0x03)
00256    */
00257   union max30001_en_int2_reg {
00258     uint32_t all;
00259 
00260     struct {
00261       uint32_t intb_type : 2;
00262       uint32_t reserved1 : 1;
00263       uint32_t reserved2 : 1;
00264 
00265       uint32_t reserved3 : 1;
00266       uint32_t reserved4 : 1;
00267       uint32_t reserved5 : 1;
00268       uint32_t reserved6 : 1;
00269 
00270       uint32_t en_pllint : 1;
00271       uint32_t en_samp   : 1;
00272       uint32_t en_rrint  : 1;
00273       uint32_t en_lonint : 1;
00274 
00275       uint32_t en_pedge  : 1;
00276       uint32_t en_povf   : 1;
00277       uint32_t en_pint   : 1;
00278       uint32_t en_bcgmon : 1;
00279 
00280       uint32_t en_bundr  : 1;
00281       uint32_t en_bover  : 1;
00282       uint32_t en_bovf   : 1;
00283       uint32_t en_bint   : 1;
00284 
00285       uint32_t en_dcloffint : 1;
00286       uint32_t en_fstint    : 1;
00287       uint32_t en_eovf      : 1;
00288       uint32_t en_eint      : 1;
00289 
00290       uint32_t reserved : 8;
00291 
00292     } bit;
00293 
00294   } max30001_en_int2;
00295 
00296   /**
00297    * @brief MNGR_INT (0x04)
00298    */
00299   union max30001_mngr_int_reg {
00300     uint32_t all;
00301 
00302     struct {
00303       uint32_t samp_it   : 2;
00304       uint32_t clr_samp  : 1;
00305       uint32_t clr_pedge : 1;
00306       uint32_t clr_rrint : 2;
00307       uint32_t clr_fast  : 1;
00308       uint32_t reserved1 : 1;
00309       uint32_t reserved2 : 4;
00310       uint32_t reserved3 : 4;
00311 
00312       uint32_t b_fit     : 3;
00313       uint32_t e_fit     : 5;
00314 
00315       uint32_t reserved : 8;
00316 
00317     } bit;
00318 
00319   } max30001_mngr_int;
00320 
00321    /**
00322    * @brief MNGR_DYN (0x05)
00323    */
00324   union max30001_mngr_dyn_reg {
00325     uint32_t all;
00326 
00327     struct {
00328       uint32_t bloff_lo_it : 8;
00329       uint32_t bloff_hi_it : 8;
00330       uint32_t fast_th     : 6;
00331       uint32_t fast        : 2;
00332       uint32_t reserved    : 8;
00333     } bit;
00334 
00335   } max30001_mngr_dyn;
00336 
00337   // 0x08
00338   // uint32_t max30001_sw_rst;
00339 
00340   // 0x09
00341   // uint32_t max30001_synch;
00342 
00343   // 0x0A
00344   // uint32_t max30001_fifo_rst;
00345 
00346 
00347    /**
00348    * @brief INFO (0x0F)
00349    */
00350   union max30001_info_reg {
00351     uint32_t all;
00352     struct {
00353       uint32_t serial    : 12;
00354       uint32_t part_id   : 2;
00355       uint32_t sample    : 1;
00356       uint32_t reserved1 : 1;
00357       uint32_t rev_id    : 4;
00358       uint32_t pattern   : 4;
00359       uint32_t reserved  : 8;
00360     } bit;
00361 
00362   } max30001_info;
00363 
00364    /**
00365    * @brief CNFG_GEN (0x10)
00366    */
00367   union max30001_cnfg_gen_reg {
00368     uint32_t all;
00369     struct {
00370       uint32_t rbiasn     : 1;
00371       uint32_t rbiasp     : 1;
00372       uint32_t rbiasv     : 2;
00373       uint32_t en_rbias   : 2;
00374       uint32_t vth        : 2;
00375       uint32_t imag       : 3;
00376       uint32_t ipol       : 1;
00377       uint32_t en_dcloff  : 2;
00378       uint32_t en_bloff   : 2;
00379       uint32_t reserved1  : 1;
00380       uint32_t en_pace    : 1;
00381       uint32_t en_bioz    : 1;
00382       uint32_t en_ecg     : 1;
00383       uint32_t fmstr      : 2;
00384       uint32_t en_ulp_lon : 2;
00385       uint32_t reserved : 8;
00386     } bit;
00387 
00388   } max30001_cnfg_gen;
00389 
00390 
00391    /**
00392    * @brief CNFG_CAL (0x12)
00393    */
00394   union max30001_cnfg_cal_reg {
00395     uint32_t all;
00396     struct {
00397       uint32_t thigh     : 11;
00398       uint32_t fifty     : 1;
00399       uint32_t fcal      : 3;
00400       uint32_t reserved1 : 5;
00401       uint32_t vmag      : 1;
00402       uint32_t vmode     : 1;
00403       uint32_t en_vcal   : 1;
00404       uint32_t reserved2 : 1;
00405       uint32_t reserved  : 8;
00406     } bit;
00407 
00408   } max30001_cnfg_cal;
00409 
00410    /**
00411    * @brief CNFG_EMUX  (0x14)
00412    */
00413   union max30001_cnfg_emux_reg {
00414     uint32_t all;
00415     struct {
00416       uint32_t reserved1 : 16;
00417       uint32_t caln_sel  : 2;
00418       uint32_t calp_sel  : 2;
00419       uint32_t openn     : 1;
00420       uint32_t openp     : 1;
00421       uint32_t reserved2 : 1;
00422       uint32_t pol       : 1;
00423       uint32_t reserved : 8;
00424     } bit;
00425 
00426   } max30001_cnfg_emux;
00427 
00428 
00429    /**
00430    * @brief CNFG_ECG   (0x15)
00431    */
00432   union max30001_cnfg_ecg_reg {
00433     uint32_t all;
00434     struct {
00435       uint32_t reserved1 : 12;
00436       uint32_t dlpf      : 2;
00437       uint32_t dhpf      : 1;
00438       uint32_t reserved2 : 1;
00439       uint32_t gain      : 2;
00440       uint32_t reserved3 : 4;
00441       uint32_t rate      : 2;
00442 
00443       uint32_t reserved  : 8;
00444     } bit;
00445 
00446   } max30001_cnfg_ecg;
00447 
00448    /**
00449    * @brief CNFG_BMUX   (0x17)
00450    */
00451   union max30001_cnfg_bmux_reg {
00452     uint32_t all;
00453     struct {
00454       uint32_t fbist     : 2;
00455       uint32_t reserved1 : 2;
00456       uint32_t rmod      : 3;
00457       uint32_t reserved2 : 1;
00458       uint32_t rnom      : 3;
00459       uint32_t en_bist   : 1;
00460       uint32_t cg_mode   : 2;
00461       uint32_t reserved3 : 2;
00462       uint32_t caln_sel  : 2;
00463       uint32_t calp_sel  : 2;
00464       uint32_t openn     : 1;
00465       uint32_t openp     : 1;
00466       uint32_t reserved4 : 2;
00467       uint32_t reserved : 8;
00468     } bit;
00469 
00470   } max30001_cnfg_bmux;
00471 
00472    /**
00473    * @brief CNFG_BIOZ   (0x18)
00474    */
00475   union max30001_bioz_reg {
00476     uint32_t all;
00477     struct {
00478       uint32_t phoff     : 4;
00479       uint32_t cgmag     : 3;
00480       uint32_t cgmon     : 1;
00481       uint32_t fcgen     : 4;
00482       uint32_t dlpf      : 2;
00483       uint32_t dhpf      : 2;
00484       uint32_t gain      : 2;
00485       uint32_t inapow_mode : 1;
00486       uint32_t ext_rbias : 1;
00487       uint32_t ahpf      : 3;
00488       uint32_t rate      : 1;
00489       uint32_t reserved : 8;
00490     } bit;
00491 
00492   } max30001_cnfg_bioz;
00493 
00494 
00495    /**
00496    * @brief CNFG_PACE   (0x1A)
00497    */
00498   union max30001_cnfg_pace_reg {
00499     uint32_t all;
00500 
00501     struct {
00502       uint32_t dacn        : 4;
00503       uint32_t dacp        : 4;
00504       uint32_t reserved1   : 4;
00505       uint32_t aout        : 2;
00506       uint32_t aout_lbw    : 1;
00507       uint32_t reserved2   : 1;
00508       uint32_t gain        : 3;
00509       uint32_t gn_diff_off : 1;
00510       uint32_t reserved3   : 3;
00511       uint32_t pol         : 1;
00512       uint32_t reserved    : 8;
00513     } bit;
00514 
00515   } max30001_cnfg_pace;
00516 
00517    /**
00518    * @brief CNFG_RTOR1   (0x1D)
00519    */
00520   union max30001_cnfg_rtor1_reg {
00521     uint32_t all;
00522     struct {
00523       uint32_t reserved1 : 8;
00524       uint32_t ptsf      : 4;
00525       uint32_t pavg      : 2;
00526       uint32_t reserved2 : 1;
00527       uint32_t en_rtor   : 1;
00528       uint32_t gain      : 4;
00529       uint32_t wndw      : 4;
00530       uint32_t reserved : 8;
00531     } bit;
00532 
00533   } max30001_cnfg_rtor1;
00534 
00535    /**
00536    * @brief CNFG_RTOR2 (0x1E)
00537    */
00538   union max30001_cnfg_rtor2_reg {
00539     uint32_t all;
00540     struct {
00541       uint32_t reserved1 : 8;
00542       uint32_t rhsf      : 3;
00543       uint32_t reserved2 : 1;
00544       uint32_t ravg      : 2;
00545       uint32_t reserved3 : 2;
00546       uint32_t hoff      : 6;
00547       uint32_t reserved4 : 2;
00548       uint32_t reserved : 8;
00549     } bit;
00550 
00551   } max30001_cnfg_rtor2;
00552 
00553   /*********************************************************************************/
00554 
00555   typedef enum {
00556     MAX30001_NO_INT = 0, // No interrupt
00557     MAX30001_INT_B  = 1,  // INTB selected for interrupt
00558     MAX30001_INT_2B = 2  // INT2B selected for interrupt
00559   } max30001_intrpt_Location_t;
00560 
00561   typedef enum {
00562     MAX30001_INT_DISABLED = 0b00,
00563     MAX30001_INT_CMOS     = 0b01,
00564     MAX30001_INT_ODN      = 0b10,
00565     MAX30001_INT_ODNR     = 0b11
00566   } max30001_intrpt_type_t;
00567 
00568   typedef enum {          // Input Polarity selection
00569     MAX30001_NON_INV = 0, // Non-Inverted
00570     MAX30001_INV     = 1      // Inverted
00571   } max30001_emux_pol;
00572 
00573   typedef enum {              // OPENP and OPENN setting
00574     MAX30001_ECG_CON_AFE = 0, // ECGx is connected to AFE channel
00575     MAX30001_ECG_ISO_AFE = 1  // ECGx is isolated from AFE channel
00576   } max30001_emux_openx;
00577 
00578   typedef enum {                // EMUX_CALP_SEL & EMUX_CALN_SEL
00579     MAX30001_NO_CAL_SIG = 0b00, // No calibration signal is applied
00580     MAX30001_INPT_VMID  = 0b01,  // Input is connected to VMID
00581     MAX30001_INPT_VCALP = 0b10, // Input is connected to VCALP
00582     MAX30001_INPT_VCALN = 0b11  // Input is connected to VCALN
00583   } max30001_emux_calx_sel;
00584 
00585   typedef enum {                     // EN_ECG, EN_BIOZ, EN_PACE
00586     MAX30001_CHANNEL_DISABLED = 0b0, //
00587     MAX30001_CHANNEL_ENABLED = 0b1
00588   } max30001_en_feature;
00589 
00590   /*********************************************************************************/
00591   // Data
00592   uint32_t max30001_ECG_FIFO_buffer[32]; // (303 for internal test)
00593   uint32_t max30001_BIOZ_FIFO_buffer[8]; // (303 for internal test)
00594 
00595   uint32_t max30001_PACE[18]; // Pace Data 0-5
00596 
00597   uint32_t max30001_RtoR_data; // This holds the RtoR data
00598 
00599   uint32_t max30001_DCLeadOff; // This holds the LeadOff data, Last 4 bits give
00600                                // the status, BIT3=LOFF_PH, BIT2=LOFF_PL,
00601                                // BIT1=LOFF_NH, BIT0=LOFF_NL
00602                                // 8th and 9th bits tell Lead off is due to ECG or BIOZ.
00603                                // 0b01 = ECG Lead Off and 0b10 = BIOZ Lead off
00604 
00605   uint32_t max30001_ACLeadOff; // This gives the state of the BIOZ AC Lead Off
00606                                // state.  BIT 1 = BOVER,   BIT 0 = BUNDR
00607 
00608   uint32_t max30001_bcgmon; // This holds the BCGMON data, BIT 1 = BCGMP, BIT0 =
00609                             // BCGMN
00610 
00611   uint32_t max30001_LeadOn; // This holds the LeadOn data, BIT1 = BIOZ Lead ON,
00612                             // BIT0 = ECG Lead ON, BIT8= Lead On Status Bit
00613 
00614   uint32_t max30001_timeout; // If the PLL does not respond, timeout and get out.
00615 
00616   typedef struct { // Creating a structure for BLE data
00617     int16_t R2R;
00618     int16_t fmstr;
00619   } max30001_t;
00620 
00621   max30001_t hspValMax30001; // R2R, FMSTR
00622 
00623   //jjj 14MAR17
00624   //added DigitalOut so we can use any pin for cs
00625   //jjj
00626   MAX30001(SPI *spi, DigitalOut *cs);
00627 
00628 
00629   /**
00630   * @brief Constructor that accepts pin names for the SPI interface
00631   * @param mosi master out slave in pin name
00632   * @param miso master in slave out pin name
00633   * @param sclk serial clock pin name
00634   * @param cs chip select pin name
00635   */
00636   MAX30001(PinName mosi, PinName miso, PinName sclk, PinName cs);
00637 
00638   /**
00639    * MAX30001 destructor
00640    */
00641   ~MAX30001(void);
00642 
00643   /**
00644    * @brief This function sets up the Resistive Bias mode and also selects the master clock frequency.
00645    * @brief Uses Register: CNFG_GEN-0x10
00646    * @param En_rbias: Enable and Select Resitive Lead Bias Mode
00647    * @param Rbiasv: Resistive Bias Mode Value Selection
00648    * @param Rbiasp: Enables Resistive Bias on Positive Input
00649    * @param Rbiasn: Enables Resistive Bias on Negative Input
00650    * @param Fmstr: Selects Master Clock Frequency
00651    * @returns 0-if no error.  A non-zero value indicates an error.
00652    *
00653   */
00654   int max30001_Rbias_FMSTR_Init(uint8_t En_rbias, uint8_t Rbiasv,
00655                                 uint8_t Rbiasp, uint8_t Rbiasn, uint8_t Fmstr);
00656 
00657   /**
00658    * @brief This function uses sets up the calibration signal internally.  If it is desired to use the internal signal, then
00659    * @brief this function must be called and the registers set, prior to setting the CALP_SEL and CALN_SEL in the ECG_InitStart
00660    * @brief and BIOZ_InitStart functions.
00661    * @brief Uses Register: CNFG_CAL-0x12
00662    * @param En_Vcal: Calibration Source (VCALP and VCALN) Enable
00663    * @param Vmode:   Calibration Source Mode Selection
00664    * @param Vmag:    Calibration Source Magnitude Selection (VMAG)
00665    * @param Fcal:    Calibration Source Frequency Selection (FCAL)
00666    * @param Thigh:   Calibration Source Time High Selection
00667    * @param Fifty:   Calibration Source Duty Cycle Mode Selection
00668    * @returns 0-if no error.  A non-zero value indicates an error.
00669    *
00670    */
00671   int max30001_CAL_InitStart(uint8_t En_Vcal, uint8_t Vmode, uint8_t Vmag,
00672                              uint8_t Fcal, uint16_t Thigh, uint8_t Fifty);
00673 
00674   /**
00675    * @brief This function disables the VCAL signal
00676    * @returns 0-if no error.  A non-zero value indicates an error.
00677    */
00678   int max30001_CAL_Stop(void);
00679 
00680   /**
00681    * @brief This function handles the assignment of the two interrupt pins (INTB & INT2B) with various
00682    * @brief functions/behaviors  of the MAX30001.  Also, each pin can be configured for different drive capability.
00683    * @brief Uses Registers: EN_INT-0x02 and EN_INT2-0x03.
00684    * @param max30001_intrpt_Locatio_t  <argument>:  All the arguments with the aforementioned enumeration essentially
00685    *        can be configured to generate an interrupt on either INTB or INT2B or NONE.
00686    * @param max30001_intrpt_type_t  intb_Type:  INTB Port Type (EN_INT Selections).
00687    * @param max30001_intrpt_type _t int2b_Type:   INT2B Port Type (EN_INT2 Selections)
00688    * @returns 0-if no error.  A non-zero value indicates an error.
00689    *
00690    */
00691      int max30001_INT_assignment(max30001_intrpt_Location_t en_enint_loc,     max30001_intrpt_Location_t en_eovf_loc,  max30001_intrpt_Location_t en_fstint_loc,
00692                          max30001_intrpt_Location_t en_dcloffint_loc, max30001_intrpt_Location_t en_bint_loc,  max30001_intrpt_Location_t en_bovf_loc,
00693                          max30001_intrpt_Location_t en_bover_loc,     max30001_intrpt_Location_t en_bundr_loc, max30001_intrpt_Location_t en_bcgmon_loc,
00694                          max30001_intrpt_Location_t en_pint_loc,      max30001_intrpt_Location_t en_povf_loc,  max30001_intrpt_Location_t en_pedge_loc,
00695                          max30001_intrpt_Location_t en_lonint_loc,    max30001_intrpt_Location_t en_rrint_loc, max30001_intrpt_Location_t en_samp_loc,
00696                          max30001_intrpt_type_t  intb_Type,           max30001_intrpt_type_t int2b_Type);
00697 
00698 
00699 
00700   /**
00701    * @brief For MAX30001/3 ONLY
00702    * @brief This function sets up the MAX30001 for the ECG measurements.
00703    * @brief Registers used:  CNFG_EMUX, CNFG_GEN, MNGR_INT, CNFG_ECG.
00704    * @param En_ecg: ECG Channel Enable <CNFG_GEN register bits>
00705    * @param Openp: Open the ECGN Input Switch (most often used for testing and calibration studies) <CNFG_EMUX register bits>
00706    * @param Openn: Open the ECGN Input Switch (most often used for testing and calibration studies) <CNFG_EMUX register bits>
00707    * @param Calp_sel: ECGP Calibration Selection <CNFG_EMUX register bits>
00708    * @param Caln_sel: ECGN Calibration Selection <CNFG_EMUX register bits>
00709    * @param E_fit: ECG FIFO Interrupt Threshold (issues EINT based on number of unread FIFO records) <CNFG_GEN register bits>
00710    * @param Clr_rrint: RTOR R Detect Interrupt (RRINT) Clear Behavior <CNFG_GEN register bits>
00711    * @param Rate: ECG Data Rate
00712    * @param Gain: ECG Channel Gain Setting
00713    * @param Dhpf: ECG Channel Digital High Pass Filter Cutoff Frequency
00714    * @param Dlpf:  ECG Channel Digital Low Pass Filter Cutoff Frequency
00715    * @returns 0-if no error.  A non-zero value indicates an error.
00716    *
00717    */
00718   int max30001_ECG_InitStart(uint8_t En_ecg, uint8_t Openp, uint8_t Openn,
00719                              uint8_t Pol, uint8_t Calp_sel, uint8_t Caln_sel,
00720                              uint8_t E_fit, uint8_t Rate, uint8_t Gain,
00721                              uint8_t Dhpf, uint8_t Dlpf);
00722 
00723   /**
00724    * @brief For MAX30001/3 ONLY
00725    * @brief This function enables the Fast mode feature of the ECG.
00726    * @brief Registers used: MNGR_INT-0x04, MNGR_DYN-0x05
00727    * @param Clr_Fast: FAST MODE Interrupt Clear Behavior <MNGR_INT Register>
00728    * @param Fast: ECG Channel Fast Recovery Mode Selection (ECG High Pass Filter Bypass) <MNGR_DYN Register>
00729    * @param Fast_Th: Automatic Fast Recovery Threshold
00730    * @returns 0-if no error.  A non-zero value indicates an error.
00731    *
00732    */
00733   int max30001_ECGFast_Init(uint8_t Clr_Fast, uint8_t Fast, uint8_t Fast_Th);
00734 
00735   /**
00736   * @brief For MAX30001/3 ONLY
00737   * @brief This function disables the ECG.
00738   * @brief Uses Register CNFG_GEN-0x10.
00739   * @returns 0-if no error.  A non-zero value indicates an error.
00740   *
00741   */
00742   int max30001_Stop_ECG(void);
00743 
00744   /**
00745    *  @brief For MAX30001 ONLY
00746    *  @brief This function sets up the MAX30001 for pace signal detection.
00747    *  @brief If both PACE and BIOZ are turned ON, then make sure Fcgen is set for 80K or 40K in the
00748    *  @brief max30001_BIOZ_InitStart() function.  However, if Only PACE is on but BIOZ off, then Fcgen can be set
00749    *  @brief for 80K only, in the max30001_BIOZ_InitStart() function
00750    *  @brief Registers used: MNGR_INT-0x04, CNFG_GEN-0x37, CNFG_PACE-0x1A.
00751    *  @param En_pace : PACE Channel Enable <CNFG_GEN Register>
00752    *  @param Clr_pedge : PACE Edge Detect Interrupt (PEDGE) Clear Behavior <MNGR_INT Register>
00753    *  @param Pol: PACE Input Polarity Selection <CNFG_PACE Register>
00754    *  @param Gn_diff_off: PACE Differentiator Mode <CNFG_PACE Register>
00755    *  @param Gain: PACE Channel Gain Selection <CNFG_PACE Register>
00756    *  @param Aout_lbw:  PACE Analog Output Buffer Bandwidth Mode <CNFG_PACE Register>
00757    *  @param Aout: PACE Single Ended Analog Output Buffer Signal Monitoring Selection <CNFG_PACE Register>
00758    *  @param Dacp (4bits): PACE Detector Positive Comparator Threshold <CNFG_PACE Register>
00759    *  @param Dacn(4bits): PACE Detector Negative Comparator Threshold <CNFG_PACE Register>
00760    *  @returns 0-if no error.  A non-zero value indicates an error <CNFG_PACE Register>
00761    *
00762    */
00763   int max30001_PACE_InitStart(uint8_t En_pace, uint8_t Clr_pedge, uint8_t Pol,
00764                               uint8_t Gn_diff_off, uint8_t Gain,
00765                               uint8_t Aout_lbw, uint8_t Aout, uint8_t Dacp,
00766                               uint8_t Dacn);
00767 
00768   /**
00769    *@brief For MAX30001 ONLY
00770    *@param This function disables the PACE.  Uses Register CNFG_GEN-0x10.
00771    *@returns 0-if no error.  A non-zero value indicates an error.
00772    *
00773    */
00774   int max30001_Stop_PACE(void);
00775 
00776   /**
00777    * @brief For MAX30001/2 ONLY
00778    * @brief This function sets up the MAX30001 for BIOZ measurement.
00779    * @brief Registers used: MNGR_INT-0x04, CNFG_GEN-0X10, CNFG_BMUX-0x17,CNFG_BIOZ-0x18.
00780    * @param En_bioz: BIOZ Channel Enable <CNFG_GEN Register>
00781    * @param Openp: Open the BIP Input Switch <CNFG_BMUX Register>
00782    * @param Openn: Open the BIN Input Switch <CNFG_BMUX Register>
00783    * @param Calp_sel: BIP Calibration Selection <CNFG_BMUX Register>
00784    * @param Caln_sel: BIN Calibration Selection <CNFG_BMUX Register>
00785    * @param CG_mode:  BIOZ Current Generator Mode Selection <CNFG_BMUX Register>
00786    * @param B_fit:  BIOZ FIFO Interrupt Threshold (issues BINT based on number of unread FIFO records) <MNGR_INT Register>
00787    * @param Rate: BIOZ Data Rate <CNFG_BIOZ Register>
00788    * @param Ahpf: BIOZ/PACE Channel Analog High Pass Filter Cutoff Frequency and Bypass <CNFG_BIOZ Register>
00789    * @param Ext_rbias:  External Resistor Bias Enable <CNFG_BIOZ Register>
00790    * @param Gain: BIOZ Channel Gain Setting <CNFG_BIOZ Register>
00791    * @param Dhpf: BIOZ Channel Digital High Pass Filter Cutoff Frequency <CNFG_BIOZ Register>
00792    * @param Dlpf:  BIOZ Channel Digital Low Pass Filter Cutoff Frequency <CNFG_BIOZ Register>
00793    * @param Fcgen:  BIOZ Current Generator Modulation Frequency <CNFG_BIOZ Register>
00794    * @param Cgmon:  BIOZ Current Generator Monitor <CNFG_BIOZ Register>
00795    * @param Cgmag:  BIOZ Current Generator Magnitude <CNFG_BIOZ Register>
00796    * @param Phoff: BIOZ Current Generator Modulation Phase Offset <CNFG_BIOZ Register>
00797    * @param Inapow_mode: BIOZ Channel Instrumentation Amplifier (INA) Power Mode <CNFG_BIOZ Register>
00798    * @returns 0-if no error.  A non-zero value indicates an error.
00799    *
00800    */
00801   int max30001_BIOZ_InitStart(uint8_t En_bioz, uint8_t Openp, uint8_t Openn,
00802                               uint8_t Calp_sel, uint8_t Caln_sel,
00803                               uint8_t CG_mode,
00804                               /* uint8_t En_bioz,*/ uint8_t B_fit, uint8_t Rate,
00805                               uint8_t Ahpf, uint8_t Ext_rbias, uint8_t Gain,
00806                               uint8_t Dhpf, uint8_t Dlpf, uint8_t Fcgen,
00807                               uint8_t Cgmon, uint8_t Cgmag, uint8_t Phoff, uint8_t Inapow_mode);
00808 
00809   /**
00810    * @brief For MAX30001/2 ONLY
00811    * @brief This function disables the BIOZ.  Uses Register CNFG_GEN-0x10.
00812    * @returns 0-if no error.  A non-zero value indicates an error.
00813        * @returns 0-if no error.  A non-zero value indicates an error.
00814    *
00815    */
00816   int max30001_Stop_BIOZ(void);
00817 
00818   /**
00819    * @brief For MAX30001/2 ONLY
00820    * @brief BIOZ modulated Resistance Built-in-Self-Test, Registers used: CNFG_BMUX-0x17
00821    * @param En_bist: Enable Modulated Resistance Built-in-Self-test <CNFG_BMUX Register>
00822    * @param Rnom: BIOZ RMOD BIST Nominal Resistance Selection <CNFG_BMUX Register>
00823    * @param Rmod: BIOZ RMOD BIST Modulated Resistance Selection <CNFG_BMUX Register>
00824    * @param Fbist: BIOZ RMOD BIST Frequency Selection <CNFG_BMUX Register>
00825    * @returns 0-if no error.  A non-zero value indicates an error.
00826    *
00827    */
00828   int max30001_BIOZ_InitBist(uint8_t En_bist, uint8_t Rnom, uint8_t Rmod,
00829                              uint8_t Fbist);
00830 
00831   /**
00832    * @brief For MAX30001/3/4 ONLY
00833    * @brief Sets up the device for RtoR measurement
00834    * @param EN_rtor: ECG RTOR Detection Enable <RTOR1 Register>
00835    * @param Wndw: R to R Window Averaging (Window Width = RTOR_WNDW[3:0]*8mS) <RTOR1 Register>
00836    * @param Gain: R to R Gain (where Gain = 2^RTOR_GAIN[3:0], plus an auto-scale option) <RTOR1 Register>
00837    * @param Pavg: R to R Peak Averaging Weight Factor <RTOR1 Register>
00838    * @param Ptsf: R to R Peak Threshold Scaling Factor <RTOR1 Register>
00839    * @param Hoff: R to R minimum Hold Off <RTOR2 Register>
00840    * @param Ravg: R to R Interval Averaging Weight Factor <RTOR2 Register>
00841    * @param Rhsf: R to R Interval Hold Off Scaling Factor <RTOR2 Register>
00842    * @param Clr_rrint: RTOR Detect Interrupt Clear behaviour <MNGR_INT Register>
00843    * @returns 0-if no error.  A non-zero value indicates an error.
00844    *
00845    */
00846   int max30001_RtoR_InitStart(uint8_t En_rtor, uint8_t Wndw, uint8_t Gain,
00847                               uint8_t Pavg, uint8_t Ptsf, uint8_t Hoff,
00848                               uint8_t Ravg, uint8_t Rhsf, uint8_t Clr_rrint);
00849 
00850   /**
00851    * @brief For MAX30001/3/4 ONLY
00852    * @brief This function disables the RtoR.  Uses Register CNFG_RTOR1-0x1D
00853    * @returns 0-if no error.  A non-zero value indicates an error.
00854    *
00855    */
00856   int max30001_Stop_RtoR(void);
00857 
00858   /**
00859    * @brief This is a function that waits for the PLL to lock; once a lock is achieved it exits out. (For convenience only)
00860    * @returns 0-if no error.  A non-zero value indicates an error.
00861    *
00862    */
00863   int max30001_PLL_lock(void);
00864 
00865   /**
00866    * @brief This function causes the MAX30001 to reset.  Uses Register SW_RST-0x08
00867    * @return 0-if no error.  A non-zero value indicates an error.
00868    *
00869    */
00870   int max30001_sw_rst(void);
00871 
00872   /**
00873    * @brief This function provides a SYNCH operation.  Uses Register SYCNH-0x09. Please refer to the data sheet for
00874    * @brief the details on how to use this.
00875    * @returns 0-if no error.  A non-zero value indicates an error.
00876    *
00877    */
00878   int max30001_synch(void);
00879 
00880   /**
00881    * @brief This function performs a FIFO Reset.  Uses Register FIFO_RST-0x0A. Please refer to the data sheet
00882    * @brief for the details on how to use this.
00883    * @returns 0-if no error.  A non-zero value indicates an error.
00884    */
00885   int max300001_fifo_rst(void);
00886 
00887   /**
00888    *
00889    * @brief This is a callback function which collects all the data from the ECG, BIOZ, PACE and RtoR. It also handles
00890    * @brief Lead On/Off.  This  function is passed through the argument of max30001_COMMinit().
00891    * @returns 0-if no error.  A non-zero value indicates an error.
00892    *
00893    */
00894   int max30001_int_handler(void);
00895 
00896   /**
00897    * @brief This is function called from the max30001_int_handler() function and processes all the ECG, BIOZ, PACE
00898    * @brief and the RtoR data and sticks them in appropriate arrays and variables each unsigned 32 bits.
00899    * @param ECG data will be in the array (input): max30001_ECG_FIFO_buffer[]
00900    * @param Pace data will be in the array (input): max30001_PACE[]
00901    * @param RtoRdata will be in the variable (input): max30001_RtoR_data
00902    * @param BIOZ data will be in the array (input): max30001_BIOZ_FIFO_buffer[]
00903    * @param global  max30001_ECG_FIFO_buffer[]
00904    * @param global  max30001_PACE[]
00905    * @param global  max30001_BIOZ_FIFO_buffer[]
00906    * @param global  max30001_RtoR_data
00907    * @param global  max30001_DCLeadOff
00908    * @param global  max30001_ACLeadOff
00909    * @param global  max30001_LeadON
00910    * @returns 0-if no error.  A non-zero value indicates an error.
00911    *
00912    */
00913   int max30001_FIFO_LeadONOff_Read(void);
00914 
00915   /**
00916    * @brief This function allows writing to a register.
00917    * @param addr:  Address of the register to write to
00918    * @param data:  24-bit data read from the register.
00919    * @returns 0-if no error.  A non-zero value indicates an error.
00920    *
00921    */
00922   int max30001_reg_write(MAX30001_REG_map_t addr, uint32_t data);
00923 
00924   /**
00925    * @brief This function allows reading from a register
00926    * @param addr:   Address of the register to read from.
00927    * @param *return_data: pointer to the value read from the register.
00928    * @returns 0-if no error.  A non-zero value indicates an error.
00929    *
00930    */
00931   int max30001_reg_read(MAX30001_REG_map_t addr, uint32_t *return_data);
00932 
00933   /**
00934    * @brief This function enables the DC Lead Off detection. Either ECG or BIOZ can be detected, one at a time.
00935    * @brief Registers Used:  CNFG_GEN-0x10
00936    * @param En_dcloff: BIOZ Digital Lead Off Detection Enable
00937    * @param Ipol: DC Lead Off Current Polarity (if current sources are enabled/connected)
00938    * @param Imag: DC Lead off current Magnitude Selection
00939    * @param Vth: DC Lead Off Voltage Threshold Selection
00940    * @returns 0-if no error.  A non-zero value indicates an error.
00941    *
00942    */
00943   int max30001_Enable_DcLeadOFF_Init(int8_t En_dcloff, int8_t Ipol, int8_t Imag,
00944                                      int8_t Vth);
00945 
00946   /**
00947    * @brief This function disables the DC Lead OFF feature, whichever is active.
00948    * @returns 0-if no error.  A non-zero value indicates an error.
00949    *
00950    */
00951   int max30001_Disable_DcLeadOFF(void);
00952 
00953   /**
00954    * @brief This function sets up the BIOZ for AC Lead Off test.
00955    * @brief Registers Used:  CNFG_GEN-0x10, MNGR_DYN-0x05
00956    * @param En_bloff: BIOZ Digital Lead Off Detection Enable <CNFG_GEN register>
00957    * @param Bloff_hi_it:      DC Lead Off Current Polarity (if current sources are enabled/connected) <MNGR_DYN register>
00958    * @param Bloff_lo_it:      DC Lead off current Magnitude Selection <MNGR_DYN register>
00959    * @returns 0-if no error.  A non-zero value indicates an error.
00960    *
00961    */
00962   int max30001_BIOZ_Enable_ACLeadOFF_Init(uint8_t En_bloff, uint8_t Bloff_hi_it,
00963                                           uint8_t Bloff_lo_it);
00964 
00965   /**
00966    * @brief This function Turns of the BIOZ AC Lead OFF feature
00967    * @brief Registers Used:  CNFG_GEN-0x10
00968    * @returns 0-if no error.  A non-zero value indicates an error.
00969    *
00970    */
00971   int max30001_BIOZ_Disable_ACleadOFF(void);
00972 
00973   /**
00974    * @brief This function enables the Current Gnerator Monitor
00975    * @brief Registers Used:  CNFG_BIOZ-0x18
00976    * @returns 0-if no error.  A non-zero value indicates an error.
00977    *
00978    */
00979   int max30001_BIOZ_Enable_BCGMON(void);
00980 
00981   /**
00982    *
00983    * @brief This function enables the Lead ON detection. Either ECG or BIOZ can be detected, one at a time.
00984    * @brief Also, the en_bioz, en_ecg, en_pace setting is saved so that when this feature is disabled through the
00985    * @brief max30001_Disable_LeadON() function (or otherwise) the enable/disable state of those features can be retrieved.
00986    * @param Channel: ECG or BIOZ detection
00987    * @returns 0-if everything is good.  A non-zero value indicates an error.
00988    *
00989    */
00990   int max30001_Enable_LeadON(int8_t Channel);
00991 
00992   /**
00993    * @brief This function turns off the Lead ON feature, whichever one is active.  Also, retrieves the en_bioz,
00994    * @brief en_ecg, en_pace and sets it back to as it was.
00995    * @param 0-if everything is good.  A non-zero value indicates an error.
00996    *
00997    */
00998   int max30001_Disable_LeadON(void);
00999 
01000   /**
01001    *
01002    * @brief This function is toggled every 2 seconds to switch between ECG Lead ON and BIOZ Lead ON detect
01003    * @brief Adjust LEADOFF_SERVICE_TIME to determine the duration between the toggles.
01004    * @param CurrentTime - This gets fed the time by RTC_GetValue function
01005    *
01006    */
01007   void max30001_ServiceLeadON(uint32_t currentTime);
01008 
01009   /**
01010    *
01011    * @brief This function is toggled every 2 seconds to switch between ECG DC Lead Off and BIOZ DC Lead Off
01012    * @brief Adjust LEADOFF_SERVICE_TIME to determine the duration between the toggles.
01013    * @param CurrentTime - This gets fed the time by RTC_GetValue function
01014    *
01015    */
01016   void max30001_ServiceLeadoff(uint32_t currentTime);
01017 
01018   /**
01019    *
01020    * @brief This function sets current RtoR values and fmstr values in a pointer structure
01021    * @param hspValMax30001 - Pointer to a structure where to store the values
01022    *
01023    */
01024   void max30001_ReadHeartrateData(max30001_t *_hspValMax30001);
01025 
01026   /**
01027    * @brief type definition for data interrupt
01028    */
01029   typedef void (*PtrFunction)(uint32_t id, uint32_t *buffer, uint32_t length);
01030 
01031   /**
01032    * @brief Used to connect a callback for when interrupt data is available
01033    */
01034   void onDataAvailable(PtrFunction _onDataAvailable);
01035 
01036   static MAX30001 *instance;
01037 
01038   /// Interrupt status tracking variable
01039   bool m_max30001_int_happened_;
01040 
01041 
01042 private:
01043   void dataAvailable(uint32_t id, uint32_t *buffer, uint32_t length);
01044   /// interrupt handler for async spi events
01045   static void spiHandler(int events);
01046   /// wrapper method to transmit and recieve SPI data
01047   int SPI_Transmit(const uint8_t *tx_buf, uint32_t tx_size, uint8_t *rx_buf,
01048                    uint32_t rx_size);
01049    uint32_t readPace(int group, uint8_t* result);
01050 
01051   //jjj 14MAR17
01052   //pointer to DigitalOut for cs
01053   DigitalOut * m_cs;
01054   //jjj
01055   /// pointer to mbed SPI object
01056   SPI *m_spi;
01057   /// is this object the owner of the spi object
01058   bool spi_owner;
01059   /// buffer to use for async transfers
01060   uint8_t buffer[ASYNC_SPI_BUFFER_SIZE];
01061   /// function pointer to the async callback
01062   event_callback_t functionpointer;
01063   /// callback function when interrupt data is available
01064   PtrFunction onDataAvailableCallback;
01065 
01066 }; // End of MAX30001 Class
01067 
01068 /**
01069  * @brief Preventive measure used to dismiss interrupts that fire too early during
01070  * @brief initialization on INTB line
01071  *
01072  */
01073 void MAX30001Mid_IntB_Handler(void);
01074 
01075 /**
01076  * @brief Preventive measure used to dismiss interrupts that fire too early during
01077  * @brief initialization on INT2B line
01078  *
01079  */
01080 void MAX30001Mid_Int2B_Handler(void);
01081 
01082 /**
01083  * @brief Allows Interrupts to be accepted as valid.
01084  * @param state: 1-Allow interrupts, Any-Don't allow interrupts.
01085  *
01086  */
01087 void MAX30001_AllowInterrupts(int state);
01088 
01089 #endif /* MAX30001_H_ */