Spiker - Test program for Spikes when measuring 2 channels…

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Wim van der Vegt / Mbed 2 deprecated Spiker

Test program for Spikes when measuring 2 channels in Timer1/MAT1:0 triggering mode.

main.cpp@0:ff3d852b6266, 2011-11-30 (annotated)

Committer:: wvd_vegt
Date:: Wed Nov 30 17:02:16 2011 +0000
Revision:: 0:ff3d852b6266
Child:: 1:b6dcd0de2a17

Who changed what in which revision?

User	Revision	Line number	New contents of line
wvd_vegt	0:ff3d852b6266	1	#include "mbed.h"
wvd_vegt	0:ff3d852b6266	2	#include "ADC/adc.h"
wvd_vegt	0:ff3d852b6266	3
wvd_vegt	0:ff3d852b6266	4	//NOTE Baudrate 115200
wvd_vegt	0:ff3d852b6266	5	// Writes a . and flahes led 2 after each conversion of 1000 points (see MAX_SAMPLES)
wvd_vegt	0:ff3d852b6266	6	//
wvd_vegt	0:ff3d852b6266	7	// A spike is a point that deviates more that SpikeAmplitude of it neighbours (now 128).
wvd_vegt	0:ff3d852b6266	8	//
wvd_vegt	0:ff3d852b6266	9	// Measured on AD0 and AD1 without anything connected (so a nice humm).
wvd_vegt	0:ff3d852b6266	10	//
wvd_vegt	0:ff3d852b6266	11	// ADC Code that makes the difference is 'ADC adc(SAMPLE_RATE,1);'
wvd_vegt	0:ff3d852b6266	12	// Without it I had spikes (altough not now hen testing).
wvd_vegt	0:ff3d852b6266	13	//
wvd_vegt	0:ff3d852b6266	14	// ADC Code by sblandford (see ADC Folder). It is not used but
wvd_vegt	0:ff3d852b6266	15	// certainly initializes something i missed.
wvd_vegt	0:ff3d852b6266	16	//
wvd_vegt	0:ff3d852b6266	17	// Currently code runs nice with or without the ADC line! (but in my larger
wvd_vegt	0:ff3d852b6266	18	// program the ADC line DID make the difference.
wvd_vegt	0:ff3d852b6266	19	//
wvd_vegt	0:ff3d852b6266	20	// This 'cure' only worked in combination with timer1/mat1:0 triggering
wvd_vegt	0:ff3d852b6266	21	// Using ADC:Read Fails (no matter how timer), as did teh GPDMA based code
wvd_vegt	0:ff3d852b6266	22	// (Timer that schedules 2 channel DMA transfers at each interrupt).
wvd_vegt	0:ff3d852b6266	23
wvd_vegt	0:ff3d852b6266	24	//NOTE This Value can be changed to alter the detection criteria.
wvd_vegt	0:ff3d852b6266	25	#define SpikeAmplitude 128
wvd_vegt	0:ff3d852b6266	26
wvd_vegt	0:ff3d852b6266	27	DigitalOut myled1(LED1);
wvd_vegt	0:ff3d852b6266	28	DigitalOut myled2(LED2);
wvd_vegt	0:ff3d852b6266	29
wvd_vegt	0:ff3d852b6266	30	//We'll be using the Usb Serial port
wvd_vegt	0:ff3d852b6266	31	Serial usb(USBTX, USBRX); //tx, rx
wvd_vegt	0:ff3d852b6266	32
wvd_vegt	0:ff3d852b6266	33	//------------------------------------------------------------------------------
wvd_vegt	0:ff3d852b6266	34	//----Hardware Arrays.
wvd_vegt	0:ff3d852b6266	35	//------------------------------------------------------------------------------
wvd_vegt	0:ff3d852b6266	36
wvd_vegt	0:ff3d852b6266	37	//Define ADC array, Note p18 is used as DAC!
wvd_vegt	0:ff3d852b6266	38	AnalogIn adcs[5] = {AnalogIn(p15), AnalogIn(p16), AnalogIn(p17), AnalogIn(p19), AnalogIn(p20)};
wvd_vegt	0:ff3d852b6266	39
wvd_vegt	0:ff3d852b6266	40	//Define DAC array
wvd_vegt	0:ff3d852b6266	41	AnalogOut dac[1] = {AnalogOut(p18)};
wvd_vegt	0:ff3d852b6266	42
wvd_vegt	0:ff3d852b6266	43	//------------------------------------------------------------------------------
wvd_vegt	0:ff3d852b6266	44	//----ALL ADC Methods
wvd_vegt	0:ff3d852b6266	45	//------------------------------------------------------------------------------
wvd_vegt	0:ff3d852b6266	46
wvd_vegt	0:ff3d852b6266	47	#define XTAL_FREQ 12000000
wvd_vegt	0:ff3d852b6266	48
wvd_vegt	0:ff3d852b6266	49	//NOTE The Number of samples per call.
wvd_vegt	0:ff3d852b6266	50	#define MAX_SAMPLES 1000
wvd_vegt	0:ff3d852b6266	51
wvd_vegt	0:ff3d852b6266	52	//NOTE Only used for the statement below, the sample-rate is 1ms or lower (by skipping points).
wvd_vegt	0:ff3d852b6266	53	//#define SAMPLE_RATE 150000
wvd_vegt	0:ff3d852b6266	54
wvd_vegt	0:ff3d852b6266	55	//NOTE THIS LINE CURES THE SPIKES !!
wvd_vegt	0:ff3d852b6266	56	//ADC adc(SAMPLE_RATE,1);
wvd_vegt	0:ff3d852b6266	57
wvd_vegt	0:ff3d852b6266	58	//Current Skip Rate Index. (not important, left in to keep code identical)
wvd_vegt	0:ff3d852b6266	59	//Basically it allows me to skip points 'automatically' and thus have a varying sample time.
wvd_vegt	0:ff3d852b6266	60	static int adc_rate = 0;
wvd_vegt	0:ff3d852b6266	61
wvd_vegt	0:ff3d852b6266	62	//Start with every 10th point, end with every point. (not important, left in to keep code identical)
wvd_vegt	0:ff3d852b6266	63	static int adc_rates[2] = {1, 1};
wvd_vegt	0:ff3d852b6266	64
wvd_vegt	0:ff3d852b6266	65	//Stop with first skip rate at sample 5. -1 is forever. (not important, left in to keep code identical)
wvd_vegt	0:ff3d852b6266	66	static int adc_skippoint[2] = {-1, -1};
wvd_vegt	0:ff3d852b6266	67
wvd_vegt	0:ff3d852b6266	68	//Always start with a sample. (not important, left in to keep code identical)
wvd_vegt	0:ff3d852b6266	69	static int adc_skip = 1;
wvd_vegt	0:ff3d852b6266	70
wvd_vegt	0:ff3d852b6266	71	//Results and Timestamps
wvd_vegt	0:ff3d852b6266	72	unsigned long Samples0[MAX_SAMPLES];
wvd_vegt	0:ff3d852b6266	73	unsigned long Samples1[MAX_SAMPLES];
wvd_vegt	0:ff3d852b6266	74	unsigned long Timing01[MAX_SAMPLES];
wvd_vegt	0:ff3d852b6266	75
wvd_vegt	0:ff3d852b6266	76	Timer adc_stamper; //Timestamping Samples.
wvd_vegt	0:ff3d852b6266	77	Timer match_timing; //Total Sampling Time.
wvd_vegt	0:ff3d852b6266	78
wvd_vegt	0:ff3d852b6266	79	//------------------------------------------------------------------------------
wvd_vegt	0:ff3d852b6266	80	//----CID_TIMER (MAT1.0 Based ADC Triggering)
wvd_vegt	0:ff3d852b6266	81	//------------------------------------------------------------------------------
wvd_vegt	0:ff3d852b6266	82
wvd_vegt	0:ff3d852b6266	83	volatile uint32_t timer1hits = 0; // timer1 stops when timer1hits==imer1loop
wvd_vegt	0:ff3d852b6266	84	uint32_t match = 500; // 0.5ms (2Mhz/1000)
wvd_vegt	0:ff3d852b6266	85	uint32_t prescaler = 96-1; // 96Mhz/96 = 1Mhz
wvd_vegt	0:ff3d852b6266	86
wvd_vegt	0:ff3d852b6266	87	//See http://mbed.org/forum/mbed/topic/1965/?page=1#comment-10043
wvd_vegt	0:ff3d852b6266	88
wvd_vegt	0:ff3d852b6266	89	//Manually start a conversion (and cause an interrupt).
wvd_vegt	0:ff3d852b6266	90	//NOTE: CLKDIV can be change to alter the ADC Clock.
wvd_vegt	0:ff3d852b6266	91	#define CLKDIV 1UL
wvd_vegt	0:ff3d852b6266	92	#define START_CONVERSION_NOW(ch) \
wvd_vegt	0:ff3d852b6266	93	LPC_ADC->ADCR=(0x1<<24)\|(1UL<<21)\|(CLKDIV<<8)\|ch;\
wvd_vegt	0:ff3d852b6266	94	NVIC_EnableIRQ(ADC_IRQn);\
wvd_vegt	0:ff3d852b6266	95	LPC_ADC->ADINTEN = 0x3
wvd_vegt	0:ff3d852b6266	96
wvd_vegt	0:ff3d852b6266	97	//Trigger ADC on falling edge of MAT1:0 (and have it cause an interrupt).
wvd_vegt	0:ff3d852b6266	98	#define START_CONVERSION_TIMED(ch) \
wvd_vegt	0:ff3d852b6266	99	LPC_ADC->ADCR=(0x6<<24)\|(1UL<<21)\|(CLKDIV<<8)\|ch;\
wvd_vegt	0:ff3d852b6266	100	NVIC_EnableIRQ(ADC_IRQn);\
wvd_vegt	0:ff3d852b6266	101	LPC_ADC->ADINTEN = 0x3;\
wvd_vegt	0:ff3d852b6266	102	LPC_TIM1->TCR=0;\
wvd_vegt	0:ff3d852b6266	103	LPC_TIM1->TCR=1
wvd_vegt	0:ff3d852b6266	104
wvd_vegt	0:ff3d852b6266	105	extern "C" void Adc_IRQHandler(void) __irq {
wvd_vegt	0:ff3d852b6266	106	//LPC_TIM1->MR0 = match-1; //* Reload MR0 does not seem to be neccesary.
wvd_vegt	0:ff3d852b6266	107	LPC_TIM1->IR = 0x1UL; //* Re-eanbled
wvd_vegt	0:ff3d852b6266	108
wvd_vegt	0:ff3d852b6266	109	Timing01[timer1hits]=adc_stamper.read_us();
wvd_vegt	0:ff3d852b6266	110
wvd_vegt	0:ff3d852b6266	111	//TODO Toggle Channel Mask (01 to 01 in ADCR).
wvd_vegt	0:ff3d852b6266	112	// Take twice the number of samples at half the sampling time
wvd_vegt	0:ff3d852b6266	113	// So 2000 samples (1000+1000) at 0.5ms -> 1000 pairs in 1 sec.
wvd_vegt	0:ff3d852b6266	114
wvd_vegt	0:ff3d852b6266	115	switch (LPC_ADC->ADSTAT & 0xFF) {
wvd_vegt	0:ff3d852b6266	116	case 0x01:
wvd_vegt	0:ff3d852b6266	117	Samples0[timer1hits] = LPC_ADC->ADDR0;// adc[0];
wvd_vegt	0:ff3d852b6266	118	START_CONVERSION_NOW(0x02);
wvd_vegt	0:ff3d852b6266	119	break;
wvd_vegt	0:ff3d852b6266	120
wvd_vegt	0:ff3d852b6266	121	case 0x02:
wvd_vegt	0:ff3d852b6266	122	Samples1[timer1hits] = LPC_ADC->ADDR1;// adc[1];
wvd_vegt	0:ff3d852b6266	123	START_CONVERSION_TIMED(0x01);
wvd_vegt	0:ff3d852b6266	124
wvd_vegt	0:ff3d852b6266	125	//Skip Samples to lower rates. Change adc_rate to change sample rate.
wvd_vegt	0:ff3d852b6266	126	adc_skip--;
wvd_vegt	0:ff3d852b6266	127	if (adc_skip==0) {
wvd_vegt	0:ff3d852b6266	128	if (adc_skippoint[adc_rate]!=-1 && timer1hits==adc_skippoint[adc_rate]) {
wvd_vegt	0:ff3d852b6266	129	adc_rate++;
wvd_vegt	0:ff3d852b6266	130	}
wvd_vegt	0:ff3d852b6266	131
wvd_vegt	0:ff3d852b6266	132	//Reload adc_skip
wvd_vegt	0:ff3d852b6266	133	adc_skip = adc_rates[adc_rate];
wvd_vegt	0:ff3d852b6266	134
wvd_vegt	0:ff3d852b6266	135	timer1hits++;
wvd_vegt	0:ff3d852b6266	136	}
wvd_vegt	0:ff3d852b6266	137
wvd_vegt	0:ff3d852b6266	138	if (timer1hits==MAX_SAMPLES) {
wvd_vegt	0:ff3d852b6266	139	match_timing.stop();
wvd_vegt	0:ff3d852b6266	140
wvd_vegt	0:ff3d852b6266	141	NVIC_DisableIRQ(ADC_IRQn);
wvd_vegt	0:ff3d852b6266	142
wvd_vegt	0:ff3d852b6266	143	LPC_TIM1->TCR = 0x00; // Disable Timer
wvd_vegt	0:ff3d852b6266	144	}
wvd_vegt	0:ff3d852b6266	145
wvd_vegt	0:ff3d852b6266	146	break;
wvd_vegt	0:ff3d852b6266	147	}
wvd_vegt	0:ff3d852b6266	148	}
wvd_vegt	0:ff3d852b6266	149
wvd_vegt	0:ff3d852b6266	150	//*******************************
wvd_vegt	0:ff3d852b6266	151	//NOTE: Timer1 Driven ADC.
wvd_vegt	0:ff3d852b6266	152	//
wvd_vegt	0:ff3d852b6266	153	// Works but way to fast!!
wvd_vegt	0:ff3d852b6266	154	//
wvd_vegt	0:ff3d852b6266	155	// Did not work previously because connected
wvd_vegt	0:ff3d852b6266	156	// to the wrong IRQ (should be the adc one).
wvd_vegt	0:ff3d852b6266	157	//
wvd_vegt	0:ff3d852b6266	158	// Skips 1 usec every 2*10 samples.
wvd_vegt	0:ff3d852b6266	159	//*******************************
wvd_vegt	0:ff3d852b6266	160	int Measure() {
wvd_vegt	0:ff3d852b6266	161	int spikes=0;
wvd_vegt	0:ff3d852b6266	162
wvd_vegt	0:ff3d852b6266	163	// Enable the ISR vector
wvd_vegt	0:ff3d852b6266	164	NVIC_SetVector(ADC_IRQn, (uint32_t)&Adc_IRQHandler);
wvd_vegt	0:ff3d852b6266	165
wvd_vegt	0:ff3d852b6266	166	// Set PCLK_TIMER1
wvd_vegt	0:ff3d852b6266	167	// PCLK_TIMER1 = CCLK/1 96M/1 = 96MHz
wvd_vegt	0:ff3d852b6266	168	LPC_SC->PCLKSEL0 &= ~(3UL << 4); // Clear bits
wvd_vegt	0:ff3d852b6266	169	LPC_SC->PCLKSEL0 \|= (1UL << 4); // Set bit
wvd_vegt	0:ff3d852b6266	170
wvd_vegt	0:ff3d852b6266	171	LPC_SC->PCONP \|= 1 << 2; // Power on Timer 1
wvd_vegt	0:ff3d852b6266	172
wvd_vegt	0:ff3d852b6266	173	LPC_TIM1->TCR = 0x2UL; // Reset and set to timer mode
wvd_vegt	0:ff3d852b6266	174
wvd_vegt	0:ff3d852b6266	175	//NOTE match-2 is to much (seems like a clock is off somehwere).
wvd_vegt	0:ff3d852b6266	176
wvd_vegt	0:ff3d852b6266	177	LPC_TIM1->CTCR = 0x0UL; // Connect to prescaler
wvd_vegt	0:ff3d852b6266	178	LPC_TIM1->PR = prescaler; // Prescale -> 1Mhz
wvd_vegt	0:ff3d852b6266	179	LPC_TIM1->MR0 = match-1; // Match count for 5mS (we toggle so end up with half)
wvd_vegt	0:ff3d852b6266	180	LPC_TIM1->MCR = 2; // Reset TCR to zero on match
wvd_vegt	0:ff3d852b6266	181
wvd_vegt	0:ff3d852b6266	182	//See http://mbed.org/forum/mbed/topic/1965/?page=1#comment-10043
wvd_vegt	0:ff3d852b6266	183	LPC_TIM1->EMR = (3UL<<4)\|1; // Make MAT1.0 toggle (see START_CONVERSION_TIMED MACRO).
wvd_vegt	0:ff3d852b6266	184
wvd_vegt	0:ff3d852b6266	185	// veg - ADC Max Clock = 13MHz. One conversion takes 65cycles so 200Khz Sampling frequency!
wvd_vegt	0:ff3d852b6266	186	// For nice exact values for a single conversion we need the ADC Clock to be a 65 fold (So overclock).
wvd_vegt	0:ff3d852b6266	187
wvd_vegt	0:ff3d852b6266	188	// Power up the ADC and set PCLK
wvd_vegt	0:ff3d852b6266	189	LPC_SC->PCLKSEL0 &= ~(3UL << 16); // PCLK = CCLK/4 96M/4 = 24MHz
wvd_vegt	0:ff3d852b6266	190
wvd_vegt	0:ff3d852b6266	191	LPC_SC->PCONP \|= (1UL << 12); // Power on ADC
wvd_vegt	0:ff3d852b6266	192	LPC_ADC->ADCR \|= (1UL << 21) \| (CLKDIV<<8); // * Enable ADC & Set Divider Sample Rate 24Mhz / CLKDIV+1
wvd_vegt	0:ff3d852b6266	193
wvd_vegt	0:ff3d852b6266	194	// Set the pin functions to ADC
wvd_vegt	0:ff3d852b6266	195	LPC_PINCON->PINSEL1 &= ~(3UL << 14); // P0.23, Mbed p15. (AD0)
wvd_vegt	0:ff3d852b6266	196	LPC_PINCON->PINSEL1 \|= (1UL << 14);
wvd_vegt	0:ff3d852b6266	197	LPC_PINCON->PINSEL1 &= ~(3UL << 16); // P0.24, Mbed p16. (AD1)
wvd_vegt	0:ff3d852b6266	198	LPC_PINCON->PINSEL1 \|= (1UL << 16);
wvd_vegt	0:ff3d852b6266	199
wvd_vegt	0:ff3d852b6266	200	memset(Samples0, 0, sizeof(Samples0));
wvd_vegt	0:ff3d852b6266	201	memset(Samples1, 0, sizeof(Samples1));
wvd_vegt	0:ff3d852b6266	202
wvd_vegt	0:ff3d852b6266	203	// Enable the ADC, 12MHz, ADC0.0, ADC0.1 -> Macro/Defines!
wvd_vegt	0:ff3d852b6266	204	// LPC_ADC->ADCR = (1UL << 21) \| (1UL << 8) \| (3UL << 0);
wvd_vegt	0:ff3d852b6266	205
wvd_vegt	0:ff3d852b6266	206	//Reset Test Variable.
wvd_vegt	0:ff3d852b6266	207	timer1hits = 0;
wvd_vegt	0:ff3d852b6266	208
wvd_vegt	0:ff3d852b6266	209	//Reset Skip Rate.
wvd_vegt	0:ff3d852b6266	210	adc_rate = 0;
wvd_vegt	0:ff3d852b6266	211	adc_skip = 1; // We start with a sample!
wvd_vegt	0:ff3d852b6266	212
wvd_vegt	0:ff3d852b6266	213	adc_stamper.reset();
wvd_vegt	0:ff3d852b6266	214	adc_stamper.start();
wvd_vegt	0:ff3d852b6266	215
wvd_vegt	0:ff3d852b6266	216	match_timing.reset();
wvd_vegt	0:ff3d852b6266	217	match_timing.start();
wvd_vegt	0:ff3d852b6266	218
wvd_vegt	0:ff3d852b6266	219	START_CONVERSION_TIMED(0x01);
wvd_vegt	0:ff3d852b6266	220
wvd_vegt	0:ff3d852b6266	221	//Pause until timer stops.
wvd_vegt	0:ff3d852b6266	222	while (LPC_TIM1->TCR==1) {
wvd_vegt	0:ff3d852b6266	223	wait(0.001);
wvd_vegt	0:ff3d852b6266	224	}
wvd_vegt	0:ff3d852b6266	225
wvd_vegt	0:ff3d852b6266	226	//LPC_ADC->ADCR &= ~(7UL << 24); // Clear ADC Start bits -> Macro/Defines!
wvd_vegt	0:ff3d852b6266	227
wvd_vegt	0:ff3d852b6266	228	int elapsed = match_timing.read_us();
wvd_vegt	0:ff3d852b6266	229
wvd_vegt	0:ff3d852b6266	230	match_timing.stop();
wvd_vegt	0:ff3d852b6266	231
wvd_vegt	0:ff3d852b6266	232	adc_stamper.stop();
wvd_vegt	0:ff3d852b6266	233
wvd_vegt	0:ff3d852b6266	234	for (int i=1; i < MAX_SAMPLES-1; i++) {
wvd_vegt	0:ff3d852b6266	235
wvd_vegt	0:ff3d852b6266	236	int lv = (Samples0[i-1]>>4) & 0xFFF;
wvd_vegt	0:ff3d852b6266	237	int cv = (Samples0[i+0]>>4) & 0xFFF;
wvd_vegt	0:ff3d852b6266	238	int nv = (Samples0[i+1]>>4) & 0xFFF;
wvd_vegt	0:ff3d852b6266	239
wvd_vegt	0:ff3d852b6266	240	if (((cv >= lv + SpikeAmplitude) && (cv >= nv + SpikeAmplitude)) \|\|
wvd_vegt	0:ff3d852b6266	241	((cv <= lv - SpikeAmplitude) && (cv <= nv - SpikeAmplitude))) {
wvd_vegt	0:ff3d852b6266	242	usb.printf("\r\nSpike on Channel AD%d @ %d [%04u] [%04u] [%04u]\r\n", 0, i, lv, cv, nv);
wvd_vegt	0:ff3d852b6266	243	spikes++;
wvd_vegt	0:ff3d852b6266	244	}
wvd_vegt	0:ff3d852b6266	245	}
wvd_vegt	0:ff3d852b6266	246
wvd_vegt	0:ff3d852b6266	247	for (int i=1; i < MAX_SAMPLES-1; i++) {
wvd_vegt	0:ff3d852b6266	248
wvd_vegt	0:ff3d852b6266	249	int lv = (Samples1[i-1]>>4) & 0xFFF;
wvd_vegt	0:ff3d852b6266	250	int cv = (Samples1[i+0]>>4) & 0xFFF;
wvd_vegt	0:ff3d852b6266	251	int nv = (Samples1[i+1]>>4) & 0xFFF;
wvd_vegt	0:ff3d852b6266	252
wvd_vegt	0:ff3d852b6266	253	if (((cv >= lv + SpikeAmplitude) && (cv >= nv + SpikeAmplitude)) \|\|
wvd_vegt	0:ff3d852b6266	254	((cv <= lv - SpikeAmplitude) && (cv <= nv - SpikeAmplitude))) {
wvd_vegt	0:ff3d852b6266	255	usb.printf("\r\nSpike on Channel AD%d @ %d [%04u] [%04u] [%04u]\r\n", 1, i, lv, cv, nv);
wvd_vegt	0:ff3d852b6266	256	spikes++;
wvd_vegt	0:ff3d852b6266	257	}
wvd_vegt	0:ff3d852b6266	258	}
wvd_vegt	0:ff3d852b6266	259
wvd_vegt	0:ff3d852b6266	260	//NOTE Powering the ADC ON/OFF does not seem to be neccesary.
wvd_vegt	0:ff3d852b6266	261
wvd_vegt	0:ff3d852b6266	262	LPC_ADC->ADCR \|= (1UL << 21); // * Disable ADC
wvd_vegt	0:ff3d852b6266	263	LPC_SC->PCONP \|= (1UL << 12); // * Power off ADC
wvd_vegt	0:ff3d852b6266	264
wvd_vegt	0:ff3d852b6266	265	match_timing.reset();
wvd_vegt	0:ff3d852b6266	266
wvd_vegt	0:ff3d852b6266	267	return spikes;
wvd_vegt	0:ff3d852b6266	268	}
wvd_vegt	0:ff3d852b6266	269
wvd_vegt	0:ff3d852b6266	270	int main() {
wvd_vegt	0:ff3d852b6266	271	usb.baud(115200);
wvd_vegt	0:ff3d852b6266	272
wvd_vegt	0:ff3d852b6266	273	while (1) {
wvd_vegt	0:ff3d852b6266	274	myled1=false;
wvd_vegt	0:ff3d852b6266	275
wvd_vegt	0:ff3d852b6266	276	if (Measure()!=0) {
wvd_vegt	0:ff3d852b6266	277	myled1 = !myled1;
wvd_vegt	0:ff3d852b6266	278	}
wvd_vegt	0:ff3d852b6266	279
wvd_vegt	0:ff3d852b6266	280	myled2 = !myled2;
wvd_vegt	0:ff3d852b6266	281	usb.printf(".");
wvd_vegt	0:ff3d852b6266	282	wait_ms(100);
wvd_vegt	0:ff3d852b6266	283	myled2 = !myled2;
wvd_vegt	0:ff3d852b6266	284	}
wvd_vegt	0:ff3d852b6266	285	}

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	30 Nov 2011
Imports:	6
Forks:	0
Commits:	3
Dependents:	0
Dependencies:	1
Followers:	2

This repository is Public (Unlisted).

main.cpp@0:ff3d852b6266, 2011-11-30 (annotated)

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