Witek Ewert / Mbed 2 deprecated KL46Z-Lab2_lodz

Sensor reporting over USB CDC

Dependencies:   MAG3110 MMA8451Q SLCD- TSI USBDevice mbed

USBDevice/USBDevice/USBRegs_STM32.h@0:7b58cdacf811, 2014-04-16 (annotated)

Committer:
wue
Date:
Wed Apr 16 12:20:12 2014 +0000
Revision:
0:7b58cdacf811
Sensor reporting over USB CDC

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wue 0:7b58cdacf811 1 /**
wue 0:7b58cdacf811 2 ******************************************************************************
wue 0:7b58cdacf811 3 * @file usb_regs.h
wue 0:7b58cdacf811 4 * @author MCD Application Team
wue 0:7b58cdacf811 5 * @version V2.1.0
wue 0:7b58cdacf811 6 * @date 19-March-2012
wue 0:7b58cdacf811 7 * @brief hardware registers
wue 0:7b58cdacf811 8 ******************************************************************************
wue 0:7b58cdacf811 9 * @attention
wue 0:7b58cdacf811 10 *
wue 0:7b58cdacf811 11 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
wue 0:7b58cdacf811 12 *
wue 0:7b58cdacf811 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
wue 0:7b58cdacf811 14 * You may not use this file except in compliance with the License.
wue 0:7b58cdacf811 15 * You may obtain a copy of the License at:
wue 0:7b58cdacf811 16 *
wue 0:7b58cdacf811 17 * http://www.st.com/software_license_agreement_liberty_v2
wue 0:7b58cdacf811 18 *
wue 0:7b58cdacf811 19 * Unless required by applicable law or agreed to in writing, software
wue 0:7b58cdacf811 20 * distributed under the License is distributed on an "AS IS" BASIS,
wue 0:7b58cdacf811 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
wue 0:7b58cdacf811 22 * See the License for the specific language governing permissions and
wue 0:7b58cdacf811 23 * limitations under the License.
wue 0:7b58cdacf811 24 *
wue 0:7b58cdacf811 25 ******************************************************************************
wue 0:7b58cdacf811 26 */
wue 0:7b58cdacf811 27
wue 0:7b58cdacf811 28 #ifndef __USB_OTG_REGS_H__
wue 0:7b58cdacf811 29 #define __USB_OTG_REGS_H__
wue 0:7b58cdacf811 30
wue 0:7b58cdacf811 31 typedef struct //000h
wue 0:7b58cdacf811 32 {
wue 0:7b58cdacf811 33 __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
wue 0:7b58cdacf811 34 __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
wue 0:7b58cdacf811 35 __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
wue 0:7b58cdacf811 36 __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
wue 0:7b58cdacf811 37 __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
wue 0:7b58cdacf811 38 __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
wue 0:7b58cdacf811 39 __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
wue 0:7b58cdacf811 40 __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
wue 0:7b58cdacf811 41 __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
wue 0:7b58cdacf811 42 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
wue 0:7b58cdacf811 43 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
wue 0:7b58cdacf811 44 __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
wue 0:7b58cdacf811 45 uint32_t Reserved30[2]; /* Reserved 030h*/
wue 0:7b58cdacf811 46 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
wue 0:7b58cdacf811 47 __IO uint32_t CID; /* User ID Register 03Ch*/
wue 0:7b58cdacf811 48 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
wue 0:7b58cdacf811 49 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
wue 0:7b58cdacf811 50 __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
wue 0:7b58cdacf811 51 }
wue 0:7b58cdacf811 52 USB_OTG_GREGS;
wue 0:7b58cdacf811 53
wue 0:7b58cdacf811 54 typedef struct // 800h
wue 0:7b58cdacf811 55 {
wue 0:7b58cdacf811 56 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
wue 0:7b58cdacf811 57 __IO uint32_t DCTL; /* dev Control Register 804h*/
wue 0:7b58cdacf811 58 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
wue 0:7b58cdacf811 59 uint32_t Reserved0C; /* Reserved 80Ch*/
wue 0:7b58cdacf811 60 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
wue 0:7b58cdacf811 61 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
wue 0:7b58cdacf811 62 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
wue 0:7b58cdacf811 63 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
wue 0:7b58cdacf811 64 uint32_t Reserved20; /* Reserved 820h*/
wue 0:7b58cdacf811 65 uint32_t Reserved9; /* Reserved 824h*/
wue 0:7b58cdacf811 66 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
wue 0:7b58cdacf811 67 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
wue 0:7b58cdacf811 68 __IO uint32_t DTHRCTL; /* dev thr 830h*/
wue 0:7b58cdacf811 69 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
wue 0:7b58cdacf811 70 }
wue 0:7b58cdacf811 71 USB_OTG_DREGS;
wue 0:7b58cdacf811 72
wue 0:7b58cdacf811 73 typedef struct
wue 0:7b58cdacf811 74 {
wue 0:7b58cdacf811 75 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
wue 0:7b58cdacf811 76 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
wue 0:7b58cdacf811 77 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
wue 0:7b58cdacf811 78 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
wue 0:7b58cdacf811 79 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
wue 0:7b58cdacf811 80 uint32_t Reserved14;
wue 0:7b58cdacf811 81 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
wue 0:7b58cdacf811 82 uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
wue 0:7b58cdacf811 83 }
wue 0:7b58cdacf811 84 USB_OTG_INEPREGS;
wue 0:7b58cdacf811 85
wue 0:7b58cdacf811 86 typedef struct
wue 0:7b58cdacf811 87 {
wue 0:7b58cdacf811 88 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
wue 0:7b58cdacf811 89 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
wue 0:7b58cdacf811 90 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
wue 0:7b58cdacf811 91 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
wue 0:7b58cdacf811 92 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
wue 0:7b58cdacf811 93 uint32_t Reserved14[3];
wue 0:7b58cdacf811 94 }
wue 0:7b58cdacf811 95 USB_OTG_OUTEPREGS;
wue 0:7b58cdacf811 96
wue 0:7b58cdacf811 97 typedef struct
wue 0:7b58cdacf811 98 {
wue 0:7b58cdacf811 99 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
wue 0:7b58cdacf811 100 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
wue 0:7b58cdacf811 101 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
wue 0:7b58cdacf811 102 uint32_t Reserved40C; /* Reserved 40Ch*/
wue 0:7b58cdacf811 103 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
wue 0:7b58cdacf811 104 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
wue 0:7b58cdacf811 105 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
wue 0:7b58cdacf811 106 }
wue 0:7b58cdacf811 107 USB_OTG_HREGS;
wue 0:7b58cdacf811 108
wue 0:7b58cdacf811 109 typedef struct
wue 0:7b58cdacf811 110 {
wue 0:7b58cdacf811 111 __IO uint32_t HCCHAR;
wue 0:7b58cdacf811 112 __IO uint32_t HCSPLT;
wue 0:7b58cdacf811 113 __IO uint32_t HCINT;
wue 0:7b58cdacf811 114 __IO uint32_t HCINTMSK;
wue 0:7b58cdacf811 115 __IO uint32_t HCTSIZ;
wue 0:7b58cdacf811 116 uint32_t Reserved[3];
wue 0:7b58cdacf811 117 }
wue 0:7b58cdacf811 118 USB_OTG_HC_REGS;
wue 0:7b58cdacf811 119
wue 0:7b58cdacf811 120 typedef struct
wue 0:7b58cdacf811 121 {
wue 0:7b58cdacf811 122 USB_OTG_GREGS GREGS;
wue 0:7b58cdacf811 123 uint32_t RESERVED0[188];
wue 0:7b58cdacf811 124 USB_OTG_HREGS HREGS;
wue 0:7b58cdacf811 125 uint32_t RESERVED1[9];
wue 0:7b58cdacf811 126 __IO uint32_t HPRT;
wue 0:7b58cdacf811 127 uint32_t RESERVED2[47];
wue 0:7b58cdacf811 128 USB_OTG_HC_REGS HC_REGS[8];
wue 0:7b58cdacf811 129 uint32_t RESERVED3[128];
wue 0:7b58cdacf811 130 USB_OTG_DREGS DREGS;
wue 0:7b58cdacf811 131 uint32_t RESERVED4[50];
wue 0:7b58cdacf811 132 USB_OTG_INEPREGS INEP_REGS[4];
wue 0:7b58cdacf811 133 uint32_t RESERVED5[96];
wue 0:7b58cdacf811 134 USB_OTG_OUTEPREGS OUTEP_REGS[4];
wue 0:7b58cdacf811 135 uint32_t RESERVED6[160];
wue 0:7b58cdacf811 136 __IO uint32_t PCGCCTL;
wue 0:7b58cdacf811 137 uint32_t RESERVED7[127];
wue 0:7b58cdacf811 138 __IO uint32_t FIFO[4][1024];
wue 0:7b58cdacf811 139 }
wue 0:7b58cdacf811 140 USB_OTG_CORE_REGS;
wue 0:7b58cdacf811 141
wue 0:7b58cdacf811 142
wue 0:7b58cdacf811 143 #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
wue 0:7b58cdacf811 144 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
wue 0:7b58cdacf811 145
wue 0:7b58cdacf811 146 #endif //__USB_OTG_REGS_H__
wue 0:7b58cdacf811 147
wue 0:7b58cdacf811 148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
wue 0:7b58cdacf811 149