Witek Ewert / Mbed 2 deprecated KL46Z-Lab2_lodz

Sensor reporting over USB CDC

Dependencies:   MAG3110 MMA8451Q SLCD- TSI USBDevice mbed

USBDevice/USBDevice/USBHAL_STM32F4.cpp@0:7b58cdacf811, 2014-04-16 (annotated)

Committer:
wue
Date:
Wed Apr 16 12:20:12 2014 +0000
Revision:
0:7b58cdacf811
Sensor reporting over USB CDC

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wue 0:7b58cdacf811 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
wue 0:7b58cdacf811 2 *
wue 0:7b58cdacf811 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
wue 0:7b58cdacf811 4 * and associated documentation files (the "Software"), to deal in the Software without
wue 0:7b58cdacf811 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
wue 0:7b58cdacf811 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
wue 0:7b58cdacf811 7 * Software is furnished to do so, subject to the following conditions:
wue 0:7b58cdacf811 8 *
wue 0:7b58cdacf811 9 * The above copyright notice and this permission notice shall be included in all copies or
wue 0:7b58cdacf811 10 * substantial portions of the Software.
wue 0:7b58cdacf811 11 *
wue 0:7b58cdacf811 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
wue 0:7b58cdacf811 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
wue 0:7b58cdacf811 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
wue 0:7b58cdacf811 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
wue 0:7b58cdacf811 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
wue 0:7b58cdacf811 17 */
wue 0:7b58cdacf811 18
wue 0:7b58cdacf811 19 #if defined(TARGET_STM32F4XX)
wue 0:7b58cdacf811 20
wue 0:7b58cdacf811 21 #include "USBHAL.h"
wue 0:7b58cdacf811 22 #include "USBRegs_STM32.h"
wue 0:7b58cdacf811 23 #include "pinmap.h"
wue 0:7b58cdacf811 24
wue 0:7b58cdacf811 25 USBHAL * USBHAL::instance;
wue 0:7b58cdacf811 26
wue 0:7b58cdacf811 27 static volatile int epComplete = 0;
wue 0:7b58cdacf811 28
wue 0:7b58cdacf811 29 static uint32_t bufferEnd = 0;
wue 0:7b58cdacf811 30 static const uint32_t rxFifoSize = 512;
wue 0:7b58cdacf811 31 static uint32_t rxFifoCount = 0;
wue 0:7b58cdacf811 32
wue 0:7b58cdacf811 33 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
wue 0:7b58cdacf811 34
wue 0:7b58cdacf811 35 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
wue 0:7b58cdacf811 36 return 0;
wue 0:7b58cdacf811 37 }
wue 0:7b58cdacf811 38
wue 0:7b58cdacf811 39 USBHAL::USBHAL(void) {
wue 0:7b58cdacf811 40 NVIC_DisableIRQ(OTG_FS_IRQn);
wue 0:7b58cdacf811 41 epCallback[0] = &USBHAL::EP1_OUT_callback;
wue 0:7b58cdacf811 42 epCallback[1] = &USBHAL::EP1_IN_callback;
wue 0:7b58cdacf811 43 epCallback[2] = &USBHAL::EP2_OUT_callback;
wue 0:7b58cdacf811 44 epCallback[3] = &USBHAL::EP2_IN_callback;
wue 0:7b58cdacf811 45 epCallback[4] = &USBHAL::EP3_OUT_callback;
wue 0:7b58cdacf811 46 epCallback[5] = &USBHAL::EP3_IN_callback;
wue 0:7b58cdacf811 47
wue 0:7b58cdacf811 48 // Enable power and clocking
wue 0:7b58cdacf811 49 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
wue 0:7b58cdacf811 50
wue 0:7b58cdacf811 51 pin_function(PA_8, STM_PIN_DATA(2, 10));
wue 0:7b58cdacf811 52 pin_function(PA_9, STM_PIN_DATA(0, 0));
wue 0:7b58cdacf811 53 pin_function(PA_10, STM_PIN_DATA(2, 10));
wue 0:7b58cdacf811 54 pin_function(PA_11, STM_PIN_DATA(2, 10));
wue 0:7b58cdacf811 55 pin_function(PA_12, STM_PIN_DATA(2, 10));
wue 0:7b58cdacf811 56
wue 0:7b58cdacf811 57 // Set ID pin to open drain with pull-up resistor
wue 0:7b58cdacf811 58 pin_mode(PA_10, OpenDrain);
wue 0:7b58cdacf811 59 GPIOA->PUPDR &= ~(0x3 << 20);
wue 0:7b58cdacf811 60 GPIOA->PUPDR |= 1 << 20;
wue 0:7b58cdacf811 61
wue 0:7b58cdacf811 62 // Set VBUS pin to open drain
wue 0:7b58cdacf811 63 pin_mode(PA_9, OpenDrain);
wue 0:7b58cdacf811 64
wue 0:7b58cdacf811 65 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
wue 0:7b58cdacf811 66
wue 0:7b58cdacf811 67 // Enable interrupts
wue 0:7b58cdacf811 68 OTG_FS->GREGS.GAHBCFG |= (1 << 0);
wue 0:7b58cdacf811 69
wue 0:7b58cdacf811 70 // Turnaround time to maximum value - too small causes packet loss
wue 0:7b58cdacf811 71 OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
wue 0:7b58cdacf811 72
wue 0:7b58cdacf811 73 // Unmask global interrupts
wue 0:7b58cdacf811 74 OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
wue 0:7b58cdacf811 75 (1 << 4) | // RX FIFO not empty
wue 0:7b58cdacf811 76 (1 << 12); // USB reset
wue 0:7b58cdacf811 77
wue 0:7b58cdacf811 78 OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
wue 0:7b58cdacf811 79 (1 << 2); // Non-zero-length status OUT handshake
wue 0:7b58cdacf811 80
wue 0:7b58cdacf811 81 OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
wue 0:7b58cdacf811 82 (1 << 16); // Power Up
wue 0:7b58cdacf811 83
wue 0:7b58cdacf811 84 instance = this;
wue 0:7b58cdacf811 85 NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
wue 0:7b58cdacf811 86 NVIC_SetPriority(OTG_FS_IRQn, 1);
wue 0:7b58cdacf811 87 }
wue 0:7b58cdacf811 88
wue 0:7b58cdacf811 89 USBHAL::~USBHAL(void) {
wue 0:7b58cdacf811 90 }
wue 0:7b58cdacf811 91
wue 0:7b58cdacf811 92 void USBHAL::connect(void) {
wue 0:7b58cdacf811 93 NVIC_EnableIRQ(OTG_FS_IRQn);
wue 0:7b58cdacf811 94 }
wue 0:7b58cdacf811 95
wue 0:7b58cdacf811 96 void USBHAL::disconnect(void) {
wue 0:7b58cdacf811 97 NVIC_DisableIRQ(OTG_FS_IRQn);
wue 0:7b58cdacf811 98 }
wue 0:7b58cdacf811 99
wue 0:7b58cdacf811 100 void USBHAL::configureDevice(void) {
wue 0:7b58cdacf811 101 // Not needed
wue 0:7b58cdacf811 102 }
wue 0:7b58cdacf811 103
wue 0:7b58cdacf811 104 void USBHAL::unconfigureDevice(void) {
wue 0:7b58cdacf811 105 // Not needed
wue 0:7b58cdacf811 106 }
wue 0:7b58cdacf811 107
wue 0:7b58cdacf811 108 void USBHAL::setAddress(uint8_t address) {
wue 0:7b58cdacf811 109 OTG_FS->DREGS.DCFG |= (address << 4);
wue 0:7b58cdacf811 110 EP0write(0, 0);
wue 0:7b58cdacf811 111 }
wue 0:7b58cdacf811 112
wue 0:7b58cdacf811 113 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
wue 0:7b58cdacf811 114 uint32_t flags) {
wue 0:7b58cdacf811 115 uint32_t epIndex = endpoint >> 1;
wue 0:7b58cdacf811 116
wue 0:7b58cdacf811 117 uint32_t type;
wue 0:7b58cdacf811 118 switch (endpoint) {
wue 0:7b58cdacf811 119 case EP0IN:
wue 0:7b58cdacf811 120 case EP0OUT:
wue 0:7b58cdacf811 121 type = 0;
wue 0:7b58cdacf811 122 break;
wue 0:7b58cdacf811 123 case EPISO_IN:
wue 0:7b58cdacf811 124 case EPISO_OUT:
wue 0:7b58cdacf811 125 type = 1;
wue 0:7b58cdacf811 126 case EPBULK_IN:
wue 0:7b58cdacf811 127 case EPBULK_OUT:
wue 0:7b58cdacf811 128 type = 2;
wue 0:7b58cdacf811 129 break;
wue 0:7b58cdacf811 130 case EPINT_IN:
wue 0:7b58cdacf811 131 case EPINT_OUT:
wue 0:7b58cdacf811 132 type = 3;
wue 0:7b58cdacf811 133 break;
wue 0:7b58cdacf811 134 }
wue 0:7b58cdacf811 135
wue 0:7b58cdacf811 136 // Generic in or out EP controls
wue 0:7b58cdacf811 137 uint32_t control = (maxPacket << 0) | // Packet size
wue 0:7b58cdacf811 138 (1 << 15) | // Active endpoint
wue 0:7b58cdacf811 139 (type << 18); // Endpoint type
wue 0:7b58cdacf811 140
wue 0:7b58cdacf811 141 if (endpoint & 0x1) { // In Endpoint
wue 0:7b58cdacf811 142 // Set up the Tx FIFO
wue 0:7b58cdacf811 143 if (endpoint == EP0IN) {
wue 0:7b58cdacf811 144 OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
wue 0:7b58cdacf811 145 (bufferEnd << 0);
wue 0:7b58cdacf811 146 }
wue 0:7b58cdacf811 147 else {
wue 0:7b58cdacf811 148 OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
wue 0:7b58cdacf811 149 (bufferEnd << 0);
wue 0:7b58cdacf811 150 }
wue 0:7b58cdacf811 151 bufferEnd += maxPacket >> 2;
wue 0:7b58cdacf811 152
wue 0:7b58cdacf811 153 // Set the In EP specific control settings
wue 0:7b58cdacf811 154 if (endpoint != EP0IN) {
wue 0:7b58cdacf811 155 control |= (1 << 28); // SD0PID
wue 0:7b58cdacf811 156 }
wue 0:7b58cdacf811 157
wue 0:7b58cdacf811 158 control |= (epIndex << 22) | // TxFIFO index
wue 0:7b58cdacf811 159 (1 << 27); // SNAK
wue 0:7b58cdacf811 160 OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
wue 0:7b58cdacf811 161
wue 0:7b58cdacf811 162 // Unmask the interrupt
wue 0:7b58cdacf811 163 OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
wue 0:7b58cdacf811 164 }
wue 0:7b58cdacf811 165 else { // Out endpoint
wue 0:7b58cdacf811 166 // Set the out EP specific control settings
wue 0:7b58cdacf811 167 control |= (1 << 26); // CNAK
wue 0:7b58cdacf811 168 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
wue 0:7b58cdacf811 169
wue 0:7b58cdacf811 170 // Unmask the interrupt
wue 0:7b58cdacf811 171 OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
wue 0:7b58cdacf811 172 }
wue 0:7b58cdacf811 173 return true;
wue 0:7b58cdacf811 174 }
wue 0:7b58cdacf811 175
wue 0:7b58cdacf811 176 // read setup packet
wue 0:7b58cdacf811 177 void USBHAL::EP0setup(uint8_t *buffer) {
wue 0:7b58cdacf811 178 memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
wue 0:7b58cdacf811 179 }
wue 0:7b58cdacf811 180
wue 0:7b58cdacf811 181 void USBHAL::EP0readStage(void) {
wue 0:7b58cdacf811 182 }
wue 0:7b58cdacf811 183
wue 0:7b58cdacf811 184 void USBHAL::EP0read(void) {
wue 0:7b58cdacf811 185 }
wue 0:7b58cdacf811 186
wue 0:7b58cdacf811 187 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
wue 0:7b58cdacf811 188 uint32_t* buffer32 = (uint32_t *) buffer;
wue 0:7b58cdacf811 189 uint32_t length = rxFifoCount;
wue 0:7b58cdacf811 190 for (uint32_t i = 0; i < length; i += 4) {
wue 0:7b58cdacf811 191 buffer32[i >> 2] = OTG_FS->FIFO[0][0];
wue 0:7b58cdacf811 192 }
wue 0:7b58cdacf811 193
wue 0:7b58cdacf811 194 rxFifoCount = 0;
wue 0:7b58cdacf811 195 return length;
wue 0:7b58cdacf811 196 }
wue 0:7b58cdacf811 197
wue 0:7b58cdacf811 198 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
wue 0:7b58cdacf811 199 endpointWrite(0, buffer, size);
wue 0:7b58cdacf811 200 }
wue 0:7b58cdacf811 201
wue 0:7b58cdacf811 202 void USBHAL::EP0getWriteResult(void) {
wue 0:7b58cdacf811 203 }
wue 0:7b58cdacf811 204
wue 0:7b58cdacf811 205 void USBHAL::EP0stall(void) {
wue 0:7b58cdacf811 206 // If we stall the out endpoint here then we have problems transferring
wue 0:7b58cdacf811 207 // and setup requests after the (stalled) get device qualifier requests.
wue 0:7b58cdacf811 208 // TODO: Find out if this is correct behavior, or whether we are doing
wue 0:7b58cdacf811 209 // something else wrong
wue 0:7b58cdacf811 210 stallEndpoint(EP0IN);
wue 0:7b58cdacf811 211 // stallEndpoint(EP0OUT);
wue 0:7b58cdacf811 212 }
wue 0:7b58cdacf811 213
wue 0:7b58cdacf811 214 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
wue 0:7b58cdacf811 215 uint32_t epIndex = endpoint >> 1;
wue 0:7b58cdacf811 216 uint32_t size = (1 << 19) | // 1 packet
wue 0:7b58cdacf811 217 (maximumSize << 0); // Packet size
wue 0:7b58cdacf811 218 // if (endpoint == EP0OUT) {
wue 0:7b58cdacf811 219 size |= (1 << 29); // 1 setup packet
wue 0:7b58cdacf811 220 // }
wue 0:7b58cdacf811 221 OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
wue 0:7b58cdacf811 222 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
wue 0:7b58cdacf811 223 (1 << 26); // Clear NAK
wue 0:7b58cdacf811 224
wue 0:7b58cdacf811 225 epComplete &= ~(1 << endpoint);
wue 0:7b58cdacf811 226 return EP_PENDING;
wue 0:7b58cdacf811 227 }
wue 0:7b58cdacf811 228
wue 0:7b58cdacf811 229 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
wue 0:7b58cdacf811 230 if (!(epComplete & (1 << endpoint))) {
wue 0:7b58cdacf811 231 return EP_PENDING;
wue 0:7b58cdacf811 232 }
wue 0:7b58cdacf811 233
wue 0:7b58cdacf811 234 uint32_t* buffer32 = (uint32_t *) buffer;
wue 0:7b58cdacf811 235 uint32_t length = rxFifoCount;
wue 0:7b58cdacf811 236 for (uint32_t i = 0; i < length; i += 4) {
wue 0:7b58cdacf811 237 buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
wue 0:7b58cdacf811 238 }
wue 0:7b58cdacf811 239 rxFifoCount = 0;
wue 0:7b58cdacf811 240 *bytesRead = length;
wue 0:7b58cdacf811 241 return EP_COMPLETED;
wue 0:7b58cdacf811 242 }
wue 0:7b58cdacf811 243
wue 0:7b58cdacf811 244 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
wue 0:7b58cdacf811 245 uint32_t epIndex = endpoint >> 1;
wue 0:7b58cdacf811 246 OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
wue 0:7b58cdacf811 247 (size << 0); // Size of packet
wue 0:7b58cdacf811 248 OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
wue 0:7b58cdacf811 249 (1 << 26); // CNAK
wue 0:7b58cdacf811 250 OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
wue 0:7b58cdacf811 251
wue 0:7b58cdacf811 252 while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
wue 0:7b58cdacf811 253
wue 0:7b58cdacf811 254 for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
wue 0:7b58cdacf811 255 OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
wue 0:7b58cdacf811 256 }
wue 0:7b58cdacf811 257
wue 0:7b58cdacf811 258 epComplete &= ~(1 << endpoint);
wue 0:7b58cdacf811 259
wue 0:7b58cdacf811 260 return EP_PENDING;
wue 0:7b58cdacf811 261 }
wue 0:7b58cdacf811 262
wue 0:7b58cdacf811 263 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
wue 0:7b58cdacf811 264 if (epComplete & (1 << endpoint)) {
wue 0:7b58cdacf811 265 epComplete &= ~(1 << endpoint);
wue 0:7b58cdacf811 266 return EP_COMPLETED;
wue 0:7b58cdacf811 267 }
wue 0:7b58cdacf811 268
wue 0:7b58cdacf811 269 return EP_PENDING;
wue 0:7b58cdacf811 270 }
wue 0:7b58cdacf811 271
wue 0:7b58cdacf811 272 void USBHAL::stallEndpoint(uint8_t endpoint) {
wue 0:7b58cdacf811 273 if (endpoint & 0x1) { // In EP
wue 0:7b58cdacf811 274 OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
wue 0:7b58cdacf811 275 (1 << 21); // Stall
wue 0:7b58cdacf811 276 }
wue 0:7b58cdacf811 277 else { // Out EP
wue 0:7b58cdacf811 278 OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
wue 0:7b58cdacf811 279 OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
wue 0:7b58cdacf811 280 (1 << 21); // Stall
wue 0:7b58cdacf811 281 }
wue 0:7b58cdacf811 282 }
wue 0:7b58cdacf811 283
wue 0:7b58cdacf811 284 void USBHAL::unstallEndpoint(uint8_t endpoint) {
wue 0:7b58cdacf811 285
wue 0:7b58cdacf811 286 }
wue 0:7b58cdacf811 287
wue 0:7b58cdacf811 288 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
wue 0:7b58cdacf811 289 return false;
wue 0:7b58cdacf811 290 }
wue 0:7b58cdacf811 291
wue 0:7b58cdacf811 292 void USBHAL::remoteWakeup(void) {
wue 0:7b58cdacf811 293 }
wue 0:7b58cdacf811 294
wue 0:7b58cdacf811 295
wue 0:7b58cdacf811 296 void USBHAL::_usbisr(void) {
wue 0:7b58cdacf811 297 instance->usbisr();
wue 0:7b58cdacf811 298 }
wue 0:7b58cdacf811 299
wue 0:7b58cdacf811 300
wue 0:7b58cdacf811 301 void USBHAL::usbisr(void) {
wue 0:7b58cdacf811 302 if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
wue 0:7b58cdacf811 303 // Set SNAK bits
wue 0:7b58cdacf811 304 OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
wue 0:7b58cdacf811 305 OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
wue 0:7b58cdacf811 306 OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
wue 0:7b58cdacf811 307 OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
wue 0:7b58cdacf811 308
wue 0:7b58cdacf811 309 OTG_FS->DREGS.DIEPMSK = (1 << 0);
wue 0:7b58cdacf811 310
wue 0:7b58cdacf811 311 bufferEnd = 0;
wue 0:7b58cdacf811 312
wue 0:7b58cdacf811 313 // Set the receive FIFO size
wue 0:7b58cdacf811 314 OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
wue 0:7b58cdacf811 315 bufferEnd += rxFifoSize >> 2;
wue 0:7b58cdacf811 316
wue 0:7b58cdacf811 317 // Create the endpoints, and wait for setup packets on out EP0
wue 0:7b58cdacf811 318 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
wue 0:7b58cdacf811 319 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
wue 0:7b58cdacf811 320 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
wue 0:7b58cdacf811 321
wue 0:7b58cdacf811 322 OTG_FS->GREGS.GINTSTS = (1 << 12);
wue 0:7b58cdacf811 323 }
wue 0:7b58cdacf811 324
wue 0:7b58cdacf811 325 if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
wue 0:7b58cdacf811 326 uint32_t status = OTG_FS->GREGS.GRXSTSP;
wue 0:7b58cdacf811 327
wue 0:7b58cdacf811 328 uint32_t endpoint = (status & 0xF) << 1;
wue 0:7b58cdacf811 329 uint32_t length = (status >> 4) & 0x7FF;
wue 0:7b58cdacf811 330 uint32_t type = (status >> 17) & 0xF;
wue 0:7b58cdacf811 331
wue 0:7b58cdacf811 332 rxFifoCount = length;
wue 0:7b58cdacf811 333
wue 0:7b58cdacf811 334 if (type == 0x6) {
wue 0:7b58cdacf811 335 // Setup packet
wue 0:7b58cdacf811 336 for (uint32_t i=0; i<length; i+=4) {
wue 0:7b58cdacf811 337 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
wue 0:7b58cdacf811 338 }
wue 0:7b58cdacf811 339 rxFifoCount = 0;
wue 0:7b58cdacf811 340 }
wue 0:7b58cdacf811 341
wue 0:7b58cdacf811 342 if (type == 0x4) {
wue 0:7b58cdacf811 343 // Setup complete
wue 0:7b58cdacf811 344 EP0setupCallback();
wue 0:7b58cdacf811 345 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
wue 0:7b58cdacf811 346 }
wue 0:7b58cdacf811 347
wue 0:7b58cdacf811 348 if (type == 0x2) {
wue 0:7b58cdacf811 349 // Out packet
wue 0:7b58cdacf811 350 if (endpoint == EP0OUT) {
wue 0:7b58cdacf811 351 EP0out();
wue 0:7b58cdacf811 352 }
wue 0:7b58cdacf811 353 else {
wue 0:7b58cdacf811 354 epComplete |= (1 << endpoint);
wue 0:7b58cdacf811 355 if ((instance->*(epCallback[endpoint - 2]))()) {
wue 0:7b58cdacf811 356 epComplete &= (1 << endpoint);
wue 0:7b58cdacf811 357 }
wue 0:7b58cdacf811 358 }
wue 0:7b58cdacf811 359 }
wue 0:7b58cdacf811 360
wue 0:7b58cdacf811 361 for (uint32_t i=0; i<rxFifoCount; i+=4) {
wue 0:7b58cdacf811 362 (void) OTG_FS->FIFO[0][0];
wue 0:7b58cdacf811 363 }
wue 0:7b58cdacf811 364 OTG_FS->GREGS.GINTSTS = (1 << 4);
wue 0:7b58cdacf811 365 }
wue 0:7b58cdacf811 366
wue 0:7b58cdacf811 367 if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
wue 0:7b58cdacf811 368 // Loop through the in endpoints
wue 0:7b58cdacf811 369 for (uint32_t i=0; i<4; i++) {
wue 0:7b58cdacf811 370 if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
wue 0:7b58cdacf811 371
wue 0:7b58cdacf811 372 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
wue 0:7b58cdacf811 373 // If the Tx FIFO is empty on EP0 we need to send a further
wue 0:7b58cdacf811 374 // packet, so call EP0in()
wue 0:7b58cdacf811 375 if (i == 0) {
wue 0:7b58cdacf811 376 EP0in();
wue 0:7b58cdacf811 377 }
wue 0:7b58cdacf811 378 // Clear the interrupt
wue 0:7b58cdacf811 379 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
wue 0:7b58cdacf811 380 // Stop firing Tx empty interrupts
wue 0:7b58cdacf811 381 // Will get turned on again if another write is called
wue 0:7b58cdacf811 382 OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
wue 0:7b58cdacf811 383 }
wue 0:7b58cdacf811 384
wue 0:7b58cdacf811 385 // If the transfer is complete
wue 0:7b58cdacf811 386 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
wue 0:7b58cdacf811 387 epComplete |= (1 << (1 + (i << 1)));
wue 0:7b58cdacf811 388 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
wue 0:7b58cdacf811 389 }
wue 0:7b58cdacf811 390 }
wue 0:7b58cdacf811 391 }
wue 0:7b58cdacf811 392 OTG_FS->GREGS.GINTSTS = (1 << 18);
wue 0:7b58cdacf811 393 }
wue 0:7b58cdacf811 394
wue 0:7b58cdacf811 395 if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
wue 0:7b58cdacf811 396 SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
wue 0:7b58cdacf811 397 OTG_FS->GREGS.GINTSTS = (1 << 3);
wue 0:7b58cdacf811 398 }
wue 0:7b58cdacf811 399 }
wue 0:7b58cdacf811 400
wue 0:7b58cdacf811 401
wue 0:7b58cdacf811 402 #endif