max14724.h

00001 /******************************************************************//**
00002 * @file max14724.h
00003 *
00004 * @author Wilson Tang
00005 *
00006 * @version 1.0
00007 *
00008 * Started: 22APR15
00009 *
00010 * Updated: 
00011 *
00012 * @brief Header file for MAX14724 class
00013 * 
00014 * http://www.maximintegrated.com/max14724
00015 *
00016 ***********************************************************************
00017 *
00018 * @copyright 
00019 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
00020 *
00021 * Permission is hereby granted, free of charge, to any person obtaining a
00022 * copy of this software and associated documentation files (the "Software"),
00023 * to deal in the Software without restriction, including without limitation
00024 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00025 * and/or sell copies of the Software, and to permit persons to whom the
00026 * Software is furnished to do so, subject to the following conditions:
00027 *
00028 * The above copyright notice and this permission notice shall be included
00029 * in all copies or substantial portions of the Software.
00030 *
00031 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00032 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00033 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00034 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00035 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00036 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00037 * OTHER DEALINGS IN THE SOFTWARE.
00038 *
00039 * Except as contained in this notice, the name of Maxim Integrated
00040 * Products, Inc. shall not be used except as stated in the Maxim Integrated
00041 * Products, Inc. Branding Policy.
00042 *
00043 * The mere transfer of this software does not imply any licenses
00044 * of trade secrets, proprietary technology, copyrights, patents,
00045 * trademarks, maskwork rights, or any other form of intellectual
00046 * property whatsoever. Maxim Integrated Products, Inc. retains all
00047 * ownership rights.
00048 **********************************************************************/
00049 
00050 
00051 #ifndef MAX14724_H
00052 #define MAX14724_H
00053 
00054 
00055 #include "mbed.h"
00056 
00057 
00058 /******************************************************************//**
00059 * Max14724 Class
00060 **********************************************************************/
00061 class Max14724 : public I2C
00062 {
00063     uint8_t w_adrs, r_adrs;
00064     
00065     public:
00066     
00067         /**
00068         * max14724_i2c_adrs_t - enumerated MAX14724 I2C Addresses
00069         */
00070         typedef enum
00071         {
00072             MAX14724_I2C_ADRS0 = 0x74,
00073             MAX14724_I2C_ADRS1
00074         }max14724_i2c_adrs_t;
00075         
00076         
00077         /**
00078         * max14724_regs_t - enumerated MAX14724 register addresses
00079         */
00080         typedef enum
00081         {
00082             DIR0,         //Switches 8A–1A direct read/write access
00083             DIR1,         //Switches 8B–1B direct read/write access
00084             DIR2,         //Switches 8C–1C direct read/write access
00085             DIR3,         //Switches 8D–1D direct read/write access
00086             SHDW0 = 0x10, //Switches 8A–1A shadow read/write access
00087             SHDW1,        //Switches 8B–1B shadow read/write access
00088             SHDW2,        //Switches 8C–1C shadow read/write access
00089             SHDW3,        //Switches 8D–1D shadow read/write access
00090             CMD0,         //Set mux A and B command (reads 0x00)
00091             CMD1          //Set mux C and D command (reads 0x00)
00092         }max14724_regs_t;
00093         
00094         
00095         /**
00096         * max14724_cmds_t - enumerated MAX14724 commands
00097         */
00098         typedef enum
00099         {
00100             ENABLE_SW01,     //enables sw1 on bank only
00101             ENABLE_SW02,     //enables sw2 on bank only
00102             ENABLE_SW03,     //enables sw3 on bank only
00103             ENABLE_SW04,     //enables sw4 on bank only
00104             ENABLE_SW05,     //enables sw5 on bank only
00105             ENABLE_SW06,     //enables sw6 on bank only
00106             ENABLE_SW07,     //enables sw7 on bank only
00107             ENABLE_SW08,     //enables sw8 on bank only
00108             DISABLE_BANK,    //opens all switches on bank
00109             COPY_SHADOW,     //copies both shadow registers for bank
00110             NO_CHANGE
00111         }max14724_cmds_t;
00112         
00113         
00114         /**
00115         * max14724_sw_t - enumerated MAX14724 switch bitmasks
00116         */
00117         typedef enum
00118         {
00119             SW01 = (1 << 0),
00120             SW02 = (1 << 1),
00121             SW03 = (1 << 2),
00122             SW04 = (1 << 3),
00123             SW05 = (1 << 4),
00124             SW06 = (1 << 5),
00125             SW07 = (1 << 6),
00126             SW08 = (1 << 7)
00127         }max14724_sw_t;
00128         
00129         
00130         /**********************************************************//**
00131         * Constructor for Max14724 Class
00132         *
00133         * On Entry:
00134         *     @param[in] sda - sda pin of I2C bus
00135         *     @param[in] scl - scl pin of I2C bus
00136         *     @param[in] i2c_adrs - 7-bit slave address of MAX14724
00137         *
00138         * On Exit:
00139         *    @return none
00140         *
00141         * Example:
00142         * @code
00143         * 
00144         * //declare mux object
00145         * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0); 
00146         *
00147         * @endcode
00148         **************************************************************/
00149         Max14724(PinName sda, PinName scl, max14724_i2c_adrs_t i2c_adrs);
00150         
00151 
00152         /******************************************************************//**
00153         * Writes given commands to CMD_A, CMD_B, CMD_C, and CMD_D
00154         *
00155         * On Entry:
00156         *     @param[in] cmdA - command for CMD_A
00157         *     @param[in] cmdB - command for CMD_B
00158         *     @param[in] cmdC - command for CMD_C
00159         *     @param[in] cmdD - command for CMD_D
00160         *
00161         * On Exit:
00162         *     @return return value = 0 on success, non-0 on failure
00163         *
00164         * Example:
00165         * @code
00166         *
00167         * //declare mux object
00168         * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0); 
00169         *
00170         * uint16_t rtn_val;  
00171         *
00172         * rtn_val = mux.wrt_cmd_registers(DISABLE_BANK, DISABLE_BANK, DISABLE_BANK, DISABLE_BANK);
00173         * 
00174         * @endcode
00175         **********************************************************************/
00176         uint16_t wrt_cmd_registers(max14724_cmds_t cmdA, max14724_cmds_t cmdB, max14724_cmds_t cmdC, max14724_cmds_t cmdD);
00177 
00178 
00179         /******************************************************************//**
00180         * Writes bankA, bankB, bankC, and bankD to coresponding shadow registers
00181         *
00182         * On Entry:
00183         *     @param[in] bankA - binary representation of switch states
00184         *     @param[in] bankB - binary representation of switch states
00185         *     @param[in] bankC - binary representation of switch states
00186         *     @param[in] bankD - binary representation of switch states
00187         *
00188         * On Exit:
00189         *     @return return value = 0 on success, non-0 on failure
00190         *
00191         * Example:
00192         * @code
00193         *
00194         * //declare mux object
00195         * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0); 
00196         *
00197         * uint16_t bankA = (SW03 | SW02); //example only
00198         * uint16_t bankB = (SW05 | SW04);
00199         * uint16_t bankC = SW07;
00200         * uint16_t bankD = SW08;
00201         * uint16_t rtn_val;  
00202         *  
00203         * //wite shadow registers
00204         * rtn_val = mux.wrt_shadow_registers(bankA, bankB, bankC, bankD);
00205         *
00206         * @endcode
00207         **********************************************************************/
00208         uint16_t wrt_shadow_registers(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD);
00209 
00210 
00211         /******************************************************************//**
00212         * Writes bankA, bankB, bankC, and bankD to coresponding direct access registers 
00213         *
00214         * On Entry:
00215         *     @param[in] bankA - binary representation of switch states
00216         *     @param[in] bankB - binary representation of switch states
00217         *     @param[in] bankC - binary representation of switch states
00218         *     @param[in] bankD - binary representation of switch states
00219         *
00220         * On Exit:
00221         *     @return return value = 0 on success, non-0 on failure
00222         *
00223         * Example:
00224         * @code  
00225         *
00226         * //declare mux object
00227         * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);   
00228         *
00229         * uint16_t bankA = (SW12 | SW02); //example only
00230         * uint16_t bankB = (SW11 | SW01);
00231         * uint16_t bankC = SW07;
00232         * uint16_t bankD = SW08;
00233         * uint16_t rtn_val;  
00234         *  
00235         * //wite shadow registers
00236         * rtn_val = mux.wrt_dir_registers(bankA, bankB, bankC, bankD);
00237         *
00238         * @endcode
00239         **********************************************************************/
00240         uint16_t wrt_dir_registers(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD);
00241 
00242 
00243         /******************************************************************//**
00244         * Writes bankA, bankB, bankC, and bankD to coresponding shadow register and then 
00245         * issues copy command for both banks
00246         *
00247         * On Entry:
00248         *     @param[in] bankA - binary representation of switch states
00249         *     @param[in] bankB - binary representation of switch states
00250         *     @param[in] bankC - binary representation of switch states
00251         *     @param[in] bankD - binary representation of switch states
00252         *
00253         * On Exit:
00254         *     @return return value = 0 on success, non-0 on failure
00255         *
00256         * Example:
00257         * @code  
00258         *
00259         * //declare mux object
00260         * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);   
00261         *
00262         * uint16_t bankA = (SW12 | SW02); //example only
00263         * uint16_t bankB = (SW11 | SW01);
00264         * uint16_t bankC = SW07;
00265         * uint16_t bankD = SW08;
00266         * uint16_t rtn_val;  
00267         *  
00268         * //wite shadow registers
00269         * rtn_val = mux.set_switches(bankA, bankB, bankC, bankD);
00270         *
00271         * @endcode
00272         **********************************************************************/
00273         uint16_t set_switches(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD);
00274 
00275 
00276         /**********************************************************//**
00277         * Reads data from direct access registers starting at DIR0 and 
00278         * stores it in byte array pointed at by 'data'
00279         *
00280         * On Entry:
00281         *     @param[in] data - pointer to byte array for storing data
00282         *
00283         * On Exit:
00284         *     @param[out] data - data buffer now contains data read 
00285         *                        from dir registers
00286         *     @return return value = 0 on success, non-0 on failure
00287         *
00288         * Example:
00289         * @code
00290         *
00291         * //declare mux object
00292         * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0); 
00293         *
00294         * uint16_t rtn_val;  
00295         * uint8_t data[4];
00296         * 
00297         * //read direct access registers
00298         * rtn_val = mux.rd_dir_registers(data);
00299         *
00300         * @endcode
00301         **********************************************************************/
00302         uint16_t rd_dir_registers(uint8_t* data);
00303 
00304 
00305         /**********************************************************//**
00306         * Reads data from shadow registers starting at SHDW0 and stores 
00307         * it in byte array pointed at by 'data'
00308         *
00309         * On Entry:
00310         *     @param[in] data - pointer to byte array for storing data
00311         *
00312         * On Exit:
00313         *     @param[out] data - data buffer now contains data read 
00314         *                        from shadow registers
00315         *     @return return value = 0 on success, non-0 on failure
00316         *
00317         * Example:
00318         * @code
00319         *
00320         * //declare mux object
00321         * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0); 
00322         *
00323         * uint16_t rtn_val;  
00324         * uint8_t data[4];
00325         * 
00326         * //read shadow registers
00327         * rtn_val = mux.rd_shadow_registers(data);
00328         *
00329         * @endcode
00330         **************************************************************/      
00331         uint16_t rd_shadow_registers(uint8_t* data);  
00332 };
00333                                   
00334                                           
00335 #endif /* MAX14724_H*/