max14724.cpp

00001 /******************************************************************//**
00002 * @file max14724.cpp
00003 *
00004 * @author Wilson Tang
00005 *
00006 * @version 1.0
00007 *
00008 * Started: 22APR15
00009 *
00010 * Updated:
00011 *
00012 * @brief Source file for MAX14724 class
00013 *
00014 * http://www.maximintegrated.com/max14724
00015 *
00016 ***********************************************************************
00017 *
00018 * @copyright
00019 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
00020 *
00021 * Permission is hereby granted, free of charge, to any person obtaining a
00022 * copy of this software and associated documentation files (the "Software"),
00023 * to deal in the Software without restriction, including without limitation
00024 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00025 * and/or sell copies of the Software, and to permit persons to whom the
00026 * Software is furnished to do so, subject to the following conditions:
00027 *
00028 * The above copyright notice and this permission notice shall be included
00029 * in all copies or substantial portions of the Software.
00030 *
00031 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00032 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00033 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00034 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
00035 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00036 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00037 * OTHER DEALINGS IN THE SOFTWARE.
00038 *
00039 * Except as contained in this notice, the name of Maxim Integrated
00040 * Products, Inc. shall not be used except as stated in the Maxim Integrated
00041 * Products, Inc. Branding Policy.
00042 *
00043 * The mere transfer of this software does not imply any licenses
00044 * of trade secrets, proprietary technology, copyrights, patents,
00045 * trademarks, maskwork rights, or any other form of intellectual
00046 * property whatsoever. Maxim Integrated Products, Inc. retains all
00047 * ownership rights.
00048 **********************************************************************/
00049 
00050 
00051 #include "max14724.h"
00052 
00053 
00054 /**********************************************************//**
00055 * Constructor for Max14724 Class
00056 *
00057 * On Entry:
00058 *     @param[in] sda - sda pin of I2C bus
00059 *     @param[in] scl - scl pin of I2C bus
00060 *     @param[in] i2c_adrs - 7-bit slave address of MAX14724
00061 *
00062 * On Exit:
00063 *    @return none
00064 *
00065 * Example:
00066 * @code
00067 *
00068 * //declare mux object
00069 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
00070 *
00071 * @endcode
00072 **************************************************************/
00073 Max14724::Max14724(PinName sda, PinName scl, max14724_i2c_adrs_t i2c_adrs) :
00074     I2C(sda, scl)
00075 {
00076     w_adrs = (i2c_adrs << 1);
00077     r_adrs = (w_adrs | 0x01);
00078 }
00079 
00080 
00081 /******************************************************************//**
00082 * Writes given commands to CMD_A, CMD_B, CMD_C, and CMD_D
00083 *
00084 * On Entry:
00085 *     @param[in] cmdA - command for CMD_A
00086 *     @param[in] cmdB - command for CMD_B
00087 *     @param[in] cmdC - command for CMD_C
00088 *     @param[in] cmdD - command for CMD_D
00089 *
00090 * On Exit:
00091 *     @return return value = 0 on success, non-0 on failure
00092 *
00093 * Example:
00094 * @code
00095 *
00096 * //declare mux object
00097 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
00098 *
00099 * uint16_t rtn_val;
00100 *
00101 * rtn_val = mux.wrt_cmd_registers(DISABLE_BANK, DISABLE_BANK, DISABLE_BANK, DISABLE_BANK);
00102 *
00103 * @endcode
00104 **********************************************************************/
00105 uint16_t Max14724::wrt_cmd_registers(max14724_cmds_t cmdA, max14724_cmds_t cmdB, max14724_cmds_t cmdC, max14724_cmds_t cmdD)
00106 {
00107     uint8_t data[3];
00108     uint8_t data_length = 0;
00109     uint16_t rtn_val = 1;
00110 
00111     //build packet
00112     data[data_length++] = CMD0;
00113     data[data_length++] = (cmdB & 0x0F) << 4 | (cmdA & 0x0F);
00114     data[data_length++] = (cmdD & 0x0F) << 4 | (cmdC & 0x0F);
00115 
00116     rtn_val = write(w_adrs,(const char*) data, data_length);
00117 
00118     return(rtn_val);
00119 }
00120 
00121 
00122 /******************************************************************//**
00123 * Writes bankA, bankB, bankC, and bankD to coresponding shadow registers
00124 *
00125 * On Entry:
00126 *     @param[in] bankA - binary representation of switch states
00127 *     @param[in] bankB - binary representation of switch states
00128 *     @param[in] bankC - binary representation of switch states
00129 *     @param[in] bankD - binary representation of switch states
00130 *
00131 * On Exit:
00132 *     @return return value = 0 on success, non-0 on failure
00133 *
00134 * Example:
00135 * @code
00136 *
00137 * //declare mux object
00138 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
00139 *
00140 * uint16_t bankA = (SW03 | SW02); //example only
00141 * uint16_t bankB = (SW05 | SW04);
00142 * uint16_t bankC = SW07;
00143 * uint16_t bankD = SW08;
00144 * uint16_t rtn_val;
00145 *
00146 * //wite shadow registers
00147 * rtn_val = mux.wrt_shadow_registers(bankA, bankB, bankC, bankD);
00148 *
00149 * @endcode
00150 **********************************************************************/
00151 uint16_t Max14724::wrt_shadow_registers(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD)
00152 {
00153     uint8_t data[5];
00154     uint8_t data_length = 0;
00155     uint16_t rtn_val = 1;
00156 
00157     data[data_length++] = SHDW0;
00158     data[data_length++] = (bankA & 0x00FF);
00159     data[data_length++] = (bankB & 0x00FF);
00160     data[data_length++] = (bankC & 0x00FF);
00161     data[data_length++] = (bankD & 0x00FF);
00162 
00163     rtn_val = write(w_adrs,(const char*) data, data_length);
00164 
00165     return(rtn_val);
00166 }
00167 
00168 
00169 /******************************************************************//**
00170 * Writes bankA, bankB, bankC, and bankD to coresponding shadow registers
00171 *
00172 * On Entry:
00173 *     @param[in] bankA - binary representation of switch states
00174 *     @param[in] bankB - binary representation of switch states
00175 *     @param[in] bankC - binary representation of switch states
00176 *     @param[in] bankD - binary representation of switch states
00177 *
00178 * On Exit:
00179 *     @return return value = 0 on success, non-0 on failure
00180 *
00181 * Example:
00182 * @code
00183 *
00184 * //declare mux object
00185 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
00186 *
00187 * uint8_t bankA = (SW03 | SW02); //example only
00188 * uint8_t bankB = (SW05 | SW04);
00189 * uint8_t bankC = SW07;
00190 * uint8_t bankD = SW08;
00191 * uint16_t rtn_val;
00192 *
00193 * //wite shadow registers
00194 * rtn_val = mux.wrt_shadow_registers(bankA, bankB, bankC, bankD);
00195 *
00196 * @endcode
00197 **********************************************************************/
00198 uint16_t Max14724::wrt_dir_registers(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD)
00199 {
00200     uint8_t data[5];
00201     uint8_t data_length = 0;
00202     uint16_t rtn_val = 1;
00203 
00204     data[data_length++] = DIR0;
00205     data[data_length++] = (bankA & 0x00FF);
00206     data[data_length++] = (bankB & 0x00FF);
00207     data[data_length++] = (bankC & 0x00FF);
00208     data[data_length++] = (bankD & 0x00FF);
00209 
00210     rtn_val = write(w_adrs,(const char*) data, data_length);
00211 
00212     return(rtn_val);
00213 }
00214 
00215 
00216 /******************************************************************//**
00217 * Writes bankA, bankB, bankC, and bankD to coresponding shadow register and then
00218 * issues copy command for both banks
00219 *
00220 * On Entry:
00221 *     @param[in] bankA - binary representation of switch states
00222 *     @param[in] bankB - binary representation of switch states
00223 *     @param[in] bankC - binary representation of switch states
00224 *     @param[in] bankD - binary representation of switch states
00225 *
00226 * On Exit:
00227 *     @return return value = 0 on success, non-0 on failure
00228 *
00229 * Example:
00230 * @code
00231 *
00232 * //declare mux object
00233 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
00234 *
00235 * uint16_t bankA = (SW12 | SW02); //example only
00236 * uint16_t bankB = (SW11 | SW01);
00237 * uint16_t bankC = SW07;
00238 * uint16_t bankD = SW08;
00239 * uint16_t rtn_val;
00240 *
00241 * //wite shadow registers
00242 * rtn_val = mux.set_switches(bankA, bankB, bankC, bankD);
00243 *
00244 * @endcode
00245 **********************************************************************/
00246 uint16_t Max14724::set_switches(uint8_t bankA, uint8_t bankB, uint8_t bankC, uint8_t bankD)
00247 {
00248     uint8_t data[7];
00249     uint8_t data_length = 0;
00250     uint16_t rtn_val = 1;
00251 
00252     data[data_length++] = SHDW0;
00253     data[data_length++] = (bankA & 0x00FF);
00254     data[data_length++] = (bankB & 0x00FF);
00255     data[data_length++] = (bankC & 0x00FF);
00256     data[data_length++] = (bankD & 0x00FF);
00257     data[data_length++] = ((COPY_SHADOW << 4) | COPY_SHADOW);
00258     data[data_length++] = ((COPY_SHADOW << 4) | COPY_SHADOW);
00259 
00260     rtn_val = write(w_adrs,(const char*) data, data_length);
00261 
00262     return(rtn_val);
00263 }
00264 
00265 
00266 /**********************************************************//**
00267 * Reads data from direct access registers starting at DIR0 and
00268 * stores it in byte array pointed at by 'data'
00269 *
00270 * On Entry:
00271 *     @param[in] data - pointer to byte array for storing data
00272 *
00273 * On Exit:
00274 *     @param[out] data - data buffer now contains data read
00275 *                        from dir registers
00276 *     @return return value = 0 on success, non-0 on failure
00277 *
00278 * Example:
00279 * @code
00280 *
00281 * //declare mux object
00282 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
00283 *
00284 * uint16_t rtn_val;
00285 * uint8_t data[4];
00286 *
00287 * //read direct access registers
00288 * rtn_val = mux.rd_dir_registers(data);
00289 *
00290 * @endcode
00291 **********************************************************************/
00292 uint16_t Max14724::rd_dir_registers(uint8_t* data)
00293 {
00294     uint16_t rtn_val = 1;
00295 
00296     data[0] = DIR0;
00297 
00298     rtn_val = write(w_adrs,(const char*) data, 1);
00299 
00300     if(!rtn_val) {
00301         rtn_val = read(r_adrs,(char*) data, 4);
00302     }
00303 
00304     return(rtn_val);
00305 }
00306 
00307 
00308 /**********************************************************//**
00309 * Reads data from shadow registers starting at SHDW0 and stores
00310 * it in byte array pointed at by 'data'
00311 *
00312 * On Entry:
00313 *     @param[in] data - pointer to byte array for storing data
00314 *
00315 * On Exit:
00316 *     @param[out] data - data buffer now contains data read
00317 *                        from shadow registers
00318 *     @return return value = 0 on success, non-0 on failure
00319 *
00320 * Example:
00321 * @code
00322 *
00323 * //declare mux object
00324 * Max14724 mux(D14, D15, MAX14724_I2C_ADRS0);
00325 *
00326 * uint16_t rtn_val;
00327 * uint8_t data[4];
00328 *
00329 * //read shadow registers
00330 * rtn_val = mux.rd_shadow_registers(data);
00331 *
00332 * @endcode
00333 **************************************************************/
00334 uint16_t Max14724::rd_shadow_registers(uint8_t* data)
00335 {
00336     uint16_t rtn_val = 1;
00337 
00338     data[0] = SHDW0;
00339 
00340     rtn_val = write(w_adrs,(const char*) data, 1);
00341 
00342     if(!rtn_val) {
00343         rtn_val = read(r_adrs,(char*) data, 4);
00344     }
00345 
00346     return(rtn_val);
00347 }