Revision 410:a95c696104d3, committed 2014-11-19

Comitter:

mbed_official

Date:

Wed Nov 19 09:00:07 2014 +0000

Parent:

409:4dd1c1251ba6

Child:

411:276cd45a8c73

Commit message:

Synchronized with git revision f364b76d2fc9a89ffad67121dc2a131647263935

Full URL: https://github.com/mbedmicro/mbed/commit/f364b76d2fc9a89ffad67121dc2a131647263935/

Targets: RZ_A1H - Fixed a bug of serial interrupt

Changed in this revision

--- a/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c	Wed Nov 19 08:45:06 2014 +0000
+++ b/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c	Wed Nov 19 09:00:07 2014 +0000
@@ -73,6 +73,16 @@
 extern uint32_t Image$$ZI_DATA$$Base;
 extern uint32_t Image$$TTB$$ZI$$Base;
 
+extern uint32_t Image$$VECTORS$$Limit;
+extern uint32_t Image$$RO_DATA$$Limit;
+extern uint32_t Image$$RW_DATA$$Limit;
+extern uint32_t Image$$ZI_DATA$$Limit;
+
+#define	VECTORS_SIZE	(((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
+#define	RO_DATA_SIZE	(((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
+#define	RW_DATA_SIZE	(((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
+#define	ZI_DATA_SIZE	(((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
+
 static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
 static uint32_t Sect_Normal_NC;  //non-shareable, non-executable, rw, domain 0, base addr 0
 static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
@@ -133,11 +143,11 @@
     __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1      , 49, Sect_Device_RW);
 
     //Define Image
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, 1, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE  , 10, Sect_Normal_NC);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
 
     /* Set location of level 1 page table
     ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c	Wed Nov 19 08:45:06 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c	Wed Nov 19 09:00:07 2014 +0000
@@ -31,7 +31,9 @@
     {P1_9,  AN1, 1},
     {P1_10, AN2, 1},
     {P1_11, AN3, 1},
+        {P1_12, AN3, 1},
     {P1_13, AN5, 1},
+        {P1_14, AN5, 1},
     {P1_15, AN7, 1},
     {NC,    NC,     0}
 };
@@ -56,19 +58,25 @@
     CPGSTBCR3 &= ~(1 << 1);
     CPGSTBCR6 &= ~(1 << 7);
 
-    // 000_0 000_1 11_00 0_xxx
+    // 000_0 000_1 00_00 0_xxx
     // 15: ADFlag 14: IntEn 13: start, [12:9] Triger..0
     //    [8:6] CLK 100 :: 12-bit 1054tclk
     //    [5:3] scanmode 000 :: single mode
     //    [2:0] channel select
-    ADCADCSR = 0x0100 | (obj->adc&0xf);
+    ADCADCSR = 0x01c0 ;
     
-    pinmap_pinout(pin, PinMap_ADC);
+    for (int i = 0; i< sizeof(PinMap_ADC)/sizeof(PinMap); i++) {
+        pinmap_pinout(PinMap_ADC[i].pin, PinMap_ADC);
+    }
+
+    //pinmap_pinout(pin, PinMap_ADC);
 }
 
 static inline uint32_t adc_read(analogin_t *obj) {
     // Select the appropriate channel and start conversion
-    ADCADCSR |= (1 << 13 | (obj->adc&0xf));
+    
+    ADCADCSR &= 0xfff8;
+    ADCADCSR |= (1 << 13 | (obj->adc&0x7));
     
     // Repeatedly get the sample data until DONE bit
 #define nothing

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c	Wed Nov 19 09:00:07 2014 +0000
@@ -0,0 +1,158 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+
+#include "gpio_irq_api.h"
+#include "intc_iodefine.h"
+#include "pinmap.h"
+#include "cmsis.h"
+
+#define CHANNEL_NUM     8
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+static const int nIRQn_h = 32;
+extern PinName gpio_multi_guard;
+
+enum {
+    IRQ0,IRQ1, 
+    IRQ2,IRQ3, 
+    IRQ4,IRQ5, 
+    IRQ6,IRQ7, 
+
+} IRQNo;
+
+static const PinMap PinMap_IRQ[] = {
+    {P1_0,  IRQ0, 4}, {P1_1,  IRQ1, 4}, {P1_2,  IRQ2, 4},
+    {P1_3,  IRQ3, 4}, {P1_5,  IRQ5, 4}, {P1_7,  IRQ7, 4},
+    {P1_8,  IRQ2, 3}, {P1_9,  IRQ3, 3}, {P1_10, IRQ4, 3},
+    {P1_11, IRQ5, 3}, // 9
+    {P2_0,  IRQ5, 6}, {P2_13, IRQ7, 8}, {P2_14, IRQ0, 8},
+    {P2_15, IRQ1, 8}, // 13
+    {P3_0,  IRQ2, 3}, {P3_3,  IRQ4, 3}, // 15
+    {P4_8,  IRQ0, 8}, {P4_9,  IRQ1, 8}, {P4_10, IRQ2, 8},
+    {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8},
+    {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 23
+    {P5_6,  IRQ6, 6}, {P5_8,  IRQ0, 2}, {P5_9,  IRQ2, 4}, // 26
+    {P6_0,  IRQ5, 6}, {P6_1,  IRQ4, 4}, {P6_2,  IRQ7, 4},
+    {P6_3,  IRQ2, 4}, {P6_4,  IRQ3, 4}, {P6_8,  IRQ0, 8},
+    {P6_9,  IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8},
+    {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8},
+    {P6_15, IRQ7, 8}, // 39
+    {P7_8,  IRQ1, 8}, {P7_9,  IRQ0, 8}, {P7_10, IRQ2, 8},
+    {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8},
+    {P7_14, IRQ6, 8}, // 46
+    {P8_2,  IRQ0, 5}, {P8_3,  IRQ1, 6}, {P8_7,  IRQ5, 4},
+    {P9_1,  IRQ0, 4}, // 50
+    {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 52
+
+    {NC,    NC,     0}
+};
+
+static gpio_irq_event irq_event;
+
+static void handle_interrupt_in(void) {
+    int i;
+    uint16_t irqs;
+    int irq_num;
+    
+    irqs = INTCIRQRR;
+    for(i = 0; i< 8; i++) {
+        if (channel_ids[i] && (irqs & (1 << i))) {
+            irq_handler(channel_ids[i], irq_event);
+            INTCIRQRR &= ~(1 << i);
+            irq_num = i;
+        }
+    }
+    GIC_EndInterrupt((IRQn_Type)(nIRQn_h + irq_num));
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+    int shift;
+    if (pin == NC) return -1;
+
+    obj->ch = pinmap_peripheral(pin, PinMap_IRQ);
+    obj->pin = (int)pin ;
+    obj->port = (int)id ;
+    
+    shift = obj->ch*2;
+    channel_ids[obj->ch] = id;
+    irq_handler = handler;
+    
+    pinmap_pinout(pin, PinMap_IRQ);
+    gpio_multi_guard = pin;           /* Set multi guard */
+
+    // INTC settings
+    InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))handle_interrupt_in);
+    INTCICR1 &= ~(0x3 << shift);
+    INTCICR1 |= (0x3 << shift);
+    irq_event = IRQ_RISE;
+    GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
+    GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
+    __enable_irq();
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+    channel_ids[obj->ch] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+    int shift = obj->ch*2;
+    uint16_t val = event == IRQ_RISE ? 2 : 
+                   event == IRQ_FALL ? 1 : 0;
+    uint16_t work_icr_val;
+    uint16_t work_irqrr_val;
+    
+    /* check edge interrupt setting */
+    work_icr_val = INTCICR1;
+    if (enable == 1) {
+        /* Set interrupt serect */
+        work_icr_val |=  (val << shift);
+    } else {
+        /* Clear interrupt serect */
+        work_icr_val &= ~(val << shift);
+    }
+    
+    if ((work_icr_val & (3 << shift)) == 0) {
+        /* No edge interrupt setting */
+        GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
+        /* Clear Interrupt flags */
+        work_irqrr_val = INTCIRQRR;
+        INTCIRQRR = (work_irqrr_val & ~(1 << obj->ch));
+    } else {
+        /* Edge interrupt setting */
+        if ((work_icr_val & (3 << shift)) == 2) {
+            /* Setting of rising edge */
+            irq_event = IRQ_RISE;
+        } else { 
+            /* Setting of falling edge of both edge */
+            irq_event = IRQ_FALL;
+        }
+        GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
+    }
+    INTCICR1  = work_icr_val;
+}
+
+void gpio_irq_enable(gpio_irq_t *obj) {
+    GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+}
+
+void gpio_irq_disable(gpio_irq_t *obj) {
+    GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+}
+

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c	Wed Nov 19 08:45:06 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c	Wed Nov 19 09:00:07 2014 +0000
@@ -61,17 +61,51 @@
     while (!(i2c_status(obj) & (1 << 5))) ;
 }
 
+static void i2c_reg_reset(i2c_t *obj) {
+    // full reset
+    REG(CR1.UINT8[0]) &= ~(1 << 7); // CR1.ICE off
+    REG(CR1.UINT8[0]) |=  (1 << 6); // CR1.IICRST on
+    REG(CR1.UINT8[0]) |=  (1 << 7); // CR1.ICE on
+
+    REG(MR1.UINT8[0])  =  0x08;  // P_phi /8  9bit (including Ack)
+    REG(SER.UINT8[0])  =  0x00;  // no slave addr enabled
+
+    // set default frequency at 100k
+    i2c_frequency(obj, 100000);
+
+    REG(MR2.UINT8[0])  =  0x07;
+    REG(MR3.UINT8[0])  =  0x00;
+
+    REG(FER.UINT8[0])  =  0x72;  // SCLE, NFE enabled, TMOT
+    REG(IER.UINT8[0])  =  0x00;  // no interrupt
+
+    REG(CR1.UINT32) &= ~(1 << 6); // CR1.IICRST negate reset
+}
+
 // Wait until the Trans Data Empty (TDRE) is set
 static int i2c_wait_TDRE(i2c_t *obj) {
     int timeout = 0;
 
     while (!(i2c_status(obj) & (1 << 7))) {
+        timeout ++;
         if (timeout > 100000) return -1;
     }
 
     return 0;
 }
 
+static inline int i2c_wait_TEND(i2c_t *obj) {
+    int timeout = 0;
+
+    while (!(i2c_status(obj) & (1 << 6))) {
+        timeout ++;
+        if (timeout > 100000) return -1;
+    }
+
+    return 0;
+}
+
+
 static inline void i2c_power_enable(i2c_t *obj) {
     volatile uint8_t dummy;
     switch ((int)obj->i2c) {
@@ -90,29 +124,13 @@
     obj->i2c = pinmap_merge(i2c_sda, i2c_scl);
     obj->dummy = 1;
     MBED_ASSERT((int)obj->i2c != NC);
-    
+
     // enable power
     i2c_power_enable(obj);
-    
-    // full reset
-    REG(CR1.UINT8[0]) &= ~(1 << 7); // CR1.ICE off
-    REG(CR1.UINT8[0]) |=  (1 << 6); // CR1.IICRST on
-    REG(CR1.UINT8[0]) |=  (1 << 7); // CR1.ICE on
-
-    REG(MR1.UINT8[0])  =  0x08;  // P_phi /8  9bit (including Ack)
-    REG(SER.UINT8[0])  =  0x00;  // no slave addr enabled
 
-    // set default frequency at 100k
-    i2c_frequency(obj, 100000);
-
-    REG(MR2.UINT8[0])  =  0x07; 
-    REG(MR3.UINT8[0])  =  0x00;
+    // full reset
+    i2c_reg_reset(obj);
 
-    REG(FER.UINT8[0])  =  0x72;  // SCLE, NFE enabled, TMOT
-    REG(IER.UINT8[0])  =  0x00;  // no interrupt
-
-    REG(CR1.UINT32) &= ~(1 << 6); // CR1.IICRST negate reset
-    
     pinmap_pinout(sda, PinMap_I2C_SDA);
     pinmap_pinout(scl, PinMap_I2C_SCL);
 }
@@ -127,11 +145,11 @@
 }
 
 inline int i2c_stop(i2c_t *obj) {
-    int timeout = 0;
+    volatile int timeout = 0;
 
     // write the stop bit
     REG(CR2.UINT32) |= (1 << 3);
-    
+
     // wait for SP bit to reset
     while(REG(CR2.UINT32) & (1 << 3)) {
         timeout ++;
@@ -159,91 +177,140 @@
         volatile int dummy = REG(DRR.UINT32);
         obj->dummy = 0;
     }
-    if (last) {
+
+    // wait for it to arrive
+    i2c_wait_RDRF(obj);
+
+    if (last == 2) {
+        /* this time is befor last byte read */
+        /* Set MR3 WATI bit is 1 */;
+        REG(MR3.UINT32) |= (1 << 6);
+    } else if (last == 1) {
         // send a NOT ACK
-        REG(MR2.UINT32) |=  (1 <<6);
+        REG(MR3.UINT32) |=  (1 <<3);
     } else {
         // send a ACK
-        REG(MR2.UINT32) &= ~(1 <<6);
+        REG(MR3.UINT32) &= ~(1 <<3);
     }
-    // wait for it to arrive
-    i2c_wait_RDRF(obj);
-    
+
     // return the data
     return (REG(DRR.UINT32) & 0xFF);
 }
 
 void i2c_frequency(i2c_t *obj, int hz) {
     uint32_t PCLK = 6666666;
-    
+
     uint32_t pulse = PCLK / (hz * 2);
-    
+
     // I2C Rate
     REG(BRL.UINT32) = pulse;
     REG(BRH.UINT32) = pulse;
 }
 
 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
-    int count, status;
-    
+    int count = 0;
+    int status;
+    int value;
+    volatile uint32_t work_reg = 0;
+
+
+    // full reset
+    i2c_reg_reset(obj);
+
     status = i2c_start(obj);
-    
+
     if (status == 0xff) {
         i2c_stop(obj);
         return I2C_ERROR_BUS_BUSY;
     }
-    
+
     status = i2c_do_write(obj, (address | 0x01));
     if (status & 0x01) {
         i2c_stop(obj);
         return I2C_ERROR_NO_SLAVE;
     }
-
-    // Read in all except last byte
-    for (count = 0; count < (length - 1); count++) {
-        int value = i2c_do_read(obj, 0);
-        status = i2c_status(obj);
-        if (status & 0x10) {
-            i2c_stop(obj);
-            return count;
-        }
-        data[count] = (char) value;
+    
+    /* wati RDRF */
+    i2c_wait_RDRF(obj);
+    /* check ACK/NACK */
+    if ((REG(SR2.UINT32) & (1 << 4) == 1)) {
+        /* Slave sends NACK */
+        i2c_stop(obj);
+        return I2C_ERROR_NO_SLAVE;
     }
     
+    // Read in all except last byte
+    if (length > 1) {
+        for (count = 0; count < (length - 1); count++) {
+            if (count == (length - 2)) {
+                value = i2c_do_read(obj, 1);
+            } else if ((length >= 3) && (count == (length - 3))) {
+                value = i2c_do_read(obj, 2);
+            } else {
+                value = i2c_do_read(obj, 0);
+            }
+            status = i2c_status(obj);
+            if (status & 0x10) {
+                i2c_stop(obj);
+                return count;
+            }
+            data[count] = (char) value;
+        }
+    }
+
     // read in last byte
-    int value = i2c_do_read(obj, 1);
+    i2c_wait_RDRF(obj);
+    /* RIICnSR2.STOP = 0 */
+    REG(SR2.UINT32) &= ~(1 << 3);
+    /* RIICnCR2.SP   = 1 */
+    REG(CR2.UINT32) |= (1 << 3);
+    /* RIICnDRR read */
+    value = REG(DRR.UINT32) & 0xFF;
+    /* RIICnMR3.WAIT = 0 */
+    REG(MR3.UINT32) &= ~(1 << 6);
+    /* wait SR2.STOP = 1 */
+    while ((work_reg & (1 << 3)) == (1 << 3)) {
+        work_reg = REG(SR2.UINT32);
+    }
+    /* SR2.NACKF = 0 */
+    REG(SR2.UINT32) &= ~(1 << 4);
+    /* SR2.STOP  = 0 */
+    REG(SR2.UINT32) &= ~(1 << 3);
     status = i2c_status(obj);
     if (status & 0x10) {
         i2c_stop(obj);
         return length - 1;
     }
-    
+
     data[count] = (char) value;
-    
+
     // If not repeated start, send stop.
     if (stop) {
         i2c_stop(obj);
     }
-    
+
     return length;
 }
 
 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
     int i, status;
-    
+
+    // full reset
+    i2c_reg_reset(obj);
+
     status = i2c_start(obj);
-    
+
     if ((status == 0xff)) {
         i2c_stop(obj);
         return I2C_ERROR_BUS_BUSY;
     }
-    
+
     status = i2c_do_write(obj, address);
     if (status & 0x10) {
         i2c_stop(obj);
         return I2C_ERROR_NO_SLAVE;
     }
-    
+
     for (i=0; i<length; i++) {
         status = i2c_do_write(obj, data[i]);
         if(status & 0x10) {
@@ -251,12 +318,14 @@
             return i;
         }
     }
-    
+
+    i2c_wait_TEND(obj);
+
     // If not repeated start, send stop.
     if (stop) {
         i2c_stop(obj);
     }
-    
+
     return length;
 }
 
@@ -276,7 +345,7 @@
     } else {
         ack = 1;
     }
-    
+
     return ack;
 }
 
@@ -291,7 +360,7 @@
 int i2c_slave_receive(i2c_t *obj) {
     int status;
     int retval;
-    
+
     status = i2c_addressed(obj);
     switch(status) {
         case 0x3: retval = 1; break;
@@ -299,7 +368,7 @@
         case 0x1: retval = 3; break;
         default : retval = 1; break;
     }
-    
+
     return(retval);
 }
 
@@ -311,7 +380,7 @@
         volatile int dummy = REG(DRR.UINT32) ;
         obj->dummy = 0;
     }
-    
+
     do {
         i2c_wait_RDRF(obj);
         status = i2c_status(obj);
@@ -320,35 +389,35 @@
         }
         count++;
     } while ( !(status & 0x10)  && (count < length) );
-    
+
     if(status & 0x10) {
         i2c_stop(obj);
     }
-    
+
     //i2c_clear_TDRE(obj);
-    
+
     return count;
 }
 
 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
     int count = 0;
     int status;
-    
+
     if(length <= 0) {
         return(0);
     }
-    
+
     do {
         status = i2c_do_write(obj, data[count]);
         count++;
     } while ((count < length) && !(status & 0x10));
-    
+
     if (!(status & 0x10)) {
         i2c_stop(obj);
     }
-    
+
     i2c_clear_TDRE(obj);
-    
+
     return(count);
 }
 

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c	Wed Nov 19 08:45:06 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c	Wed Nov 19 09:00:07 2014 +0000
@@ -17,28 +17,34 @@
 #include "mbed_error.h"
 #include "gpio_addrdefine.h"
 
+PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */
+
 void pin_function(PinName pin, int function) {
     if (pin == (PinName)NC) return;
     
     int n = pin >> 4;
     int bitmask = 1<<(pin  & 0xf);
     
-    if (function == 0) {
-        // means GPIO mode
-        *PMC(n) &= ~bitmask;
-    } else {
-        // alt-function mode
-        *PMC(n) |= bitmask;
-        --function;
+    if (gpio_multi_guard != pin) {
+        if (function == 0) {
+            // means GPIO mode
+            *PMC(n) &= ~bitmask;
+        } else {
+            // alt-function mode
+            *PMC(n) |= bitmask;
+            --function;
 
-        if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else  { *PFCAE(n) &= ~bitmask;}
-        if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else  { *PFCE(n) &= ~bitmask;}
-        if (function & (1 << 0)) { *PFC(n) |= bitmask;}else  { *PFC(n) &= ~bitmask;}
-        *PIPC(n) |= bitmask;
+            if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else  { *PFCAE(n) &= ~bitmask;}
+            if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else  { *PFCE(n) &= ~bitmask;}
+            if (function & (1 << 0)) { *PFC(n) |= bitmask;}else  { *PFC(n) &= ~bitmask;}
+            *PIPC(n) |= bitmask;
 
-        if (P1_0 <= pin && pin <= P1_7 && function == 0) {
-            *PBDC(n) |= bitmask;
+            if (P1_0 <= pin && pin <= P1_7 && function == 0) {
+                *PBDC(n) |= bitmask;
+            }
         }
+    } else {
+        gpio_multi_guard = (PinName)NC;
     }
 }
 

--- a/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c	Wed Nov 19 08:45:06 2014 +0000
+++ b/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c	Wed Nov 19 09:00:07 2014 +0000
@@ -142,7 +142,7 @@
     b0 SPB2DT - Serial port break data   : High-level */
     //obj->uart->SCSPTR |= 0x0000u;
 
-    obj->uart->SCSCR = 0x0030;
+    obj->uart->SCSCR = 0x00F0;
 
     // pinout the chosen uart
     pinmap_pinout(tx, PinMap_UART_TX);
@@ -156,10 +156,11 @@
         case P_SCIF4: obj->index = 4; break;
         case P_SCIF5: obj->index = 5; break;
         case P_SCIF6: obj->index = 6; break;
+        case P_SCIF7: obj->index = 7; break;
     }
     uart_data[obj->index].sw_rts.pin = NC;
     uart_data[obj->index].sw_cts.pin = NC;
-    serial_set_flow_control(obj, FlowControlNone, NC, NC);
+//    serial_set_flow_control(obj, FlowControlNone, NC, NC);
 
     is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
 
@@ -219,11 +220,105 @@
  * INTERRUPTS HANDLING
  ******************************************************************************/
 
-void uart0_irq() {irq_handler(0, RxIrq);//dummy call
+static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
+    uint16_t dummy_read;
+    /* Clear TDFE */
+    switch (index) {
+        case 0:
+            dummy_read = SCFSR_0;
+            SCFSR_0 = (dummy_read & ~0x0060);
+            break;
+        case 1:
+            dummy_read = SCFSR_1;
+            SCFSR_1 = (dummy_read & ~0x0060);
+            break;
+        case 2:
+            dummy_read = SCFSR_2;
+            SCFSR_2 = (dummy_read & ~0x0060);
+            break;
+        case 3:
+            dummy_read = SCFSR_3;
+            SCFSR_3 = (dummy_read & ~0x0060);
+            break;
+        case 4:
+            dummy_read = SCFSR_4;
+            SCFSR_4 = (dummy_read & ~0x0060);
+            break;
+        case 5:
+            dummy_read = SCFSR_5;
+            SCFSR_5 = (dummy_read & ~0x0060);
+            break;
+        case 6:
+            dummy_read = SCFSR_6;
+            SCFSR_6 = (dummy_read & ~0x0060);
+            break;
+        case 7:
+            dummy_read = SCFSR_7;
+            SCFSR_7 = (dummy_read & ~0x0060);
+            break;
     }
-void uart1_irq() {/*uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_UART_TypeDef*)LPC_UART1);*/}
-void uart2_irq() {/*uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2, (LPC_UART_TypeDef*)LPC_UART2);*/}
-void uart3_irq() {/*uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3, (LPC_UART_TypeDef*)LPC_UART3);*/}
+    irq_handler(uart_data[index].serial_irq_id, TxIrq);
+    GIC_EndInterrupt(irq_num);
+}
+
+static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
+    uint16_t dummy_read;
+    /* Clear RDF */
+    switch (index) {
+        case 0:
+            dummy_read = SCFSR_0;
+            SCFSR_0 = (dummy_read & ~0x0003);
+            break;
+        case 1:
+            dummy_read = SCFSR_1;
+            SCFSR_1 = (dummy_read & ~0x0003);
+            break;
+        case 2:
+            dummy_read = SCFSR_2;
+            SCFSR_2 = (dummy_read & ~0x0003);
+            break;
+        case 3:
+            dummy_read = SCFSR_3;
+            SCFSR_3 = (dummy_read & ~0x0003);
+            break;
+        case 4:
+            dummy_read = SCFSR_4;
+            SCFSR_4 = (dummy_read & ~0x0003);
+            break;
+        case 5:
+            dummy_read = SCFSR_5;
+            SCFSR_5 = (dummy_read & ~0x0003);
+            break;
+        case 6:
+            dummy_read = SCFSR_6;
+            SCFSR_6 = (dummy_read & ~0x0003);
+            break;
+        case 7:
+            dummy_read = SCFSR_7;
+            SCFSR_7 = (dummy_read & ~0x0003);
+            break;
+    }
+    irq_handler(uart_data[index].serial_irq_id, RxIrq);
+    GIC_EndInterrupt(irq_num);
+}
+/* TX handler */
+void uart0_tx_irq()  {uart_tx_irq(SCIFTXI0_IRQn, 0);}
+void uart1_tx_irq()  {uart_tx_irq(SCIFTXI1_IRQn, 1);}
+void uart2_tx_irq()  {uart_tx_irq(SCIFTXI2_IRQn, 2);}
+void uart3_tx_irq()  {uart_tx_irq(SCIFTXI3_IRQn, 3);}
+void uart4_tx_irq()  {uart_tx_irq(SCIFTXI4_IRQn, 4);}
+void uart5_tx_irq()  {uart_tx_irq(SCIFTXI5_IRQn, 5);}
+void uart6_tx_irq()  {uart_tx_irq(SCIFTXI6_IRQn, 6);}
+void uart7_tx_irq()  {uart_tx_irq(SCIFTXI7_IRQn, 7);}
+/* RX handler */
+void uart0_rx_irq()  {uart_rx_irq(SCIFRXI0_IRQn, 0);}
+void uart1_rx_irq()  {uart_rx_irq(SCIFRXI1_IRQn, 1);}
+void uart2_rx_irq()  {uart_rx_irq(SCIFRXI2_IRQn, 2);}
+void uart3_rx_irq()  {uart_rx_irq(SCIFRXI3_IRQn, 3);}
+void uart4_rx_irq()  {uart_rx_irq(SCIFRXI4_IRQn, 4);}
+void uart5_rx_irq()  {uart_rx_irq(SCIFRXI5_IRQn, 5);}
+void uart6_rx_irq()  {uart_rx_irq(SCIFRXI6_IRQn, 6);}
+void uart7_rx_irq()  {uart_rx_irq(SCIFRXI7_IRQn, 7);}
 
 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
     irq_handler = handler;
@@ -231,27 +326,72 @@
 }
 
 static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
-/*    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-    switch ((int)obj->uart) {
-        case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
-        case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
-        case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
-        case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
+    switch (obj->index){
+        case 0:
+            InterruptHandlerRegister(SCIFTXI0_IRQn, (void (*)(uint32_t))uart0_tx_irq);
+            InterruptHandlerRegister(SCIFRXI0_IRQn, (void (*)(uint32_t))uart0_rx_irq);
+            GIC_SetPriority(SCIFTXI0_IRQn, 5);
+            GIC_SetPriority(SCIFRXI0_IRQn, 5);
+            GIC_EnableIRQ(SCIFTXI0_IRQn);
+            GIC_EnableIRQ(SCIFRXI0_IRQn);
+            break;
+        case 1:
+            InterruptHandlerRegister(SCIFTXI1_IRQn, (void (*)(uint32_t))uart1_tx_irq);
+            InterruptHandlerRegister(SCIFRXI1_IRQn, (void (*)(uint32_t))uart1_rx_irq);
+            GIC_SetPriority(SCIFTXI1_IRQn, 5);
+            GIC_SetPriority(SCIFRXI1_IRQn, 5);
+            GIC_EnableIRQ(SCIFTXI1_IRQn);
+            GIC_EnableIRQ(SCIFRXI1_IRQn);
+            break;
+        case 2:
+            InterruptHandlerRegister(SCIFTXI2_IRQn, (void (*)(uint32_t))uart2_tx_irq);
+            InterruptHandlerRegister(SCIFRXI2_IRQn, (void (*)(uint32_t))uart2_rx_irq);
+            GIC_SetPriority(SCIFTXI2_IRQn, 5);
+            GIC_SetPriority(SCIFRXI2_IRQn, 5);
+            GIC_EnableIRQ(SCIFTXI2_IRQn);
+            GIC_EnableIRQ(SCIFRXI2_IRQn);
+            break;
+        case 3:
+            InterruptHandlerRegister(SCIFTXI3_IRQn, (void (*)(uint32_t))uart3_tx_irq);
+            InterruptHandlerRegister(SCIFRXI3_IRQn, (void (*)(uint32_t))uart3_rx_irq);
+            GIC_SetPriority(SCIFTXI3_IRQn, 5);
+            GIC_SetPriority(SCIFRXI3_IRQn, 5);
+            GIC_EnableIRQ(SCIFTXI3_IRQn);
+            GIC_EnableIRQ(SCIFRXI3_IRQn);
+            break;
+        case 4:
+            InterruptHandlerRegister(SCIFTXI4_IRQn, (void (*)(uint32_t))uart4_tx_irq);
+            InterruptHandlerRegister(SCIFRXI4_IRQn, (void (*)(uint32_t))uart4_rx_irq);
+            GIC_SetPriority(SCIFTXI4_IRQn, 5);
+            GIC_SetPriority(SCIFRXI4_IRQn, 5);
+            GIC_EnableIRQ(SCIFTXI4_IRQn);
+            GIC_EnableIRQ(SCIFRXI4_IRQn);
+            break;
+        case 5:
+            InterruptHandlerRegister(SCIFTXI5_IRQn, (void (*)(uint32_t))uart5_tx_irq);
+            InterruptHandlerRegister(SCIFRXI5_IRQn, (void (*)(uint32_t))uart5_rx_irq);
+            GIC_SetPriority(SCIFTXI5_IRQn, 5);
+            GIC_SetPriority(SCIFRXI5_IRQn, 5);
+            GIC_EnableIRQ(SCIFTXI5_IRQn);
+            GIC_EnableIRQ(SCIFRXI5_IRQn);
+            break;
+        case 6:
+            InterruptHandlerRegister(SCIFTXI6_IRQn, (void (*)(uint32_t))uart6_tx_irq);
+            InterruptHandlerRegister(SCIFRXI6_IRQn, (void (*)(uint32_t))uart6_rx_irq);
+            GIC_SetPriority(SCIFTXI6_IRQn, 5);
+            GIC_SetPriority(SCIFRXI6_IRQn, 5);
+            GIC_EnableIRQ(SCIFTXI6_IRQn);
+            GIC_EnableIRQ(SCIFRXI6_IRQn);
+            break;
+        case 7:
+            InterruptHandlerRegister(SCIFTXI7_IRQn, (void (*)(uint32_t))uart7_tx_irq);
+            InterruptHandlerRegister(SCIFRXI7_IRQn, (void (*)(uint32_t))uart7_rx_irq);
+            GIC_SetPriority(SCIFTXI7_IRQn, 5);
+            GIC_SetPriority(SCIFRXI7_IRQn, 5);
+            GIC_EnableIRQ(SCIFTXI7_IRQn);
+            GIC_EnableIRQ(SCIFRXI7_IRQn);
+            break;
     }
-
-    if (enable) {
-        obj->uart->IER |= 1 << irq;
-        //NVIC_SetVector(irq_n, vector);
-        //NVIC_EnableIRQ(irq_n);
-    } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
-        int all_disabled = 0;
-        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
-        obj->uart->IER &= ~(1 << irq);
-        all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
-        if (all_disabled) ;
-            //NVIC_DisableIRQ(irq_n);
-    }*/
 }
 
 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {