Wim Huiskamp / SWO

Serial Wire Output (SWO) viewer for tracing purposes. Tested on F401 and ST-LINK Utility as well as for F103 and Segger J-Link SWO viewer.

Dependents:   WiFi_Scanner mbed_nucleo_swo DISCO-F429ZI_LCDTS_demo_richard TEST_SM_SPEED

SWO.cpp@2:ef928f61a770, 2014-12-21 (annotated)

Committer:
wim
Date:
Sun Dec 21 15:09:10 2014 +0000
Revision:
2:ef928f61a770
Parent:
1:bae4cff278f6
Child:
3:e5af2e131b95
Added comments and documentation

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wim 1:bae4cff278f6 1 /* mbed SWO Library
wim 2:ef928f61a770 2 * Copyright (c) 2014, v01: WH. Ported from Segger example (www.segger.com)
wim 1:bae4cff278f6 3 *
wim 2:ef928f61a770 4 * Simple implementation for tracing via Serial Wire Output(SWO) for Cortex-M processors.
wim 1:bae4cff278f6 5 * It can be used with Host PC software such as ST-LINK Utility or Segger J-Link SWO viewer.
wim 1:bae4cff278f6 6 * This sample implementation ensures that output via SWO is enabled in order to guarantee
wim 1:bae4cff278f6 7 * that the application does not hang.
wim 1:bae4cff278f6 8 *
wim 1:bae4cff278f6 9 * Permission is hereby granted, free of charge, to any person obtaining a copy
wim 1:bae4cff278f6 10 * of this software and associated documentation files (the "Software"), to deal
wim 1:bae4cff278f6 11 * in the Software without restriction, including without limitation the rights
wim 1:bae4cff278f6 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
wim 1:bae4cff278f6 13 * copies of the Software, and to permit persons to whom the Software is
wim 1:bae4cff278f6 14 * furnished to do so, subject to the following conditions:
wim 1:bae4cff278f6 15 *
wim 1:bae4cff278f6 16 * The above copyright notice and this permission notice shall be included in
wim 1:bae4cff278f6 17 * all copies or substantial portions of the Software.
wim 1:bae4cff278f6 18 *
wim 1:bae4cff278f6 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
wim 1:bae4cff278f6 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
wim 1:bae4cff278f6 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
wim 1:bae4cff278f6 22 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
wim 1:bae4cff278f6 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
wim 1:bae4cff278f6 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
wim 1:bae4cff278f6 25 * THE SOFTWARE.
wim 1:bae4cff278f6 26 */
wim 2:ef928f61a770 27 #include "mbed.h"
wim 0:0fd55660fc26 28 #include "SWO.h"
wim 0:0fd55660fc26 29
wim 1:bae4cff278f6 30 /**
wim 1:bae4cff278f6 31 * Defines for Cortex-M debug unit
wim 1:bae4cff278f6 32 */
wim 0:0fd55660fc26 33 #define ITM_STIM_U32(n) (*(volatile unsigned int*)(0xE0000000+4*n)) // Stimulus Port n Register word access
wim 2:ef928f61a770 34 #define ITM_STIM_U8(n) (*(volatile char*)(0xE0000000+4*n)) // Stimulus Port n Register byte access
wim 0:0fd55660fc26 35 //#define ITM_STIM_U32_0 (*(volatile unsigned int*)0xE0000000) // Stimulus Port 0 Register word access
wim 0:0fd55660fc26 36 //#define ITM_STIM_U8_0 (*(volatile char*)0xE0000000) // Stimulus Port 0 Register byte access
wim 0:0fd55660fc26 37 #define ITM_ENA (*(volatile unsigned int*)0xE0000E00) // Trace Enable Ports Register
wim 0:0fd55660fc26 38 #define ITM_TCR (*(volatile unsigned int*)0xE0000E80) // Trace control register
wim 0:0fd55660fc26 39
wim 2:ef928f61a770 40 #define ITM_STIM_FIFOREADY 0x00000001 // FIFO empty
wim 2:ef928f61a770 41
wim 2:ef928f61a770 42 //Stuff below is for documentation and needs further testing
wim 2:ef928f61a770 43 // It seems that the Segger SWO Viewer and the ST-Link Utility do most/all of these
wim 2:ef928f61a770 44 // initialisations on the target before starting the session. This is probably not the case
wim 2:ef928f61a770 45 // when using GDB/OpenOCD.
wim 2:ef928f61a770 46 //
wim 2:ef928f61a770 47 //
wim 2:ef928f61a770 48 #if(0)
wim 2:ef928f61a770 49 #include <libopencm3/stm32/rcc.h>
wim 2:ef928f61a770 50 #include <libopencm3/stm32/gpio.h>
wim 2:ef928f61a770 51
wim 2:ef928f61a770 52 #include <libopencm3/stm32/dbgmcu.h>
wim 2:ef928f61a770 53 #include <libopencm3/cm3/scs.h>
wim 2:ef928f61a770 54 #include <libopencm3/cm3/tpiu.h>
wim 2:ef928f61a770 55 #include <libopencm3/cm3/itm.h>
wim 2:ef928f61a770 56
wim 1:bae4cff278f6 57 /**
wim 2:ef928f61a770 58 * SWO_Setup() Example
wim 1:bae4cff278f6 59 *
wim 2:ef928f61a770 60 * This file is part of the libopencm3 project.
wim 2:ef928f61a770 61 *
wim 2:ef928f61a770 62 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
wim 2:ef928f61a770 63 * https://github.com/1divf/libopenstm32/blob/master/examples/stm32/stm32-h103/traceswo/traceswo.c
wim 2:ef928f61a770 64 *
wim 2:ef928f61a770 65 */
wim 2:ef928f61a770 66 void SWO_Setup(void) {
wim 2:ef928f61a770 67 /* Enable trace subsystem (we'll use ITM and TPIU) */
wim 2:ef928f61a770 68 SCS_DEMCR |= SCS_DEMCR_TRCENA;
wim 2:ef928f61a770 69
wim 2:ef928f61a770 70 /* Use Manchester code for asynchronous transmission */
wim 2:ef928f61a770 71 TPIU_SPPR = TPIU_SPPR_ASYNC_MANCHESTER;
wim 2:ef928f61a770 72 TPIU_ACPR = 7;
wim 2:ef928f61a770 73
wim 2:ef928f61a770 74 /* Data width is 1 byte */
wim 2:ef928f61a770 75 TPIU_CSPSR = TPIU_CSPSR_BYTE;
wim 2:ef928f61a770 76
wim 2:ef928f61a770 77 /* Formatter and flush control */
wim 2:ef928f61a770 78 TPIU_FFCR &= ~TPIU_FFCR_ENFCONT;
wim 2:ef928f61a770 79
wim 2:ef928f61a770 80 /* Enable TRACESWO pin for async mode */
wim 2:ef928f61a770 81 DBGMCU_CR = DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_ASYNC;
wim 2:ef928f61a770 82
wim 2:ef928f61a770 83 /* Unlock access to ITM registers */
wim 2:ef928f61a770 84 /* FIXME: Magic numbers... Is this Cortex-M3 generic? */
wim 2:ef928f61a770 85 *((volatile uint32_t*)0xE0000FB0) = 0xC5ACCE55;
wim 2:ef928f61a770 86
wim 2:ef928f61a770 87 /* Enable ITM with ID = 1 */
wim 2:ef928f61a770 88 ITM_TCR = (1 << 16) | ITM_TCR_ITMENA;
wim 2:ef928f61a770 89 /* Enable stimulus port 1 */
wim 2:ef928f61a770 90 ITM_TER[0] = 1;
wim 2:ef928f61a770 91 }
wim 2:ef928f61a770 92
wim 2:ef928f61a770 93 /**
wim 2:ef928f61a770 94 * SWO_Setup() Example
wim 2:ef928f61a770 95 *
wim 2:ef928f61a770 96 * http://forum.segger.com/index.php?page=Thread&threadID=608
wim 2:ef928f61a770 97 *
wim 2:ef928f61a770 98 */
wim 2:ef928f61a770 99 void SWO_Setup_1(void) {
wim 2:ef928f61a770 100 U32 SWOPrescaler;
wim 2:ef928f61a770 101 U32 SWOSpeed;
wim 2:ef928f61a770 102
wim 2:ef928f61a770 103 //<Init PLL, set CPU clock to 72 MHz> // Optional, so I do not pos it here
wim 2:ef928f61a770 104
wim 2:ef928f61a770 105 SWOSpeed = 6000000;
wim 2:ef928f61a770 106 *((volatile unsigned *)0xE000EDFC) = 0x01000000; // "Debug Exception and Monitor Control Register (DEMCR)"
wim 2:ef928f61a770 107 *((volatile unsigned *)0xE0042004) = 0x00000027;
wim 2:ef928f61a770 108 *((volatile unsigned *)0xE00400F0) = 0x00000002; // "Selected PIN Protocol Register": Select which protocol to use for trace output (2: SWO)
wim 2:ef928f61a770 109 SWOPrescaler = (72000000 / SWOSpeed) - 1; // SWOSpeed in Hz
wim 2:ef928f61a770 110 *((volatile unsigned *)0xE0040010) = SWOPrescaler; // "Async Clock Prescaler Register". Scale the baud rate of the asynchronous output
wim 2:ef928f61a770 111 *((volatile unsigned *)0xE0000FB0) = 0xC5ACCE55; // ITM Lock Access Register, C5ACCE55 enables more write access to Control Register 0xE00 :: 0xFFC
wim 2:ef928f61a770 112 *((volatile unsigned *)0xE0000E80) = 0x0001000D; // ITM Trace Control Register
wim 2:ef928f61a770 113 *((volatile unsigned *)0xE0000E40) = 0x0000000F; // ITM Trace Privilege Register
wim 2:ef928f61a770 114 *((volatile unsigned *)0xE0000E00) = 0x00000001; // ITM Trace Enable Register. Enabled tracing on stimulus ports. One bit per stimulus port.
wim 2:ef928f61a770 115 *((volatile unsigned *)0xE0001000) = 0x400003FE; // DWT_CTRL
wim 2:ef928f61a770 116 *((volatile unsigned *)0xE0040304) = 0x00000100; // Formatter and Flush Control Register
wim 2:ef928f61a770 117 }
wim 2:ef928f61a770 118 #endif
wim 2:ef928f61a770 119
wim 2:ef928f61a770 120 /**
wim 1:bae4cff278f6 121 * SWO_PrintChar()
wim 1:bae4cff278f6 122 *
wim 1:bae4cff278f6 123 * @brief
wim 1:bae4cff278f6 124 * Checks if SWO is set up. If it is not, return,
wim 1:bae4cff278f6 125 * to avoid program hangs if no debugger is connected.
wim 1:bae4cff278f6 126 * If it is set up, print a character to the ITM_STIM register
wim 1:bae4cff278f6 127 * in order to provide data for SWO.
wim 1:bae4cff278f6 128 * @param c The Character to be printed.
wim 1:bae4cff278f6 129 * @notes Additional checks for device specific registers can be added.
wim 1:bae4cff278f6 130 */
wim 1:bae4cff278f6 131 void SWO_PrintChar(char c) {
wim 0:0fd55660fc26 132
wim 2:ef928f61a770 133 #if(1)
wim 2:ef928f61a770 134 //Use CMSIS_core_DebugFunctions. See core_cm3.h
wim 2:ef928f61a770 135 ITM_SendChar (c);
wim 2:ef928f61a770 136
wim 2:ef928f61a770 137 #else
wim 2:ef928f61a770 138 //Use Segger example. Basically same as CMSIS
wim 2:ef928f61a770 139
wim 0:0fd55660fc26 140 // Check if ITM_TCR.ITMENA is set
wim 0:0fd55660fc26 141 if ((ITM_TCR & 1) == 0) {
wim 0:0fd55660fc26 142 return;
wim 0:0fd55660fc26 143 }
wim 1:bae4cff278f6 144
wim 0:0fd55660fc26 145 // Check if stimulus port is enabled
wim 0:0fd55660fc26 146 if ((ITM_ENA & 1) == 0) {
wim 0:0fd55660fc26 147 return;
wim 0:0fd55660fc26 148 }
wim 0:0fd55660fc26 149
wim 1:bae4cff278f6 150 // Wait until STIMx FIFO is ready, then send data
wim 2:ef928f61a770 151 // while ((ITM_STIM_U8(0) & 1) == 0);
wim 2:ef928f61a770 152 while (!(ITM_STIM_U8(0) & ITM_STIM_FIFOREADY));
wim 1:bae4cff278f6 153 ITM_STIM_U8(0) = c;
wim 2:ef928f61a770 154
wim 1:bae4cff278f6 155 // while ((ITM_STIM_U32(0) & 1) == 0);
wim 1:bae4cff278f6 156 // ITM_STIM_U32(0) = c;
wim 2:ef928f61a770 157
wim 2:ef928f61a770 158 #endif
wim 0:0fd55660fc26 159 }
wim 0:0fd55660fc26 160
wim 1:bae4cff278f6 161 /**
wim 1:bae4cff278f6 162 * SWO_PrintString()
wim 1:bae4cff278f6 163 *
wim 1:bae4cff278f6 164 * @brief Print a string via SWO.
wim 1:bae4cff278f6 165 * @param *s The string to be printed.
wim 1:bae4cff278f6 166 *
wim 1:bae4cff278f6 167 */
wim 0:0fd55660fc26 168 void SWO_PrintString(const char *s) {
wim 1:bae4cff278f6 169
wim 1:bae4cff278f6 170 // Print out characters until \0
wim 0:0fd55660fc26 171 while (*s) {
wim 0:0fd55660fc26 172 SWO_PrintChar(*s++);
wim 0:0fd55660fc26 173 }
wim 0:0fd55660fc26 174 }