HDSP253X Smart Alphanumeric LED matrix display
HDSP253X.h@0:b3430a613781, 2015-01-25 (annotated)
- Committer:
- wim
- Date:
- Sun Jan 25 17:23:44 2015 +0000
- Revision:
- 0:b3430a613781
HDSP253X Smart Alphanumeric LED matrix display. First release as Lib.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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wim | 0:b3430a613781 | 1 | /* HDSP253X_Display - Intelligent 8 digit 5x7 LED matrix display |
wim | 0:b3430a613781 | 2 | * |
wim | 0:b3430a613781 | 3 | * Copyright (c) 2011 Wim Huiskamp |
wim | 0:b3430a613781 | 4 | * Modified software based on sourcecode by RAC 06/08/2008 |
wim | 0:b3430a613781 | 5 | * |
wim | 0:b3430a613781 | 6 | * Released under the MIT License: http://mbed.org/license/mit |
wim | 0:b3430a613781 | 7 | * |
wim | 0:b3430a613781 | 8 | * version 0.2 Initial Release |
wim | 0:b3430a613781 | 9 | */ |
wim | 0:b3430a613781 | 10 | #ifndef MBED_HDSP253X_H |
wim | 0:b3430a613781 | 11 | #define MBED_HDSP253X_H |
wim | 0:b3430a613781 | 12 | /*---------------------------------------------------------------------------*\ |
wim | 0:b3430a613781 | 13 | | Original text by RAC 06/08/2008 has been modified to fix those parts of |
wim | 0:b3430a613781 | 14 | | the description which explain hardware or software that has been removed or |
wim | 0:b3430a613781 | 15 | | adapted in the new version. |
wim | 0:b3430a613781 | 16 | | |
wim | 0:b3430a613781 | 17 | | Description: Display driver and demonstrator for HDSP253X series intelligent |
wim | 0:b3430a613781 | 18 | | 8 character LED display modules. Options include adjusting |
wim | 0:b3430a613781 | 19 | | brightness and message blinking. |
wim | 0:b3430a613781 | 20 | | This software drives a single display module using 8 bit databus, |
wim | 0:b3430a613781 | 21 | | 5 bit addressbus and controlsignals. Note that this software |
wim | 0:b3430a613781 | 22 | | will drive all display devices in the series, including HDSP2530 Orange, |
wim | 0:b3430a613781 | 23 | | HDSP2531 Yellow, HDSP2532 red and HDSP2533 green devices. It will also |
wim | 0:b3430a613781 | 24 | | drive the smaller HDSP21XX series. |
wim | 0:b3430a613781 | 25 | | |
wim | 0:b3430a613781 | 26 | | The peripheral is connected to the following pins: |
wim | 0:b3430a613781 | 27 | | HDSP253X |
wim | 0:b3430a613781 | 28 | | - Reset (pin 1) to EnableBus.RESET |
wim | 0:b3430a613781 | 29 | | - Flash (pin 2) to AddressBus.A5 |
wim | 0:b3430a613781 | 30 | | - Addr A0 (pin 3) to AddressBus.A0 |
wim | 0:b3430a613781 | 31 | | - Addr A1 (pin 4) to AddressBus.A1 |
wim | 0:b3430a613781 | 32 | | - Addr A2 (pin 5) to AddressBus.A2 |
wim | 0:b3430a613781 | 33 | | - Addr A3 (pin 6) to AddressBus.A3 |
wim | 0:b3430a613781 | 34 | | - Addr A4 (pin 10) to AddressBus.A4 |
wim | 0:b3430a613781 | 35 | | - Clock select (pin 11) to VCC (Pull Up) |
wim | 0:b3430a613781 | 36 | | - Clock in/out (pin 12) to Not Connected |
wim | 0:b3430a613781 | 37 | | - Write (pin 13) to ControlBus.WR |
wim | 0:b3430a613781 | 38 | | - CE (Pin 14) to EnableBus.CSDISP |
wim | 0:b3430a613781 | 39 | | - VDD 5V (Pin 15) |
wim | 0:b3430a613781 | 40 | | - GND (supply) (Pin 16) |
wim | 0:b3430a613781 | 41 | | - TST (Pin 16) NC |
wim | 0:b3430a613781 | 42 | | - GND (logic) (Pin 18) |
wim | 0:b3430a613781 | 43 | | - Read (pin 19) to ControlBus.RD |
wim | 0:b3430a613781 | 44 | | - Data D0 (pin 20) to Databus.D0 |
wim | 0:b3430a613781 | 45 | | - Data D1 (pin 21) to Databus.D1 |
wim | 0:b3430a613781 | 46 | | - Data D2 (pin 25) to Databus.D2 |
wim | 0:b3430a613781 | 47 | | - Data D3 (pin 26) to Databus.D3 |
wim | 0:b3430a613781 | 48 | | - Data D4 (pin 27) to Databus.D4 |
wim | 0:b3430a613781 | 49 | | - Data D5 (pin 28) to Databus.D5 |
wim | 0:b3430a613781 | 50 | | - Data D6 (pin 29) to Databus.D6 |
wim | 0:b3430a613781 | 51 | | - Data D7 (pin 30) to Databus.D7 |
wim | 0:b3430a613781 | 52 | | |
wim | 0:b3430a613781 | 53 | | The peripheral is connected to the following pins: |
wim | 0:b3430a613781 | 54 | | HDSP211X |
wim | 0:b3430a613781 | 55 | | - Reset (pin 1) to EnableBus.RESET |
wim | 0:b3430a613781 | 56 | | - Flash (pin 2) to AddressBus.A5 |
wim | 0:b3430a613781 | 57 | | - Addr A0 (pin 3) to AddressBus.A0 |
wim | 0:b3430a613781 | 58 | | - Addr A1 (pin 4) to AddressBus.A1 |
wim | 0:b3430a613781 | 59 | | - Addr A2 (pin 5) to AddressBus.A2 |
wim | 0:b3430a613781 | 60 | | - Addr A3 (pin 6) to AddressBus.A3 |
wim | 0:b3430a613781 | 61 | | - Addr A4 (pin 10) to AddressBus.A4 |
wim | 0:b3430a613781 | 62 | | - Clock select (pin 11) to VCC (Pull Up) |
wim | 0:b3430a613781 | 63 | | - Clock in/out (pin 12) to Not Connected |
wim | 0:b3430a613781 | 64 | | - Write (pin 13) to ControlBus.WR |
wim | 0:b3430a613781 | 65 | | - VDD 5V (Pin 14) |
wim | 0:b3430a613781 | 66 | | - GND (supply) (Pin 15) |
wim | 0:b3430a613781 | 67 | | - GND (logic) (Pin 16) |
wim | 0:b3430a613781 | 68 | | - CE (Pin 17) to EnableBus.CSDISP |
wim | 0:b3430a613781 | 69 | | - Read (pin 18) to ControlBus.RD |
wim | 0:b3430a613781 | 70 | | - Data D0 (pin 19) to Databus.D0 |
wim | 0:b3430a613781 | 71 | | - Data D1 (pin 20) to Databus.D1 |
wim | 0:b3430a613781 | 72 | | - Data D2 (pin 23) to Databus.D2 |
wim | 0:b3430a613781 | 73 | | - Data D3 (pin 24) to Databus.D3 |
wim | 0:b3430a613781 | 74 | | - Data D4 (pin 25) to Databus.D4 |
wim | 0:b3430a613781 | 75 | | - Data D5 (pin 26) to Databus.D5 |
wim | 0:b3430a613781 | 76 | | - Data D6 (pin 27) to Databus.D6 |
wim | 0:b3430a613781 | 77 | | - Data D7 (pin 28) to Databus.D7 |
wim | 0:b3430a613781 | 78 | | |
wim | 0:b3430a613781 | 79 | | Details: All signals to the HDSP253X are pulled up by 10K resistors. |
wim | 0:b3430a613781 | 80 | | The device must be reset by pulsing Reset low with Chip Enable |
wim | 0:b3430a613781 | 81 | | set high. Other signals are don't cares during a reset. This |
wim | 0:b3430a613781 | 82 | | firmware meets these conditions, as long as the pullups are |
wim | 0:b3430a613781 | 83 | | correctly installed. |
wim | 0:b3430a613781 | 84 | | |
wim | 0:b3430a613781 | 85 | | Connecting the clock select and in/out lines to the CPU is optional, |
wim | 0:b3430a613781 | 86 | | and may be used for experimentation. |
wim | 0:b3430a613781 | 87 | | If using one display, the clock select should normally be pulled |
wim | 0:b3430a613781 | 88 | | up high, which results in the clock signal being an output. |
wim | 0:b3430a613781 | 89 | | This driver software does not currently control these signals. |
wim | 0:b3430a613781 | 90 | | |
wim | 0:b3430a613781 | 91 | | If using more than one display, the driver software will |
wim | 0:b3430a613781 | 92 | | require modification and extension. Multiple displays should |
wim | 0:b3430a613781 | 93 | | have reset, data, address, flash and read/write lines paralleled. |
wim | 0:b3430a613781 | 94 | | Each display requires a unique Chip Enable input, and the |
wim | 0:b3430a613781 | 95 | | driver software will need to select which display to access. |
wim | 0:b3430a613781 | 96 | | The first display should have clock select high, and its clock |
wim | 0:b3430a613781 | 97 | | output connected to the clock inputs on all the other displays; |
wim | 0:b3430a613781 | 98 | | these should have clock select low to input the clock signal. |
wim | 0:b3430a613781 | 99 | | |
wim | 0:b3430a613781 | 100 | | Calls to wait_ms() are used to meet the display timing specs |
wim | 0:b3430a613781 | 101 | | may need to be modified at higher CPU speeds. |
wim | 0:b3430a613781 | 102 | | |
wim | 0:b3430a613781 | 103 | | |
wim | 0:b3430a613781 | 104 | | Legalese: This software is FREEWARE, and you can adapt it for any |
wim | 0:b3430a613781 | 105 | | purpose whatsoever. I cannot be held responsible for any |
wim | 0:b3430a613781 | 106 | | loss, injury, damage or death caused by the use of this |
wim | 0:b3430a613781 | 107 | | software. |
wim | 0:b3430a613781 | 108 | | |
wim | 0:b3430a613781 | 109 | \*---------------------------------------------------------------------------*/ |
wim | 0:b3430a613781 | 110 | |
wim | 0:b3430a613781 | 111 | //Useful stuff to simplify porting of some third party software |
wim | 0:b3430a613781 | 112 | #include <stdarg.h> |
wim | 0:b3430a613781 | 113 | //#include "Utils.h" |
wim | 0:b3430a613781 | 114 | |
wim | 0:b3430a613781 | 115 | |
wim | 0:b3430a613781 | 116 | /*****************************************************************************/ |
wim | 0:b3430a613781 | 117 | /********************* DEFINITIONS FOR HDSP253X DISPLAY ********************/ |
wim | 0:b3430a613781 | 118 | /*****************************************************************************/ |
wim | 0:b3430a613781 | 119 | |
wim | 0:b3430a613781 | 120 | // Specific delays for display operation, assuming internal clocking |
wim | 0:b3430a613781 | 121 | // This may need to be lengthened if a significantly slower external clock is used |
wim | 0:b3430a613781 | 122 | #define HDSP253X_1TCY_WAIT_MS 1 |
wim | 0:b3430a613781 | 123 | //#define HDSP253X_1TCY_WAIT_MS 10 |
wim | 0:b3430a613781 | 124 | #define HDSP253X_RST_CLR_DELAY_MS 2 // delay AFTER issuing reset or clear |
wim | 0:b3430a613781 | 125 | #define HDSP253X_SELFTEST_WAIT_MS 6000 // duration of self test operation |
wim | 0:b3430a613781 | 126 | |
wim | 0:b3430a613781 | 127 | // address values and masks for HDSP253X display access |
wim | 0:b3430a613781 | 128 | #define HDSP253X_ADDR_FLASH_BASE 0x00 |
wim | 0:b3430a613781 | 129 | #define HDSP253X_ADDR_UDC_ADDRESS 0x20 |
wim | 0:b3430a613781 | 130 | #define HDSP253X_ADDR_UDC_ROW_BASE 0x28 |
wim | 0:b3430a613781 | 131 | #define HDSP253X_ADDR_CTRL_WORD 0x30 |
wim | 0:b3430a613781 | 132 | #define HDSP253X_ADDR_CHAR_BASE 0x38 |
wim | 0:b3430a613781 | 133 | // minimises address line power consumption through pullups |
wim | 0:b3430a613781 | 134 | #define HDSP253X_ADDR_LOW_POWER 0x3F |
wim | 0:b3430a613781 | 135 | |
wim | 0:b3430a613781 | 136 | // control word masks for HDSP253X display |
wim | 0:b3430a613781 | 137 | #define HDSP253X_CTRL_BRIGHT_MASK 0x07 |
wim | 0:b3430a613781 | 138 | #define HDSP253X_CTRL_FLASH_MASK 0x08 |
wim | 0:b3430a613781 | 139 | #define HDSP253X_CTRL_BLINK_MASK 0x10 |
wim | 0:b3430a613781 | 140 | #define HDSP253X_CTRL_STRESULT_MASK 0x20 |
wim | 0:b3430a613781 | 141 | #define HDSP253X_CTRL_SELFTEST_MASK 0x40 |
wim | 0:b3430a613781 | 142 | #define HDSP253X_CTRL_CLEAR_MASK 0x80 |
wim | 0:b3430a613781 | 143 | |
wim | 0:b3430a613781 | 144 | // Masks for register read, Bit 7 not readable in the target hardware |
wim | 0:b3430a613781 | 145 | #define HDSP253X_CTRL_MASK 0x7F |
wim | 0:b3430a613781 | 146 | |
wim | 0:b3430a613781 | 147 | |
wim | 0:b3430a613781 | 148 | // display brightness definitions, indicating percentage brightness |
wim | 0:b3430a613781 | 149 | #define HDSP253X_BRIGHT_100 0x00 |
wim | 0:b3430a613781 | 150 | #define HDSP253X_BRIGHT_80 0x01 |
wim | 0:b3430a613781 | 151 | #define HDSP253X_BRIGHT_53 0x02 |
wim | 0:b3430a613781 | 152 | #define HDSP253X_BRIGHT_40 0x03 |
wim | 0:b3430a613781 | 153 | #define HDSP253X_BRIGHT_27 0x04 |
wim | 0:b3430a613781 | 154 | #define HDSP253X_BRIGHT_20 0x05 |
wim | 0:b3430a613781 | 155 | #define HDSP253X_BRIGHT_13 0x06 |
wim | 0:b3430a613781 | 156 | #define HDSP253X_BRIGHT_0 0x07 |
wim | 0:b3430a613781 | 157 | |
wim | 0:b3430a613781 | 158 | // miscellaneous definitions for HDSP253X display |
wim | 0:b3430a613781 | 159 | #define HDSP253X_NUM_CHARS 8 |
wim | 0:b3430a613781 | 160 | #define HDSP253X_CHAR_MASK 0x7F |
wim | 0:b3430a613781 | 161 | #define HDSP253X_UDC_SEL 0x80 |
wim | 0:b3430a613781 | 162 | #define HDSP253X_UDC_MASK 0x0F |
wim | 0:b3430a613781 | 163 | #define HDSP253X_ASCII_UDC_CHARS 0x80 |
wim | 0:b3430a613781 | 164 | |
wim | 0:b3430a613781 | 165 | // default display brightness |
wim | 0:b3430a613781 | 166 | #define HDSP253X_DEF_DISPLAY_BRIGHT HDSP253X_BRIGHT_100 |
wim | 0:b3430a613781 | 167 | |
wim | 0:b3430a613781 | 168 | |
wim | 0:b3430a613781 | 169 | /** Create an HDSP253X_Display object connected to the proper busses |
wim | 0:b3430a613781 | 170 | * |
wim | 0:b3430a613781 | 171 | * @param PCF8574_DataBus data databus to connect to |
wim | 0:b3430a613781 | 172 | * @param PCF8574_AddressBus address addressbus to connect to |
wim | 0:b3430a613781 | 173 | * @param PCF8574_EnableBus enable enablebus to connect to |
wim | 0:b3430a613781 | 174 | * @param MBED_ControlBus control controlbus to connect to |
wim | 0:b3430a613781 | 175 | */ |
wim | 0:b3430a613781 | 176 | class HDSP253X_Display { |
wim | 0:b3430a613781 | 177 | public: |
wim | 0:b3430a613781 | 178 | HDSP253X_Display(PCF8574_DataBus &databus, PCF8574_AddressBus &addressbus, |
wim | 0:b3430a613781 | 179 | PCF8574_EnableBus &enablebus, MBED_ControlBus &controlbus); |
wim | 0:b3430a613781 | 180 | void cls(); |
wim | 0:b3430a613781 | 181 | void putc(char disp_char); |
wim | 0:b3430a613781 | 182 | // char getc(); |
wim | 0:b3430a613781 | 183 | |
wim | 0:b3430a613781 | 184 | void printf (char * format, ...); |
wim | 0:b3430a613781 | 185 | void locate(uint8_t column); |
wim | 0:b3430a613781 | 186 | void define_user_char(uint8_t udc_char_num, uint8_t row_data_1, uint8_t row_data_2, |
wim | 0:b3430a613781 | 187 | uint8_t row_data_3, uint8_t row_data_4, uint8_t row_data_5, |
wim | 0:b3430a613781 | 188 | uint8_t row_data_6, uint8_t row_data_7); |
wim | 0:b3430a613781 | 189 | void putudc(char udc_char_num); |
wim | 0:b3430a613781 | 190 | |
wim | 0:b3430a613781 | 191 | void set_char_flash_state(bool flash_state, uint8_t char_pos); |
wim | 0:b3430a613781 | 192 | void set_all_flash_states(uint8_t flash_bits); |
wim | 0:b3430a613781 | 193 | void set_brightness(uint8_t brightness); |
wim | 0:b3430a613781 | 194 | void set_blink_mode(bool enable); |
wim | 0:b3430a613781 | 195 | void set_flash_mode(bool enable); |
wim | 0:b3430a613781 | 196 | void reset(); |
wim | 0:b3430a613781 | 197 | void start_self_test(); |
wim | 0:b3430a613781 | 198 | bool finish_self_test(); |
wim | 0:b3430a613781 | 199 | |
wim | 0:b3430a613781 | 200 | protected: |
wim | 0:b3430a613781 | 201 | PCF8574_DataBus &_databus; |
wim | 0:b3430a613781 | 202 | PCF8574_AddressBus &_addressbus; |
wim | 0:b3430a613781 | 203 | PCF8574_EnableBus &_enablebus; |
wim | 0:b3430a613781 | 204 | MBED_ControlBus &_controlbus; |
wim | 0:b3430a613781 | 205 | |
wim | 0:b3430a613781 | 206 | // int _row; |
wim | 0:b3430a613781 | 207 | int _column; |
wim | 0:b3430a613781 | 208 | void _write(uint8_t address, uint8_t data); |
wim | 0:b3430a613781 | 209 | uint8_t _read(uint8_t address); |
wim | 0:b3430a613781 | 210 | void _init(); |
wim | 0:b3430a613781 | 211 | // void _display_ascii_char(char ascii_char, uint8_t char_pos); |
wim | 0:b3430a613781 | 212 | // void _display_udc_char(char udc_char, uint8_t char_pos); |
wim | 0:b3430a613781 | 213 | // void _display_part_string(const char *disp_string, uint8_t start_pos, uint8_t end_pos); |
wim | 0:b3430a613781 | 214 | // void _display_fixed_string(const char *disp_string, uint8_t start_pos); |
wim | 0:b3430a613781 | 215 | |
wim | 0:b3430a613781 | 216 | }; |
wim | 0:b3430a613781 | 217 | |
wim | 0:b3430a613781 | 218 | |
wim | 0:b3430a613781 | 219 | #endif |
wim | 0:b3430a613781 | 220 | /*****************************************************************************/ |
wim | 0:b3430a613781 | 221 | /****************************** END OF FILE ********************************/ |
wim | 0:b3430a613781 | 222 | /*****************************************************************************/ |
wim | 0:b3430a613781 | 223 |