stephen mathenge
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Level_estimation_Maesurement
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Dependencies: Cayenne-LPP SDBlockDevice
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sx1276Regs-LoRa.h
00001 /** 00002 / _____) _ | | 00003 ( (____ _____ ____ _| |_ _____ ____| |__ 00004 \____ \| ___ | (_ _) ___ |/ ___) _ \ 00005 _____) ) ____| | | || |_| ____( (___| | | | 00006 (______/|_____)_|_|_| \__)_____)\____)_| |_| 00007 (C) 2014 Semtech 00008 00009 Description: SX1276 LoRa modem registers and bits definitions 00010 00011 License: Revised BSD License, see LICENSE.TXT file include in the project 00012 00013 Maintainer: Miguel Luis and Gregory Cristian 00014 00015 Copyright (c) 2017, Arm Limited and affiliates. 00016 00017 SPDX-License-Identifier: BSD-3-Clause 00018 */ 00019 #ifndef __SX1276_REGS_LORA_H__ 00020 #define __SX1276_REGS_LORA_H__ 00021 00022 /*! 00023 * ============================================================================ 00024 * SX1276 Internal registers Address 00025 * ============================================================================ 00026 */ 00027 #define REG_LR_FIFO 0x00 00028 // Common settings 00029 #define REG_LR_OPMODE 0x01 00030 #define REG_LR_FRFMSB 0x06 00031 #define REG_LR_FRFMID 0x07 00032 #define REG_LR_FRFLSB 0x08 00033 // Tx settings 00034 #define REG_LR_PACONFIG 0x09 00035 #define REG_LR_PARAMP 0x0A 00036 #define REG_LR_OCP 0x0B 00037 // Rx settings 00038 #define REG_LR_LNA 0x0C 00039 // LoRa registers 00040 #define REG_LR_FIFOADDRPTR 0x0D 00041 #define REG_LR_FIFOTXBASEADDR 0x0E 00042 #define REG_LR_FIFORXBASEADDR 0x0F 00043 #define REG_LR_FIFORXCURRENTADDR 0x10 00044 #define REG_LR_IRQFLAGSMASK 0x11 00045 #define REG_LR_IRQFLAGS 0x12 00046 #define REG_LR_RXNBBYTES 0x13 00047 #define REG_LR_RXHEADERCNTVALUEMSB 0x14 00048 #define REG_LR_RXHEADERCNTVALUELSB 0x15 00049 #define REG_LR_RXPACKETCNTVALUEMSB 0x16 00050 #define REG_LR_RXPACKETCNTVALUELSB 0x17 00051 #define REG_LR_MODEMSTAT 0x18 00052 #define REG_LR_PKTSNRVALUE 0x19 00053 #define REG_LR_PKTRSSIVALUE 0x1A 00054 #define REG_LR_RSSIVALUE 0x1B 00055 #define REG_LR_HOPCHANNEL 0x1C 00056 #define REG_LR_MODEMCONFIG1 0x1D 00057 #define REG_LR_MODEMCONFIG2 0x1E 00058 #define REG_LR_SYMBTIMEOUTLSB 0x1F 00059 #define REG_LR_PREAMBLEMSB 0x20 00060 #define REG_LR_PREAMBLELSB 0x21 00061 #define REG_LR_PAYLOADLENGTH 0x22 00062 #define REG_LR_PAYLOADMAXLENGTH 0x23 00063 #define REG_LR_HOPPERIOD 0x24 00064 #define REG_LR_FIFORXBYTEADDR 0x25 00065 #define REG_LR_MODEMCONFIG3 0x26 00066 #define REG_LR_FEIMSB 0x28 00067 #define REG_LR_FEIMID 0x29 00068 #define REG_LR_FEILSB 0x2A 00069 #define REG_LR_RSSIWIDEBAND 0x2C 00070 #define REG_LR_TEST2F 0x2F 00071 #define REG_LR_TEST30 0x30 00072 #define REG_LR_DETECTOPTIMIZE 0x31 00073 #define REG_LR_INVERTIQ 0x33 00074 #define REG_LR_TEST36 0x36 00075 #define REG_LR_DETECTIONTHRESHOLD 0x37 00076 #define REG_LR_SYNCWORD 0x39 00077 #define REG_LR_TEST3A 0x3A 00078 #define REG_LR_INVERTIQ2 0x3B 00079 00080 // end of documented register in datasheet 00081 // I/O settings 00082 #define REG_LR_DIOMAPPING1 0x40 00083 #define REG_LR_DIOMAPPING2 0x41 00084 // Version 00085 #define REG_LR_VERSION 0x42 00086 // Additional settings 00087 #define REG_LR_PLLHOP 0x44 00088 #define REG_LR_TCXO 0x4B 00089 #define REG_LR_PADAC 0x4D 00090 #define REG_LR_FORMERTEMP 0x5B 00091 #define REG_LR_BITRATEFRAC 0x5D 00092 #define REG_LR_AGCREF 0x61 00093 #define REG_LR_AGCTHRESH1 0x62 00094 #define REG_LR_AGCTHRESH2 0x63 00095 #define REG_LR_AGCTHRESH3 0x64 00096 #define REG_LR_PLL 0x70 00097 00098 /*! 00099 * ============================================================================ 00100 * SX1276 LoRa bits control definition 00101 * ============================================================================ 00102 */ 00103 00104 /*! 00105 * RegFifo 00106 */ 00107 00108 /*! 00109 * RegOpMode 00110 */ 00111 #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F 00112 #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default 00113 #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 00114 00115 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF 00116 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 00117 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default 00118 00119 #define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 00120 #define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default 00121 #define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 00122 00123 #define RFLR_OPMODE_MASK 0xF8 00124 #define RFLR_OPMODE_SLEEP 0x00 00125 #define RFLR_OPMODE_STANDBY 0x01 // Default 00126 #define RFLR_OPMODE_SYNTHESIZER_TX 0x02 00127 #define RFLR_OPMODE_TRANSMITTER 0x03 00128 #define RFLR_OPMODE_SYNTHESIZER_RX 0x04 00129 #define RFLR_OPMODE_RECEIVER 0x05 00130 // LoRa specific modes 00131 #define RFLR_OPMODE_RECEIVER_SINGLE 0x06 00132 #define RFLR_OPMODE_CAD 0x07 00133 00134 /*! 00135 * RegFrf (MHz) 00136 */ 00137 #define RFLR_FRFMSB_434_MHZ 0x6C // Default 00138 #define RFLR_FRFMID_434_MHZ 0x80 // Default 00139 #define RFLR_FRFLSB_434_MHZ 0x00 // Default 00140 00141 /*! 00142 * RegPaConfig 00143 */ 00144 #define RFLR_PACONFIG_PASELECT_MASK 0x7F 00145 #define RFLR_PACONFIG_PASELECT_PABOOST 0x80 00146 #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default 00147 00148 #define RFLR_PACONFIG_MAX_POWER_MASK 0x8F 00149 00150 #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 00151 00152 /*! 00153 * RegPaRamp 00154 */ 00155 #define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF 00156 #define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 00157 #define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default 00158 00159 #define RFLR_PARAMP_MASK 0xF0 00160 #define RFLR_PARAMP_3400_US 0x00 00161 #define RFLR_PARAMP_2000_US 0x01 00162 #define RFLR_PARAMP_1000_US 0x02 00163 #define RFLR_PARAMP_0500_US 0x03 00164 #define RFLR_PARAMP_0250_US 0x04 00165 #define RFLR_PARAMP_0125_US 0x05 00166 #define RFLR_PARAMP_0100_US 0x06 00167 #define RFLR_PARAMP_0062_US 0x07 00168 #define RFLR_PARAMP_0050_US 0x08 00169 #define RFLR_PARAMP_0040_US 0x09 // Default 00170 #define RFLR_PARAMP_0031_US 0x0A 00171 #define RFLR_PARAMP_0025_US 0x0B 00172 #define RFLR_PARAMP_0020_US 0x0C 00173 #define RFLR_PARAMP_0015_US 0x0D 00174 #define RFLR_PARAMP_0012_US 0x0E 00175 #define RFLR_PARAMP_0010_US 0x0F 00176 00177 /*! 00178 * RegOcp 00179 */ 00180 #define RFLR_OCP_MASK 0xDF 00181 #define RFLR_OCP_ON 0x20 // Default 00182 #define RFLR_OCP_OFF 0x00 00183 00184 #define RFLR_OCP_TRIM_MASK 0xE0 00185 #define RFLR_OCP_TRIM_045_MA 0x00 00186 #define RFLR_OCP_TRIM_050_MA 0x01 00187 #define RFLR_OCP_TRIM_055_MA 0x02 00188 #define RFLR_OCP_TRIM_060_MA 0x03 00189 #define RFLR_OCP_TRIM_065_MA 0x04 00190 #define RFLR_OCP_TRIM_070_MA 0x05 00191 #define RFLR_OCP_TRIM_075_MA 0x06 00192 #define RFLR_OCP_TRIM_080_MA 0x07 00193 #define RFLR_OCP_TRIM_085_MA 0x08 00194 #define RFLR_OCP_TRIM_090_MA 0x09 00195 #define RFLR_OCP_TRIM_095_MA 0x0A 00196 #define RFLR_OCP_TRIM_100_MA 0x0B // Default 00197 #define RFLR_OCP_TRIM_105_MA 0x0C 00198 #define RFLR_OCP_TRIM_110_MA 0x0D 00199 #define RFLR_OCP_TRIM_115_MA 0x0E 00200 #define RFLR_OCP_TRIM_120_MA 0x0F 00201 #define RFLR_OCP_TRIM_130_MA 0x10 00202 #define RFLR_OCP_TRIM_140_MA 0x11 00203 #define RFLR_OCP_TRIM_150_MA 0x12 00204 #define RFLR_OCP_TRIM_160_MA 0x13 00205 #define RFLR_OCP_TRIM_170_MA 0x14 00206 #define RFLR_OCP_TRIM_180_MA 0x15 00207 #define RFLR_OCP_TRIM_190_MA 0x16 00208 #define RFLR_OCP_TRIM_200_MA 0x17 00209 #define RFLR_OCP_TRIM_210_MA 0x18 00210 #define RFLR_OCP_TRIM_220_MA 0x19 00211 #define RFLR_OCP_TRIM_230_MA 0x1A 00212 #define RFLR_OCP_TRIM_240_MA 0x1B 00213 00214 /*! 00215 * RegLna 00216 */ 00217 #define RFLR_LNA_GAIN_MASK 0x1F 00218 #define RFLR_LNA_GAIN_G1 0x20 // Default 00219 #define RFLR_LNA_GAIN_G2 0x40 00220 #define RFLR_LNA_GAIN_G3 0x60 00221 #define RFLR_LNA_GAIN_G4 0x80 00222 #define RFLR_LNA_GAIN_G5 0xA0 00223 #define RFLR_LNA_GAIN_G6 0xC0 00224 00225 #define RFLR_LNA_BOOST_LF_MASK 0xE7 00226 #define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default 00227 00228 #define RFLR_LNA_BOOST_HF_MASK 0xFC 00229 #define RFLR_LNA_BOOST_HF_OFF 0x00 // Default 00230 #define RFLR_LNA_BOOST_HF_ON 0x03 00231 00232 /*! 00233 * RegFifoAddrPtr 00234 */ 00235 #define RFLR_FIFOADDRPTR 0x00 // Default 00236 00237 /*! 00238 * RegFifoTxBaseAddr 00239 */ 00240 #define RFLR_FIFOTXBASEADDR 0x80 // Default 00241 00242 /*! 00243 * RegFifoTxBaseAddr 00244 */ 00245 #define RFLR_FIFORXBASEADDR 0x00 // Default 00246 00247 /*! 00248 * RegFifoRxCurrentAddr (Read Only) 00249 */ 00250 00251 /*! 00252 * RegIrqFlagsMask 00253 */ 00254 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 00255 #define RFLR_IRQFLAGS_RXDONE_MASK 0x40 00256 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 00257 #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 00258 #define RFLR_IRQFLAGS_TXDONE_MASK 0x08 00259 #define RFLR_IRQFLAGS_CADDONE_MASK 0x04 00260 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 00261 #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 00262 00263 /*! 00264 * RegIrqFlags 00265 */ 00266 #define RFLR_IRQFLAGS_RXTIMEOUT 0x80 00267 #define RFLR_IRQFLAGS_RXDONE 0x40 00268 #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 00269 #define RFLR_IRQFLAGS_VALIDHEADER 0x10 00270 #define RFLR_IRQFLAGS_TXDONE 0x08 00271 #define RFLR_IRQFLAGS_CADDONE 0x04 00272 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 00273 #define RFLR_IRQFLAGS_CADDETECTED 0x01 00274 00275 /*! 00276 * RegFifoRxNbBytes (Read Only) 00277 */ 00278 00279 /*! 00280 * RegRxHeaderCntValueMsb (Read Only) 00281 */ 00282 00283 /*! 00284 * RegRxHeaderCntValueLsb (Read Only) 00285 */ 00286 00287 /*! 00288 * RegRxPacketCntValueMsb (Read Only) 00289 */ 00290 00291 /*! 00292 * RegRxPacketCntValueLsb (Read Only) 00293 */ 00294 00295 /*! 00296 * RegModemStat (Read Only) 00297 */ 00298 #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F 00299 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 00300 00301 /*! 00302 * RegPktSnrValue (Read Only) 00303 */ 00304 00305 /*! 00306 * RegPktRssiValue (Read Only) 00307 */ 00308 00309 /*! 00310 * RegRssiValue (Read Only) 00311 */ 00312 00313 /*! 00314 * RegHopChannel (Read Only) 00315 */ 00316 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F 00317 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 00318 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default 00319 00320 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF 00321 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 00322 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default 00323 00324 #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F 00325 00326 /*! 00327 * RegModemConfig1 00328 */ 00329 #define RFLR_MODEMCONFIG1_BW_MASK 0x0F 00330 #define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 00331 #define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 00332 #define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 00333 #define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 00334 #define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 00335 #define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 00336 #define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 00337 #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default 00338 #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 00339 #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 00340 00341 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 00342 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 00343 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default 00344 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 00345 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 00346 00347 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE 00348 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 00349 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default 00350 00351 /*! 00352 * RegModemConfig2 00353 */ 00354 #define RFLR_MODEMCONFIG2_SF_MASK 0x0F 00355 #define RFLR_MODEMCONFIG2_SF_6 0x60 00356 #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default 00357 #define RFLR_MODEMCONFIG2_SF_8 0x80 00358 #define RFLR_MODEMCONFIG2_SF_9 0x90 00359 #define RFLR_MODEMCONFIG2_SF_10 0xA0 00360 #define RFLR_MODEMCONFIG2_SF_11 0xB0 00361 #define RFLR_MODEMCONFIG2_SF_12 0xC0 00362 00363 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 00364 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 00365 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 00366 00367 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB 00368 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 00369 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default 00370 00371 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC 00372 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default 00373 00374 /*! 00375 * RegSymbTimeoutLsb 00376 */ 00377 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default 00378 00379 /*! 00380 * RegPreambleLengthMsb 00381 */ 00382 #define RFLR_PREAMBLELENGTHMSB 0x00 // Default 00383 00384 /*! 00385 * RegPreambleLengthLsb 00386 */ 00387 #define RFLR_PREAMBLELENGTHLSB 0x08 // Default 00388 00389 /*! 00390 * RegPayloadLength 00391 */ 00392 #define RFLR_PAYLOADLENGTH 0x0E // Default 00393 00394 /*! 00395 * RegPayloadMaxLength 00396 */ 00397 #define RFLR_PAYLOADMAXLENGTH 0xFF // Default 00398 00399 /*! 00400 * RegHopPeriod 00401 */ 00402 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default 00403 00404 /*! 00405 * RegFifoRxByteAddr (Read Only) 00406 */ 00407 00408 /*! 00409 * RegModemConfig3 00410 */ 00411 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 00412 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 00413 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default 00414 00415 #define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB 00416 #define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default 00417 #define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 00418 00419 /*! 00420 * RegFeiMsb (Read Only) 00421 */ 00422 00423 /*! 00424 * RegFeiMid (Read Only) 00425 */ 00426 00427 /*! 00428 * RegFeiLsb (Read Only) 00429 */ 00430 00431 /*! 00432 * RegRssiWideband (Read Only) 00433 */ 00434 00435 /*! 00436 * RegDetectOptimize 00437 */ 00438 #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 00439 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default 00440 #define RFLR_DETECTIONOPTIMIZE_SF6 0x05 00441 00442 /*! 00443 * RegInvertIQ 00444 */ 00445 #define RFLR_INVERTIQ_RX_MASK 0xBF 00446 #define RFLR_INVERTIQ_RX_OFF 0x00 00447 #define RFLR_INVERTIQ_RX_ON 0x40 00448 #define RFLR_INVERTIQ_TX_MASK 0xFE 00449 #define RFLR_INVERTIQ_TX_OFF 0x01 00450 #define RFLR_INVERTIQ_TX_ON 0x00 00451 00452 /*! 00453 * RegDetectionThreshold 00454 */ 00455 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default 00456 #define RFLR_DETECTIONTHRESH_SF6 0x0C 00457 00458 /*! 00459 * RegInvertIQ2 00460 */ 00461 #define RFLR_INVERTIQ2_ON 0x19 00462 #define RFLR_INVERTIQ2_OFF 0x1D 00463 00464 /*! 00465 * RegDioMapping1 00466 */ 00467 #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F 00468 #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default 00469 #define RFLR_DIOMAPPING1_DIO0_01 0x40 00470 #define RFLR_DIOMAPPING1_DIO0_10 0x80 00471 #define RFLR_DIOMAPPING1_DIO0_11 0xC0 00472 00473 #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF 00474 #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default 00475 #define RFLR_DIOMAPPING1_DIO1_01 0x10 00476 #define RFLR_DIOMAPPING1_DIO1_10 0x20 00477 #define RFLR_DIOMAPPING1_DIO1_11 0x30 00478 00479 #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 00480 #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default 00481 #define RFLR_DIOMAPPING1_DIO2_01 0x04 00482 #define RFLR_DIOMAPPING1_DIO2_10 0x08 00483 #define RFLR_DIOMAPPING1_DIO2_11 0x0C 00484 00485 #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC 00486 #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default 00487 #define RFLR_DIOMAPPING1_DIO3_01 0x01 00488 #define RFLR_DIOMAPPING1_DIO3_10 0x02 00489 #define RFLR_DIOMAPPING1_DIO3_11 0x03 00490 00491 /*! 00492 * RegDioMapping2 00493 */ 00494 #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F 00495 #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default 00496 #define RFLR_DIOMAPPING2_DIO4_01 0x40 00497 #define RFLR_DIOMAPPING2_DIO4_10 0x80 00498 #define RFLR_DIOMAPPING2_DIO4_11 0xC0 00499 00500 #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF 00501 #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default 00502 #define RFLR_DIOMAPPING2_DIO5_01 0x10 00503 #define RFLR_DIOMAPPING2_DIO5_10 0x20 00504 #define RFLR_DIOMAPPING2_DIO5_11 0x30 00505 00506 #define RFLR_DIOMAPPING2_MAP_MASK 0xFE 00507 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 00508 #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default 00509 00510 /*! 00511 * RegVersion (Read Only) 00512 */ 00513 00514 /*! 00515 * RegPllHop 00516 */ 00517 #define RFLR_PLLHOP_FASTHOP_MASK 0x7F 00518 #define RFLR_PLLHOP_FASTHOP_ON 0x80 00519 #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default 00520 00521 /*! 00522 * RegTcxo 00523 */ 00524 #define RFLR_TCXO_TCXOINPUT_MASK 0xEF 00525 #define RFLR_TCXO_TCXOINPUT_ON 0x10 00526 #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default 00527 00528 /*! 00529 * RegPaDac 00530 */ 00531 #define RFLR_PADAC_20DBM_MASK 0xF8 00532 #define RFLR_PADAC_20DBM_ON 0x07 00533 #define RFLR_PADAC_20DBM_OFF 0x04 // Default 00534 00535 /*! 00536 * RegFormerTemp 00537 */ 00538 00539 /*! 00540 * RegBitrateFrac 00541 */ 00542 #define RF_BITRATEFRAC_MASK 0xF0 00543 00544 /*! 00545 * RegAgcRef 00546 */ 00547 00548 /*! 00549 * RegAgcThresh1 00550 */ 00551 00552 /*! 00553 * RegAgcThresh2 00554 */ 00555 00556 /*! 00557 * RegAgcThresh3 00558 */ 00559 00560 /*! 00561 * RegPll 00562 */ 00563 #define RF_PLL_BANDWIDTH_MASK 0x3F 00564 #define RF_PLL_BANDWIDTH_75 0x00 00565 #define RF_PLL_BANDWIDTH_150 0x40 00566 #define RF_PLL_BANDWIDTH_225 0x80 00567 #define RF_PLL_BANDWIDTH_300 0xC0 // Default 00568 00569 #endif // __SX1276_REGS_LORA_H__
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