stephen mathenge
/
Level_estimation_Maesurement
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Dependencies: Cayenne-LPP SDBlockDevice
Embed:
(wiki syntax)
Show/hide line numbers
sx1272Regs-LoRa.h
00001 /** 00002 / _____) _ | | 00003 ( (____ _____ ____ _| |_ _____ ____| |__ 00004 \____ \| ___ | (_ _) ___ |/ ___) _ \ 00005 _____) ) ____| | | || |_| ____( (___| | | | 00006 (______/|_____)_|_|_| \__)_____)\____)_| |_| 00007 (C) 2015 Semtech 00008 00009 Description: SX1272 LoRa modem registers and bits definitions 00010 00011 License: Revised BSD License, see LICENSE.TXT file include in the project 00012 00013 Maintainer: Miguel Luis and Gregory Cristian 00014 00015 Copyright (c) 2017, Arm Limited and affiliates. 00016 00017 SPDX-License-Identifier: BSD-3-Clause 00018 */ 00019 #ifndef __SX1272_REGS_LORA_H__ 00020 #define __SX1272_REGS_LORA_H__ 00021 00022 /*! 00023 * ============================================================================ 00024 * SX1272 Internal registers Address 00025 * ============================================================================ 00026 */ 00027 #define REG_LR_FIFO 0x00 00028 // Common settings 00029 #define REG_LR_OPMODE 0x01 00030 #define REG_LR_FRFMSB 0x06 00031 #define REG_LR_FRFMID 0x07 00032 #define REG_LR_FRFLSB 0x08 00033 // Tx settings 00034 #define REG_LR_PACONFIG 0x09 00035 #define REG_LR_PARAMP 0x0A 00036 #define REG_LR_OCP 0x0B 00037 // Rx settings 00038 #define REG_LR_LNA 0x0C 00039 // LoRa registers 00040 #define REG_LR_FIFOADDRPTR 0x0D 00041 #define REG_LR_FIFOTXBASEADDR 0x0E 00042 #define REG_LR_FIFORXBASEADDR 0x0F 00043 #define REG_LR_FIFORXCURRENTADDR 0x10 00044 #define REG_LR_IRQFLAGSMASK 0x11 00045 #define REG_LR_IRQFLAGS 0x12 00046 #define REG_LR_RXNBBYTES 0x13 00047 #define REG_LR_RXHEADERCNTVALUEMSB 0x14 00048 #define REG_LR_RXHEADERCNTVALUELSB 0x15 00049 #define REG_LR_RXPACKETCNTVALUEMSB 0x16 00050 #define REG_LR_RXPACKETCNTVALUELSB 0x17 00051 #define REG_LR_MODEMSTAT 0x18 00052 #define REG_LR_PKTSNRVALUE 0x19 00053 #define REG_LR_PKTRSSIVALUE 0x1A 00054 #define REG_LR_RSSIVALUE 0x1B 00055 #define REG_LR_HOPCHANNEL 0x1C 00056 #define REG_LR_MODEMCONFIG1 0x1D 00057 #define REG_LR_MODEMCONFIG2 0x1E 00058 #define REG_LR_SYMBTIMEOUTLSB 0x1F 00059 #define REG_LR_PREAMBLEMSB 0x20 00060 #define REG_LR_PREAMBLELSB 0x21 00061 #define REG_LR_PAYLOADLENGTH 0x22 00062 #define REG_LR_PAYLOADMAXLENGTH 0x23 00063 #define REG_LR_HOPPERIOD 0x24 00064 #define REG_LR_FIFORXBYTEADDR 0x25 00065 #define REG_LR_FEIMSB 0x28 00066 #define REG_LR_FEIMID 0x29 00067 #define REG_LR_FEILSB 0x2A 00068 #define REG_LR_RSSIWIDEBAND 0x2C 00069 #define REG_LR_DETECTOPTIMIZE 0x31 00070 #define REG_LR_INVERTIQ 0x33 00071 #define REG_LR_DETECTIONTHRESHOLD 0x37 00072 #define REG_LR_SYNCWORD 0x39 00073 #define REG_LR_INVERTIQ2 0x3B 00074 00075 // end of documented register in datasheet 00076 // I/O settings 00077 #define REG_LR_DIOMAPPING1 0x40 00078 #define REG_LR_DIOMAPPING2 0x41 00079 // Version 00080 #define REG_LR_VERSION 0x42 00081 // Additional settings 00082 #define REG_LR_AGCREF 0x43 00083 #define REG_LR_AGCTHRESH1 0x44 00084 #define REG_LR_AGCTHRESH2 0x45 00085 #define REG_LR_AGCTHRESH3 0x46 00086 #define REG_LR_PLLHOP 0x4B 00087 #define REG_LR_TCXO 0x58 00088 #define REG_LR_PADAC 0x5A 00089 #define REG_LR_PLL 0x5C 00090 #define REG_LR_PLLLOWPN 0x5E 00091 #define REG_LR_FORMERTEMP 0x6C 00092 00093 /*! 00094 * ============================================================================ 00095 * SX1272 LoRa bits control definition 00096 * ============================================================================ 00097 */ 00098 00099 /*! 00100 * RegFifo 00101 */ 00102 00103 /*! 00104 * RegOpMode 00105 */ 00106 #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F 00107 #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default 00108 #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 00109 00110 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF 00111 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 00112 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default 00113 00114 #define RFLR_OPMODE_MASK 0xF8 00115 #define RFLR_OPMODE_SLEEP 0x00 00116 #define RFLR_OPMODE_STANDBY 0x01 // Default 00117 #define RFLR_OPMODE_SYNTHESIZER_TX 0x02 00118 #define RFLR_OPMODE_TRANSMITTER 0x03 00119 #define RFLR_OPMODE_SYNTHESIZER_RX 0x04 00120 #define RFLR_OPMODE_RECEIVER 0x05 00121 // LoRa specific modes 00122 #define RFLR_OPMODE_RECEIVER_SINGLE 0x06 00123 #define RFLR_OPMODE_CAD 0x07 00124 00125 /*! 00126 * RegFrf (MHz) 00127 */ 00128 #define RFLR_FRFMSB_915_MHZ 0xE4 // Default 00129 #define RFLR_FRFMID_915_MHZ 0xC0 // Default 00130 #define RFLR_FRFLSB_915_MHZ 0x00 // Default 00131 00132 /*! 00133 * RegPaConfig 00134 */ 00135 #define RFLR_PACONFIG_PASELECT_MASK 0x7F 00136 #define RFLR_PACONFIG_PASELECT_PABOOST 0x80 00137 #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default 00138 00139 #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 00140 00141 /*! 00142 * RegPaRamp 00143 */ 00144 #define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0 00145 #define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default 00146 #define RFLR_PARAMP_LOWPNTXPLL_ON 0x00 00147 00148 #define RFLR_PARAMP_MASK 0xF0 00149 #define RFLR_PARAMP_3400_US 0x00 00150 #define RFLR_PARAMP_2000_US 0x01 00151 #define RFLR_PARAMP_1000_US 0x02 00152 #define RFLR_PARAMP_0500_US 0x03 00153 #define RFLR_PARAMP_0250_US 0x04 00154 #define RFLR_PARAMP_0125_US 0x05 00155 #define RFLR_PARAMP_0100_US 0x06 00156 #define RFLR_PARAMP_0062_US 0x07 00157 #define RFLR_PARAMP_0050_US 0x08 00158 #define RFLR_PARAMP_0040_US 0x09 // Default 00159 #define RFLR_PARAMP_0031_US 0x0A 00160 #define RFLR_PARAMP_0025_US 0x0B 00161 #define RFLR_PARAMP_0020_US 0x0C 00162 #define RFLR_PARAMP_0015_US 0x0D 00163 #define RFLR_PARAMP_0012_US 0x0E 00164 #define RFLR_PARAMP_0010_US 0x0F 00165 00166 /*! 00167 * RegOcp 00168 */ 00169 #define RFLR_OCP_MASK 0xDF 00170 #define RFLR_OCP_ON 0x20 // Default 00171 #define RFLR_OCP_OFF 0x00 00172 00173 #define RFLR_OCP_TRIM_MASK 0xE0 00174 #define RFLR_OCP_TRIM_045_MA 0x00 00175 #define RFLR_OCP_TRIM_050_MA 0x01 00176 #define RFLR_OCP_TRIM_055_MA 0x02 00177 #define RFLR_OCP_TRIM_060_MA 0x03 00178 #define RFLR_OCP_TRIM_065_MA 0x04 00179 #define RFLR_OCP_TRIM_070_MA 0x05 00180 #define RFLR_OCP_TRIM_075_MA 0x06 00181 #define RFLR_OCP_TRIM_080_MA 0x07 00182 #define RFLR_OCP_TRIM_085_MA 0x08 00183 #define RFLR_OCP_TRIM_090_MA 0x09 00184 #define RFLR_OCP_TRIM_095_MA 0x0A 00185 #define RFLR_OCP_TRIM_100_MA 0x0B // Default 00186 #define RFLR_OCP_TRIM_105_MA 0x0C 00187 #define RFLR_OCP_TRIM_110_MA 0x0D 00188 #define RFLR_OCP_TRIM_115_MA 0x0E 00189 #define RFLR_OCP_TRIM_120_MA 0x0F 00190 #define RFLR_OCP_TRIM_130_MA 0x10 00191 #define RFLR_OCP_TRIM_140_MA 0x11 00192 #define RFLR_OCP_TRIM_150_MA 0x12 00193 #define RFLR_OCP_TRIM_160_MA 0x13 00194 #define RFLR_OCP_TRIM_170_MA 0x14 00195 #define RFLR_OCP_TRIM_180_MA 0x15 00196 #define RFLR_OCP_TRIM_190_MA 0x16 00197 #define RFLR_OCP_TRIM_200_MA 0x17 00198 #define RFLR_OCP_TRIM_210_MA 0x18 00199 #define RFLR_OCP_TRIM_220_MA 0x19 00200 #define RFLR_OCP_TRIM_230_MA 0x1A 00201 #define RFLR_OCP_TRIM_240_MA 0x1B 00202 00203 /*! 00204 * RegLna 00205 */ 00206 #define RFLR_LNA_GAIN_MASK 0x1F 00207 #define RFLR_LNA_GAIN_G1 0x20 // Default 00208 #define RFLR_LNA_GAIN_G2 0x40 00209 #define RFLR_LNA_GAIN_G3 0x60 00210 #define RFLR_LNA_GAIN_G4 0x80 00211 #define RFLR_LNA_GAIN_G5 0xA0 00212 #define RFLR_LNA_GAIN_G6 0xC0 00213 00214 #define RFLR_LNA_BOOST_MASK 0xFC 00215 #define RFLR_LNA_BOOST_OFF 0x00 // Default 00216 #define RFLR_LNA_BOOST_ON 0x03 00217 00218 /*! 00219 * RegFifoAddrPtr 00220 */ 00221 #define RFLR_FIFOADDRPTR 0x00 // Default 00222 00223 /*! 00224 * RegFifoTxBaseAddr 00225 */ 00226 #define RFLR_FIFOTXBASEADDR 0x80 // Default 00227 00228 /*! 00229 * RegFifoTxBaseAddr 00230 */ 00231 #define RFLR_FIFORXBASEADDR 0x00 // Default 00232 00233 /*! 00234 * RegFifoRxCurrentAddr (Read Only) 00235 */ 00236 00237 /*! 00238 * RegIrqFlagsMask 00239 */ 00240 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 00241 #define RFLR_IRQFLAGS_RXDONE_MASK 0x40 00242 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 00243 #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 00244 #define RFLR_IRQFLAGS_TXDONE_MASK 0x08 00245 #define RFLR_IRQFLAGS_CADDONE_MASK 0x04 00246 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 00247 #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 00248 00249 /*! 00250 * RegIrqFlags 00251 */ 00252 #define RFLR_IRQFLAGS_RXTIMEOUT 0x80 00253 #define RFLR_IRQFLAGS_RXDONE 0x40 00254 #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 00255 #define RFLR_IRQFLAGS_VALIDHEADER 0x10 00256 #define RFLR_IRQFLAGS_TXDONE 0x08 00257 #define RFLR_IRQFLAGS_CADDONE 0x04 00258 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 00259 #define RFLR_IRQFLAGS_CADDETECTED 0x01 00260 00261 /*! 00262 * RegFifoRxNbBytes (Read Only) 00263 */ 00264 00265 /*! 00266 * RegRxHeaderCntValueMsb (Read Only) 00267 */ 00268 00269 /*! 00270 * RegRxHeaderCntValueLsb (Read Only) 00271 */ 00272 00273 /*! 00274 * RegRxPacketCntValueMsb (Read Only) 00275 */ 00276 00277 /*! 00278 * RegRxPacketCntValueLsb (Read Only) 00279 */ 00280 00281 /*! 00282 * RegModemStat (Read Only) 00283 */ 00284 #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F 00285 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 00286 00287 /*! 00288 * RegPktSnrValue (Read Only) 00289 */ 00290 00291 /*! 00292 * RegPktRssiValue (Read Only) 00293 */ 00294 00295 /*! 00296 * RegRssiValue (Read Only) 00297 */ 00298 00299 /*! 00300 * RegHopChannel (Read Only) 00301 */ 00302 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F 00303 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 00304 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default 00305 00306 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF 00307 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 00308 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default 00309 00310 #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F 00311 00312 /*! 00313 * RegModemConfig1 00314 */ 00315 #define RFLR_MODEMCONFIG1_BW_MASK 0x3F 00316 #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default 00317 #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40 00318 #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80 00319 00320 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7 00321 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08 00322 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default 00323 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18 00324 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20 00325 00326 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB 00327 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04 00328 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default 00329 00330 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD 00331 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02 00332 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default 00333 00334 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE 00335 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01 00336 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default 00337 00338 /*! 00339 * RegModemConfig2 00340 */ 00341 #define RFLR_MODEMCONFIG2_SF_MASK 0x0F 00342 #define RFLR_MODEMCONFIG2_SF_6 0x60 00343 #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default 00344 #define RFLR_MODEMCONFIG2_SF_8 0x80 00345 #define RFLR_MODEMCONFIG2_SF_9 0x90 00346 #define RFLR_MODEMCONFIG2_SF_10 0xA0 00347 #define RFLR_MODEMCONFIG2_SF_11 0xB0 00348 #define RFLR_MODEMCONFIG2_SF_12 0xC0 00349 00350 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 00351 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 00352 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 00353 00354 #define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB 00355 #define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default 00356 #define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00 00357 00358 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC 00359 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default 00360 00361 /*! 00362 * RegSymbTimeoutLsb 00363 */ 00364 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default 00365 00366 /*! 00367 * RegPreambleLengthMsb 00368 */ 00369 #define RFLR_PREAMBLELENGTHMSB 0x00 // Default 00370 00371 /*! 00372 * RegPreambleLengthLsb 00373 */ 00374 #define RFLR_PREAMBLELENGTHLSB 0x08 // Default 00375 00376 /*! 00377 * RegPayloadLength 00378 */ 00379 #define RFLR_PAYLOADLENGTH 0x0E // Default 00380 00381 /*! 00382 * RegPayloadMaxLength 00383 */ 00384 #define RFLR_PAYLOADMAXLENGTH 0xFF // Default 00385 00386 /*! 00387 * RegHopPeriod 00388 */ 00389 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default 00390 00391 /*! 00392 * RegFifoRxByteAddr (Read Only) 00393 */ 00394 00395 /*! 00396 * RegFeiMsb (Read Only) 00397 */ 00398 00399 /*! 00400 * RegFeiMid (Read Only) 00401 */ 00402 00403 /*! 00404 * RegFeiLsb (Read Only) 00405 */ 00406 00407 /*! 00408 * RegRssiWideband (Read Only) 00409 */ 00410 00411 /*! 00412 * RegDetectOptimize 00413 */ 00414 #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 00415 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default 00416 #define RFLR_DETECTIONOPTIMIZE_SF6 0x05 00417 00418 /*! 00419 * RegInvertIQ 00420 */ 00421 #define RFLR_INVERTIQ_RX_MASK 0xBF 00422 #define RFLR_INVERTIQ_RX_OFF 0x00 00423 #define RFLR_INVERTIQ_RX_ON 0x40 00424 #define RFLR_INVERTIQ_TX_MASK 0xFE 00425 #define RFLR_INVERTIQ_TX_OFF 0x01 00426 #define RFLR_INVERTIQ_TX_ON 0x00 00427 00428 /*! 00429 * RegDetectionThreshold 00430 */ 00431 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default 00432 #define RFLR_DETECTIONTHRESH_SF6 0x0C 00433 00434 /*! 00435 * RegInvertIQ2 00436 */ 00437 #define RFLR_INVERTIQ2_ON 0x19 00438 #define RFLR_INVERTIQ2_OFF 0x1D 00439 00440 /*! 00441 * RegDioMapping1 00442 */ 00443 #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F 00444 #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default 00445 #define RFLR_DIOMAPPING1_DIO0_01 0x40 00446 #define RFLR_DIOMAPPING1_DIO0_10 0x80 00447 #define RFLR_DIOMAPPING1_DIO0_11 0xC0 00448 00449 #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF 00450 #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default 00451 #define RFLR_DIOMAPPING1_DIO1_01 0x10 00452 #define RFLR_DIOMAPPING1_DIO1_10 0x20 00453 #define RFLR_DIOMAPPING1_DIO1_11 0x30 00454 00455 #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 00456 #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default 00457 #define RFLR_DIOMAPPING1_DIO2_01 0x04 00458 #define RFLR_DIOMAPPING1_DIO2_10 0x08 00459 #define RFLR_DIOMAPPING1_DIO2_11 0x0C 00460 00461 #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC 00462 #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default 00463 #define RFLR_DIOMAPPING1_DIO3_01 0x01 00464 #define RFLR_DIOMAPPING1_DIO3_10 0x02 00465 #define RFLR_DIOMAPPING1_DIO3_11 0x03 00466 00467 /*! 00468 * RegDioMapping2 00469 */ 00470 #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F 00471 #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default 00472 #define RFLR_DIOMAPPING2_DIO4_01 0x40 00473 #define RFLR_DIOMAPPING2_DIO4_10 0x80 00474 #define RFLR_DIOMAPPING2_DIO4_11 0xC0 00475 00476 #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF 00477 #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default 00478 #define RFLR_DIOMAPPING2_DIO5_01 0x10 00479 #define RFLR_DIOMAPPING2_DIO5_10 0x20 00480 #define RFLR_DIOMAPPING2_DIO5_11 0x30 00481 00482 #define RFLR_DIOMAPPING2_MAP_MASK 0xFE 00483 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 00484 #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default 00485 00486 /*! 00487 * RegVersion (Read Only) 00488 */ 00489 00490 /*! 00491 * RegAgcRef 00492 */ 00493 00494 /*! 00495 * RegAgcThresh1 00496 */ 00497 00498 /*! 00499 * RegAgcThresh2 00500 */ 00501 00502 /*! 00503 * RegAgcThresh3 00504 */ 00505 00506 /*! 00507 * RegPllHop 00508 */ 00509 #define RFLR_PLLHOP_FASTHOP_MASK 0x7F 00510 #define RFLR_PLLHOP_FASTHOP_ON 0x80 00511 #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default 00512 00513 /*! 00514 * RegTcxo 00515 */ 00516 #define RFLR_TCXO_TCXOINPUT_MASK 0xEF 00517 #define RFLR_TCXO_TCXOINPUT_ON 0x10 00518 #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default 00519 00520 /*! 00521 * RegPaDac 00522 */ 00523 #define RFLR_PADAC_20DBM_MASK 0xF8 00524 #define RFLR_PADAC_20DBM_ON 0x07 00525 #define RFLR_PADAC_20DBM_OFF 0x04 // Default 00526 00527 /*! 00528 * RegPll 00529 */ 00530 #define RFLR_PLL_BANDWIDTH_MASK 0x3F 00531 #define RFLR_PLL_BANDWIDTH_75 0x00 00532 #define RFLR_PLL_BANDWIDTH_150 0x40 00533 #define RFLR_PLL_BANDWIDTH_225 0x80 00534 #define RFLR_PLL_BANDWIDTH_300 0xC0 // Default 00535 00536 /*! 00537 * RegPllLowPn 00538 */ 00539 #define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F 00540 #define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 00541 #define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 00542 #define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 00543 #define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default 00544 00545 /*! 00546 * RegFormerTemp 00547 */ 00548 00549 #endif // __SX1272_REGS_LORA_H__
Generated on Sat Jul 16 2022 05:24:58 by
1.7.2